Merge branch 'remotes/lorenzo/pci/misc'
- Remove IRQ handler & data together for altera, brcmstb, dwc (Martin Kaiser) - Fix xgene race in installing chained IRQ handler (Martin Kaiser) - Drop PCIE_RCAR config option (replaced by PCIE_RCAR_HOST) (Lad Prabhakar) - Fix xgene comment about CRS vs CRS SV (Bjorn Helgaas) * remotes/lorenzo/pci/misc: PCI: hv: Fix typo PCI: xgene: Fix CRS SV comment PCI: brcmstb: Remove chained IRQ handler and data in one go PCI: Drop PCIE_RCAR config option PCI: xgene-msi: Fix race in installing chained irq handler PCI: dwc: Remove IRQ handler and data in one go PCI: altera-msi: Remove IRQ handler and data in one go
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Коммит
e18fb64b79
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@ -55,15 +55,6 @@ config PCI_RCAR_GEN2
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There are 3 internal PCI controllers available with a single
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built-in EHCI/OHCI host controller present on each one.
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config PCIE_RCAR
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bool "Renesas R-Car PCIe controller"
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depends on ARCH_RENESAS || COMPILE_TEST
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_RCAR_HOST
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help
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Say Y here if you want PCIe controller support on R-Car SoCs.
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This option will be removed after arm64 defconfig is updated.
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config PCIE_RCAR_HOST
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bool "Renesas R-Car PCIe host controller"
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depends on ARCH_RENESAS || COMPILE_TEST
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@ -258,10 +258,8 @@ int dw_pcie_allocate_domains(struct pcie_port *pp)
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static void dw_pcie_free_msi(struct pcie_port *pp)
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{
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if (pp->msi_irq) {
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irq_set_chained_handler(pp->msi_irq, NULL);
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irq_set_handler_data(pp->msi_irq, NULL);
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}
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if (pp->msi_irq)
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irq_set_chained_handler_and_data(pp->msi_irq, NULL, NULL);
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irq_domain_remove(pp->msi_domain);
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irq_domain_remove(pp->irq_domain);
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@ -1714,7 +1714,7 @@ static void prepopulate_bars(struct hv_pcibus_device *hbus)
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* resumed and suspended again: see hibernation_snapshot() and
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* hibernation_platform_enter().
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*
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* If the memory enable bit is already set, Hyper-V sliently ignores
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* If the memory enable bit is already set, Hyper-V silently ignores
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* the below BAR updates, and the related PCI device driver can not
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* work, because reading from the device register(s) always returns
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* 0xFFFFFFFF.
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@ -384,13 +384,9 @@ static int xgene_msi_hwirq_alloc(unsigned int cpu)
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if (!msi_group->gic_irq)
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continue;
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irq_set_chained_handler(msi_group->gic_irq,
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xgene_msi_isr);
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err = irq_set_handler_data(msi_group->gic_irq, msi_group);
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if (err) {
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pr_err("failed to register GIC IRQ handler\n");
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return -EINVAL;
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}
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irq_set_chained_handler_and_data(msi_group->gic_irq,
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xgene_msi_isr, msi_group);
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/*
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* Statically allocate MSI GIC IRQs to each CPU core.
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* With 8-core X-Gene v1, 2 MSI GIC IRQs are allocated
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@ -173,12 +173,13 @@ static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
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/*
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* The v1 controller has a bug in its Configuration Request
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* Retry Status (CRS) logic: when CRS is enabled and we read the
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* Vendor and Device ID of a non-existent device, the controller
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* fabricates return data of 0xFFFF0001 ("device exists but is not
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* ready") instead of 0xFFFFFFFF ("device does not exist"). This
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* causes the PCI core to retry the read until it times out.
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* Avoid this by not claiming to support CRS.
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* Retry Status (CRS) logic: when CRS Software Visibility is
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* enabled and we read the Vendor and Device ID of a non-existent
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* device, the controller fabricates return data of 0xFFFF0001
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* ("device exists but is not ready") instead of 0xFFFFFFFF
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* ("device does not exist"). This causes the PCI core to retry
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* the read until it times out. Avoid this by not claiming to
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* support CRS SV.
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*/
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if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) &&
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((where & ~0x3) == XGENE_V1_PCI_EXP_CAP + PCI_EXP_RTCTL))
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@ -204,8 +204,7 @@ static int altera_msi_remove(struct platform_device *pdev)
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struct altera_msi *msi = platform_get_drvdata(pdev);
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msi_writel(msi, 0, MSI_INTMASK);
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irq_set_chained_handler(msi->irq, NULL);
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irq_set_handler_data(msi->irq, NULL);
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irq_set_chained_handler_and_data(msi->irq, NULL, NULL);
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altera_free_domains(msi);
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@ -614,8 +614,7 @@ static void brcm_msi_remove(struct brcm_pcie *pcie)
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if (!msi)
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return;
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irq_set_chained_handler(msi->irq, NULL);
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irq_set_handler_data(msi->irq, NULL);
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irq_set_chained_handler_and_data(msi->irq, NULL, NULL);
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brcm_free_domains(msi);
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}
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