ARM64 fixes:

- Exception level check at boot time (for completeness, not triggering
   any bug before)
 - I/D-cache synchronisation logic for huge pages
 - Config symbol typo
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.9 (GNU/Linux)
 
 iQIcBAABAgAGBQJTt+DiAAoJEGvWsS0AyF7xufkP/RLthhgr6OJJW2UF1uLKa4VC
 ouRCPLsMvTk8KGOOYOq//2tnM0B3ZR5489YQouiVA9a0QW6R1QNkGeWdB9q/6hyG
 YhfS+yRyq4+xtv1qKrwD2LF2AJ9Wb6q6E4NwkuqNiYQN4c9npImouZ70PZRqj7Qw
 y8xf1mstaIiQZBqfkIt6o6lKBwlFPvcXrDLEwG4leg03AetbW9OkLaSOTtSOIHw3
 jHwpiKonKhN0j1gzJp4quLLu6NtdiFeNmXv0qSRdX+sRQpkSkO8cV0bSWNiEO501
 W2allUz9a9rY+zkYXByIoJNe04lrTPYye+rc4TtCnGXp+rE82aIz6hHLPFGzfnGH
 j2uBJZho90uY23wN/sxtfTlXvRnYpni9jb+dtQGa2GkcB/hlh+4+ge2BCJ7EjDN8
 n0UZGMRLa3odi+t5n3cSt+jNnjCimtrDbFsq+Zs97QMV/0T2XjV1rwGsZKXj2EDR
 7EFm5dAR/9OjTmy7DCEQOcsiyBpvH2X0rJeE44SoVWTY/qIoebVnwsDxsExK3wn8
 6AdYGEg4eZefC2sELoTPddP1FquUd7sFr+AIfvclmrgaoaWH34i1UMe7vmvODeki
 5Mt85cg2qhKLE5+EOfMdzB6ztazRkY1Kw7t7vghSpW3Q0Q1lteuHAfLVlEAOuzT7
 cDeJrERLoJJ4xTjDZ9a+
 =1PCg
 -----END PGP SIGNATURE-----

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull ARM64 fixes from Catalin Marinas:
 - Exception level check at boot time (for completeness, not triggering
   any bug before)
 - I/D-cache synchronisation logic for huge pages
 - Config symbol typo

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: fix el2_setup check of CurrentEL
  arm64: mm: Make icache synchronisation logic huge page aware
  arm64: mm: Fix horrendous config typo

arch/arm64/include/asm/pgtable.h

@@ -292,7 +292,7 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 #define pmd_sect(pmd)		((pmd_val(pmd) & PMD_TYPE_MASK) == \
 				 PMD_TYPE_SECT)
 
-#ifdef ARM64_64K_PAGES
+#ifdef CONFIG_ARM64_64K_PAGES
 #define pud_sect(pud)		(0)
 #else
 #define pud_sect(pud)		((pud_val(pud) & PUD_TYPE_MASK) == \

arch/arm64/include/asm/ptrace.h

@@ -21,6 +21,10 @@
 
 #include <uapi/asm/ptrace.h>
 
+/* Current Exception Level values, as contained in CurrentEL */
+#define CurrentEL_EL1		(1 << 2)
+#define CurrentEL_EL2		(2 << 2)
+
 /* AArch32-specific ptrace requests */
 #define COMPAT_PTRACE_GETREGS		12
 #define COMPAT_PTRACE_SETREGS		13

arch/arm64/kernel/efi-entry.S

@@ -78,8 +78,7 @@ ENTRY(efi_stub_entry)
 
 	/* Turn off Dcache and MMU */
 	mrs	x0, CurrentEL
-	cmp	x0, #PSR_MODE_EL2t
-	ccmp	x0, #PSR_MODE_EL2h, #0x4, ne
+	cmp	x0, #CurrentEL_EL2
 	b.ne	1f
 	mrs	x0, sctlr_el2
 	bic	x0, x0, #1 << 0	// clear SCTLR.M

arch/arm64/kernel/head.S

@@ -270,8 +270,7 @@ ENDPROC(stext)
  */
 ENTRY(el2_setup)
 	mrs	x0, CurrentEL
-	cmp	x0, #PSR_MODE_EL2t
-	ccmp	x0, #PSR_MODE_EL2h, #0x4, ne
+	cmp	x0, #CurrentEL_EL2
 	b.ne	1f
 	mrs	x0, sctlr_el2
 CPU_BE(	orr	x0, x0, #(1 << 25)	)	// Set the EE bit for EL2

arch/arm64/mm/flush.c

@@ -79,7 +79,8 @@ void __sync_icache_dcache(pte_t pte, unsigned long addr)
 		return;
 
 	if (!test_and_set_bit(PG_dcache_clean, &page->flags)) {
-		__flush_dcache_area(page_address(page), PAGE_SIZE);
+		__flush_dcache_area(page_address(page),
+				PAGE_SIZE << compound_order(page));
 		__flush_icache_all();
 	} else if (icache_is_aivivt()) {
 		__flush_icache_all();