x86/fpu: Factor out the exception error code handling code
Factor out the FPU error code handling code from traps.c and fpu/internal.h and move them close to each other. Also convert the helper functions to 'struct fpu *', which further simplifies them. Cc: Andy Lutomirski <luto@amacapital.net> Cc: Borislav Petkov <bp@alien8.de> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Oleg Nesterov <oleg@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Ingo Molnar
Родитель
acd58a3ad0
Коммит
e1cebad49c
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@ -30,7 +30,8 @@ extern void fpu__init_system(struct cpuinfo_x86 *c);
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extern void fpu__activate_curr(struct fpu *fpu);
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extern void fpstate_init(struct fpu *fpu);
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extern int dump_fpu(struct pt_regs *, struct user_i387_struct *);
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extern int dump_fpu(struct pt_regs *, struct user_i387_struct *);
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extern int fpu__exception_code(struct fpu *fpu, int trap_nr);
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/*
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* High level FPU state handling functions:
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@ -467,34 +468,4 @@ static inline void user_fpu_begin(void)
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preempt_enable();
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}
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/*
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* i387 state interaction
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*/
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static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
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{
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if (cpu_has_fxsr) {
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return tsk->thread.fpu.state.fxsave.cwd;
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} else {
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return (unsigned short)tsk->thread.fpu.state.fsave.cwd;
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}
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}
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static inline unsigned short get_fpu_swd(struct task_struct *tsk)
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{
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if (cpu_has_fxsr) {
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return tsk->thread.fpu.state.fxsave.swd;
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} else {
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return (unsigned short)tsk->thread.fpu.state.fsave.swd;
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}
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}
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static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
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{
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if (cpu_has_xmm) {
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return tsk->thread.fpu.state.fxsave.mxcsr;
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} else {
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return MXCSR_DEFAULT;
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}
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}
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#endif /* _ASM_X86_FPU_INTERNAL_H */
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@ -8,6 +8,7 @@
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#include <asm/fpu/internal.h>
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#include <asm/fpu/regset.h>
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#include <asm/fpu/signal.h>
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#include <asm/traps.h>
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#include <linux/hardirq.h>
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@ -749,3 +750,90 @@ int dump_fpu(struct pt_regs *regs, struct user_i387_struct *ufpu)
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EXPORT_SYMBOL(dump_fpu);
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#endif /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */
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/*
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* x87 math exception handling:
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*/
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static inline unsigned short get_fpu_cwd(struct fpu *fpu)
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{
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if (cpu_has_fxsr) {
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return fpu->state.fxsave.cwd;
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} else {
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return (unsigned short)fpu->state.fsave.cwd;
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}
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}
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static inline unsigned short get_fpu_swd(struct fpu *fpu)
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{
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if (cpu_has_fxsr) {
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return fpu->state.fxsave.swd;
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} else {
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return (unsigned short)fpu->state.fsave.swd;
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}
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}
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static inline unsigned short get_fpu_mxcsr(struct fpu *fpu)
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{
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if (cpu_has_xmm) {
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return fpu->state.fxsave.mxcsr;
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} else {
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return MXCSR_DEFAULT;
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}
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}
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int fpu__exception_code(struct fpu *fpu, int trap_nr)
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{
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int err;
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if (trap_nr == X86_TRAP_MF) {
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unsigned short cwd, swd;
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/*
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* (~cwd & swd) will mask out exceptions that are not set to unmasked
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* status. 0x3f is the exception bits in these regs, 0x200 is the
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* C1 reg you need in case of a stack fault, 0x040 is the stack
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* fault bit. We should only be taking one exception at a time,
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* so if this combination doesn't produce any single exception,
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* then we have a bad program that isn't synchronizing its FPU usage
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* and it will suffer the consequences since we won't be able to
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* fully reproduce the context of the exception
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*/
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cwd = get_fpu_cwd(fpu);
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swd = get_fpu_swd(fpu);
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err = swd & ~cwd;
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} else {
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/*
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* The SIMD FPU exceptions are handled a little differently, as there
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* is only a single status/control register. Thus, to determine which
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* unmasked exception was caught we must mask the exception mask bits
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* at 0x1f80, and then use these to mask the exception bits at 0x3f.
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*/
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unsigned short mxcsr = get_fpu_mxcsr(fpu);
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err = ~(mxcsr >> 7) & mxcsr;
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}
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if (err & 0x001) { /* Invalid op */
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/*
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* swd & 0x240 == 0x040: Stack Underflow
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* swd & 0x240 == 0x240: Stack Overflow
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* User must clear the SF bit (0x40) if set
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*/
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return FPE_FLTINV;
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} else if (err & 0x004) { /* Divide by Zero */
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return FPE_FLTDIV;
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} else if (err & 0x008) { /* Overflow */
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return FPE_FLTOVF;
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} else if (err & 0x012) { /* Denormal, Underflow */
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return FPE_FLTUND;
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} else if (err & 0x020) { /* Precision */
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return FPE_FLTRES;
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}
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/*
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* If we're using IRQ 13, or supposedly even some trap
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* X86_TRAP_MF implementations, it's possible
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* we get a spurious trap, which is not an error.
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*/
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return 0;
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}
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@ -708,8 +708,8 @@ NOKPROBE_SYMBOL(do_debug);
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static void math_error(struct pt_regs *regs, int error_code, int trapnr)
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{
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struct task_struct *task = current;
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struct fpu *fpu = &task->thread.fpu;
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siginfo_t info;
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unsigned short err;
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char *str = (trapnr == X86_TRAP_MF) ? "fpu exception" :
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"simd exception";
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@ -717,8 +717,7 @@ static void math_error(struct pt_regs *regs, int error_code, int trapnr)
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return;
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conditional_sti(regs);
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if (!user_mode(regs))
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{
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if (!user_mode(regs)) {
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if (!fixup_exception(regs)) {
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task->thread.error_code = error_code;
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task->thread.trap_nr = trapnr;
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@ -730,62 +729,20 @@ static void math_error(struct pt_regs *regs, int error_code, int trapnr)
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/*
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* Save the info for the exception handler and clear the error.
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*/
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fpu__save(&task->thread.fpu);
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task->thread.trap_nr = trapnr;
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fpu__save(fpu);
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task->thread.trap_nr = trapnr;
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task->thread.error_code = error_code;
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info.si_signo = SIGFPE;
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info.si_errno = 0;
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info.si_addr = (void __user *)uprobe_get_trap_addr(regs);
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if (trapnr == X86_TRAP_MF) {
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unsigned short cwd, swd;
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/*
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* (~cwd & swd) will mask out exceptions that are not set to unmasked
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* status. 0x3f is the exception bits in these regs, 0x200 is the
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* C1 reg you need in case of a stack fault, 0x040 is the stack
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* fault bit. We should only be taking one exception at a time,
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* so if this combination doesn't produce any single exception,
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* then we have a bad program that isn't synchronizing its FPU usage
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* and it will suffer the consequences since we won't be able to
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* fully reproduce the context of the exception
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*/
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cwd = get_fpu_cwd(task);
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swd = get_fpu_swd(task);
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info.si_signo = SIGFPE;
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info.si_errno = 0;
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info.si_addr = (void __user *)uprobe_get_trap_addr(regs);
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err = swd & ~cwd;
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} else {
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/*
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* The SIMD FPU exceptions are handled a little differently, as there
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* is only a single status/control register. Thus, to determine which
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* unmasked exception was caught we must mask the exception mask bits
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* at 0x1f80, and then use these to mask the exception bits at 0x3f.
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*/
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unsigned short mxcsr = get_fpu_mxcsr(task);
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err = ~(mxcsr >> 7) & mxcsr;
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}
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info.si_code = fpu__exception_code(fpu, trapnr);
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if (err & 0x001) { /* Invalid op */
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/*
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* swd & 0x240 == 0x040: Stack Underflow
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* swd & 0x240 == 0x240: Stack Overflow
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* User must clear the SF bit (0x40) if set
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*/
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info.si_code = FPE_FLTINV;
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} else if (err & 0x004) { /* Divide by Zero */
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info.si_code = FPE_FLTDIV;
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} else if (err & 0x008) { /* Overflow */
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info.si_code = FPE_FLTOVF;
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} else if (err & 0x012) { /* Denormal, Underflow */
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info.si_code = FPE_FLTUND;
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} else if (err & 0x020) { /* Precision */
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info.si_code = FPE_FLTRES;
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} else {
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/*
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* If we're using IRQ 13, or supposedly even some trap
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* X86_TRAP_MF implementations, it's possible
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* we get a spurious trap, which is not an error.
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*/
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/* Retry when we get spurious exceptions: */
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if (!info.si_code)
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return;
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}
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force_sig_info(SIGFPE, &info, task);
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}
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