IB/mlx5: Support congestion related counters
This patch adds support to query the congestion related hardware counters
through new command and links them with other hw counters being available
in hw_counters sysfs location.
In order to reuse existing infrastructure it renames related q_counter
data structures to more generic counters to reflect q_counters and
congestion counters and maybe some other counters in the future.
New hardware counters:
* rp_cnp_handled - CNP packets handled by the reaction point
* rp_cnp_ignored - CNP packets ignored by the reaction point
* np_cnp_sent - CNP packets sent by notification point to respond to
CE marked RoCE packets
* np_ecn_marked_roce_packets - CE marked RoCE packets received by
notification point
It also avoids returning ENOSYS which is specific for invalid
system call and produces the following checkpatch.pl warning.
WARNING: ENOSYS means 'invalid syscall nr' and nothing else
+ return -ENOSYS;
Signed-off-by: Parav Pandit <parav@mellanox.com>
Reviewed-by: Eli Cohen <eli@mellanox.com>
Reviewed-by: Daniel Jurgens <danielj@mellanox.com>
Signed-off-by: Leon Romanovsky <leon@kernel.org>
Signed-off-by: Doug Ledford <dledford@redhat.com>
This commit is contained in:
Parav Pandit
Doug Ledford
Родитель
a43402af1e
Коммит
e1f24a79f4
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@ -46,3 +46,14 @@ int mlx5_cmd_null_mkey(struct mlx5_core_dev *dev, u32 *null_mkey)
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null_mkey);
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return err;
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}
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int mlx5_cmd_query_cong_counter(struct mlx5_core_dev *dev,
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bool reset, void *out, int out_size)
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{
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u32 in[MLX5_ST_SZ_DW(query_cong_statistics_in)] = { };
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MLX5_SET(query_cong_statistics_in, in, opcode,
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MLX5_CMD_OP_QUERY_CONG_STATISTICS);
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MLX5_SET(query_cong_statistics_in, in, clear, reset);
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return mlx5_cmd_exec(dev, in, sizeof(in), out, out_size);
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}
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@ -37,4 +37,6 @@
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#include <linux/mlx5/driver.h>
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int mlx5_cmd_null_mkey(struct mlx5_core_dev *dev, u32 *null_mkey);
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int mlx5_cmd_query_cong_counter(struct mlx5_core_dev *dev,
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bool reset, void *out, int out_size);
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#endif /* MLX5_IB_CMD_H */
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@ -57,6 +57,7 @@
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#include <linux/mlx5/fs.h>
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#include <linux/mlx5/vport.h>
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#include "mlx5_ib.h"
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#include "cmd.h"
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#define DRIVER_NAME "mlx5_ib"
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#define DRIVER_VERSION "2.2-1"
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@ -3213,7 +3214,7 @@ static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
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mlx5_nic_vport_disable_roce(dev->mdev);
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}
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struct mlx5_ib_q_counter {
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struct mlx5_ib_counter {
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const char *name;
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size_t offset;
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};
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@ -3221,18 +3222,18 @@ struct mlx5_ib_q_counter {
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#define INIT_Q_COUNTER(_name) \
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{ .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
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static const struct mlx5_ib_q_counter basic_q_cnts[] = {
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static const struct mlx5_ib_counter basic_q_cnts[] = {
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INIT_Q_COUNTER(rx_write_requests),
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INIT_Q_COUNTER(rx_read_requests),
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INIT_Q_COUNTER(rx_atomic_requests),
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INIT_Q_COUNTER(out_of_buffer),
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};
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static const struct mlx5_ib_q_counter out_of_seq_q_cnts[] = {
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static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
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INIT_Q_COUNTER(out_of_sequence),
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};
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static const struct mlx5_ib_q_counter retrans_q_cnts[] = {
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static const struct mlx5_ib_counter retrans_q_cnts[] = {
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INIT_Q_COUNTER(duplicate_request),
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INIT_Q_COUNTER(rnr_nak_retry_err),
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INIT_Q_COUNTER(packet_seq_err),
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@ -3240,22 +3241,31 @@ static const struct mlx5_ib_q_counter retrans_q_cnts[] = {
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INIT_Q_COUNTER(local_ack_timeout_err),
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};
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static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev)
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#define INIT_CONG_COUNTER(_name) \
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{ .name = #_name, .offset = \
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MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
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static const struct mlx5_ib_counter cong_cnts[] = {
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INIT_CONG_COUNTER(rp_cnp_ignored),
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INIT_CONG_COUNTER(rp_cnp_handled),
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INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
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INIT_CONG_COUNTER(np_cnp_sent),
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};
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static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
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{
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unsigned int i;
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for (i = 0; i < dev->num_ports; i++) {
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mlx5_core_dealloc_q_counter(dev->mdev,
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dev->port[i].q_cnts.set_id);
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kfree(dev->port[i].q_cnts.names);
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kfree(dev->port[i].q_cnts.offsets);
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dev->port[i].cnts.set_id);
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kfree(dev->port[i].cnts.names);
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kfree(dev->port[i].cnts.offsets);
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}
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}
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static int __mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev,
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const char ***names,
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size_t **offsets,
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u32 *num)
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static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
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struct mlx5_ib_counters *cnts)
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{
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u32 num_counters;
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@ -3266,27 +3276,32 @@ static int __mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev,
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if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
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num_counters += ARRAY_SIZE(retrans_q_cnts);
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cnts->num_q_counters = num_counters;
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*names = kcalloc(num_counters, sizeof(**names), GFP_KERNEL);
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if (!*names)
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if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
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cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
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num_counters += ARRAY_SIZE(cong_cnts);
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}
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cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
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if (!cnts->names)
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return -ENOMEM;
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*offsets = kcalloc(num_counters, sizeof(**offsets), GFP_KERNEL);
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if (!*offsets)
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cnts->offsets = kcalloc(num_counters,
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sizeof(cnts->offsets), GFP_KERNEL);
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if (!cnts->offsets)
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goto err_names;
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*num = num_counters;
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return 0;
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err_names:
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kfree(*names);
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kfree(cnts->names);
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return -ENOMEM;
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}
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static void mlx5_ib_fill_q_counters(struct mlx5_ib_dev *dev,
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const char **names,
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size_t *offsets)
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static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
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const char **names,
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size_t *offsets)
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{
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int i;
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int j = 0;
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@ -3309,9 +3324,16 @@ static void mlx5_ib_fill_q_counters(struct mlx5_ib_dev *dev,
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offsets[j] = retrans_q_cnts[i].offset;
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}
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}
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if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
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for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
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names[j] = cong_cnts[i].name;
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offsets[j] = cong_cnts[i].offset;
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}
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}
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}
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static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev)
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static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
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{
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int i;
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int ret;
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@ -3320,7 +3342,7 @@ static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev)
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struct mlx5_ib_port *port = &dev->port[i];
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ret = mlx5_core_alloc_q_counter(dev->mdev,
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&port->q_cnts.set_id);
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&port->cnts.set_id);
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if (ret) {
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mlx5_ib_warn(dev,
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"couldn't allocate queue counter for port %d, err %d\n",
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@ -3328,15 +3350,12 @@ static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev)
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goto dealloc_counters;
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}
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ret = __mlx5_ib_alloc_q_counters(dev,
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&port->q_cnts.names,
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&port->q_cnts.offsets,
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&port->q_cnts.num_counters);
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ret = __mlx5_ib_alloc_counters(dev, &port->cnts);
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if (ret)
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goto dealloc_counters;
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mlx5_ib_fill_q_counters(dev, port->q_cnts.names,
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port->q_cnts.offsets);
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mlx5_ib_fill_counters(dev, port->cnts.names,
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port->cnts.offsets);
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}
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return 0;
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@ -3344,7 +3363,7 @@ static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev)
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dealloc_counters:
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while (--i >= 0)
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mlx5_core_dealloc_q_counter(dev->mdev,
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dev->port[i].q_cnts.set_id);
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dev->port[i].cnts.set_id);
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return ret;
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}
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@ -3359,44 +3378,93 @@ static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
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if (port_num == 0)
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return NULL;
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return rdma_alloc_hw_stats_struct(port->q_cnts.names,
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port->q_cnts.num_counters,
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return rdma_alloc_hw_stats_struct(port->cnts.names,
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port->cnts.num_q_counters +
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port->cnts.num_cong_counters,
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RDMA_HW_STATS_DEFAULT_LIFESPAN);
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}
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static int mlx5_ib_query_q_counters(struct mlx5_ib_dev *dev,
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struct mlx5_ib_port *port,
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struct rdma_hw_stats *stats)
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{
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int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
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void *out;
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__be32 val;
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int ret, i;
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out = mlx5_vzalloc(outlen);
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if (!out)
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return -ENOMEM;
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ret = mlx5_core_query_q_counter(dev->mdev,
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port->cnts.set_id, 0,
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out, outlen);
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if (ret)
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goto free;
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for (i = 0; i < port->cnts.num_q_counters; i++) {
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val = *(__be32 *)(out + port->cnts.offsets[i]);
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stats->value[i] = (u64)be32_to_cpu(val);
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}
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free:
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kvfree(out);
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return ret;
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}
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static int mlx5_ib_query_cong_counters(struct mlx5_ib_dev *dev,
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struct mlx5_ib_port *port,
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struct rdma_hw_stats *stats)
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{
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int outlen = MLX5_ST_SZ_BYTES(query_cong_statistics_out);
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void *out;
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int ret, i;
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int offset = port->cnts.num_q_counters;
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out = mlx5_vzalloc(outlen);
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if (!out)
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return -ENOMEM;
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ret = mlx5_cmd_query_cong_counter(dev->mdev, false, out, outlen);
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if (ret)
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goto free;
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for (i = 0; i < port->cnts.num_cong_counters; i++) {
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stats->value[i + offset] =
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be64_to_cpup((__be64 *)(out +
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port->cnts.offsets[i + offset]));
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}
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free:
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kvfree(out);
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return ret;
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}
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static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
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struct rdma_hw_stats *stats,
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u8 port_num, int index)
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{
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struct mlx5_ib_dev *dev = to_mdev(ibdev);
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struct mlx5_ib_port *port = &dev->port[port_num - 1];
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int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
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void *out;
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__be32 val;
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int ret;
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int i;
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int ret, num_counters;
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if (!stats)
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return -ENOSYS;
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return -EINVAL;
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out = mlx5_vzalloc(outlen);
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if (!out)
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return -ENOMEM;
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ret = mlx5_core_query_q_counter(dev->mdev,
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port->q_cnts.set_id, 0,
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out, outlen);
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ret = mlx5_ib_query_q_counters(dev, port, stats);
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if (ret)
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goto free;
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return ret;
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num_counters = port->cnts.num_q_counters;
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for (i = 0; i < port->q_cnts.num_counters; i++) {
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val = *(__be32 *)(out + port->q_cnts.offsets[i]);
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stats->value[i] = (u64)be32_to_cpu(val);
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if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
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ret = mlx5_ib_query_cong_counters(dev, port, stats);
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if (ret)
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return ret;
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num_counters += port->cnts.num_cong_counters;
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}
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free:
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kvfree(out);
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return port->q_cnts.num_counters;
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return num_counters;
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}
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static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
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|
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@ -3603,14 +3671,14 @@ static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
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goto err_rsrc;
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if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
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err = mlx5_ib_alloc_q_counters(dev);
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err = mlx5_ib_alloc_counters(dev);
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if (err)
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goto err_odp;
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}
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dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
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if (!dev->mdev->priv.uar)
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goto err_q_cnt;
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goto err_cnt;
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err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
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if (err)
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|
|
@ -3654,9 +3722,9 @@ err_bfreg:
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err_uar_page:
|
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mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
|
||||
|
||||
err_q_cnt:
|
||||
err_cnt:
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if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
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mlx5_ib_dealloc_q_counters(dev);
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mlx5_ib_dealloc_counters(dev);
|
||||
|
||||
err_odp:
|
||||
mlx5_ib_odp_remove_one(dev);
|
||||
|
|
@ -3690,7 +3758,7 @@ static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
|
|||
mlx5_free_bfreg(dev->mdev, &dev->bfreg);
|
||||
mlx5_put_uars_page(dev->mdev, mdev->priv.uar);
|
||||
if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
|
||||
mlx5_ib_dealloc_q_counters(dev);
|
||||
mlx5_ib_dealloc_counters(dev);
|
||||
destroy_umrc_res(dev);
|
||||
mlx5_ib_odp_remove_one(dev);
|
||||
destroy_dev_resources(&dev->devr);
|
||||
|
|
|
|||
|
|
@ -595,15 +595,16 @@ struct mlx5_ib_resources {
|
|||
struct mutex mutex;
|
||||
};
|
||||
|
||||
struct mlx5_ib_q_counters {
|
||||
struct mlx5_ib_counters {
|
||||
const char **names;
|
||||
size_t *offsets;
|
||||
u32 num_counters;
|
||||
u32 num_q_counters;
|
||||
u32 num_cong_counters;
|
||||
u16 set_id;
|
||||
};
|
||||
|
||||
struct mlx5_ib_port {
|
||||
struct mlx5_ib_q_counters q_cnts;
|
||||
struct mlx5_ib_counters cnts;
|
||||
};
|
||||
|
||||
struct mlx5_roce {
|
||||
|
|
|
|||
|
|
@ -2799,7 +2799,7 @@ static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
|
|||
qp->port) - 1;
|
||||
mibport = &dev->port[port_num];
|
||||
context->qp_counter_set_usr_page |=
|
||||
cpu_to_be32((u32)(mibport->q_cnts.set_id) << 24);
|
||||
cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
|
||||
}
|
||||
|
||||
if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
|
||||
|
|
@ -2827,7 +2827,7 @@ static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
|
|||
|
||||
raw_qp_param.operation = op;
|
||||
if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
|
||||
raw_qp_param.rq_q_ctr_id = mibport->q_cnts.set_id;
|
||||
raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
|
||||
raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
|
||||
}
|
||||
|
||||
|
|
@ -4965,7 +4965,8 @@ int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
|
|||
if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
|
||||
MLX5_SET64(modify_rq_in, in, modify_bitmask,
|
||||
MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
|
||||
MLX5_SET(rqc, rqc, counter_set_id, dev->port->q_cnts.set_id);
|
||||
MLX5_SET(rqc, rqc, counter_set_id,
|
||||
dev->port->cnts.set_id);
|
||||
} else
|
||||
pr_info_once("%s: Receive WQ counters are not supported on current FW\n",
|
||||
dev->ib_dev.name);
|
||||
|
|
|
|||
|
|
@ -4735,17 +4735,17 @@ struct mlx5_ifc_query_cong_statistics_out_bits {
|
|||
|
||||
u8 reserved_at_40[0x40];
|
||||
|
||||
u8 cur_flows[0x20];
|
||||
u8 rp_cur_flows[0x20];
|
||||
|
||||
u8 sum_flows[0x20];
|
||||
|
||||
u8 cnp_ignored_high[0x20];
|
||||
u8 rp_cnp_ignored_high[0x20];
|
||||
|
||||
u8 cnp_ignored_low[0x20];
|
||||
u8 rp_cnp_ignored_low[0x20];
|
||||
|
||||
u8 cnp_handled_high[0x20];
|
||||
u8 rp_cnp_handled_high[0x20];
|
||||
|
||||
u8 cnp_handled_low[0x20];
|
||||
u8 rp_cnp_handled_low[0x20];
|
||||
|
||||
u8 reserved_at_140[0x100];
|
||||
|
||||
|
|
@ -4755,13 +4755,13 @@ struct mlx5_ifc_query_cong_statistics_out_bits {
|
|||
|
||||
u8 accumulators_period[0x20];
|
||||
|
||||
u8 ecn_marked_roce_packets_high[0x20];
|
||||
u8 np_ecn_marked_roce_packets_high[0x20];
|
||||
|
||||
u8 ecn_marked_roce_packets_low[0x20];
|
||||
u8 np_ecn_marked_roce_packets_low[0x20];
|
||||
|
||||
u8 cnps_sent_high[0x20];
|
||||
u8 np_cnp_sent_high[0x20];
|
||||
|
||||
u8 cnps_sent_low[0x20];
|
||||
u8 np_cnp_sent_low[0x20];
|
||||
|
||||
u8 reserved_at_320[0x560];
|
||||
};
|
||||
|
|
|
|||
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