phy: fixes for 5.9
*) platform_no_drv_owner.cocci and return value check qcom ipq806x-usb driver *) correcting register programming for ipq8074 phy *) disable PHY charger detect for omap-usb2-phy -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE+vs47OPLdNbVcHzyfBQHDyUjg0cFAl9SE4EACgkQfBQHDyUj g0fVLw/9Hl1qw32LgWdWOdcJjL/FChyq7MvXqW+RW/j2c8zaGZCDYHeb4zwQMt7k JNawbARwyjbJPPiCpSL7gpyQ/kNHxmNmkoSPSTKkIwitpdh3x7cxGlxuWHkC6ECV uoJhRBO4yUkNZ1t9vrQ0XRbn49yUzP2ff+dpqAT2HU6E7CZGpJ8eV8er09gHyUp8 tbFaSBJm8WhbUKdGQN4EyqembI6doIuW7QNaL+ByQqI6p+ReAFwl2rwMSsM8wz3c Z0UhzUfbLMaw69Q3ujle6I5Pn/Suixu4J8bffkdW8k7xze/1PtyzES/q85nMZsR5 ZBgGd8cjRD6neBCFOgkhf/RUUhYczwaXIRYP57K/fC1nIot+8bmt4TRtz2Oh1s06 o0iozvmkvKupXmEefMm5XE5efxJ8Kof1QDdff2mpE0UvB8KQzcQQN4C3Dk/TF8xt gkRnG4CcL7ISVwcBmykjZV/DLwJNLU34oVbeKiJ8UbNmPt18cmv6TRrM9AAgabKJ 0jXm1GwwmWkE6E3C1/zBuDjxitamjCv+nBBFzXdkCJk0u6AZn6hnoi4xYyZSxVvc SumrTAk04zcUtAgGMUEn2iiBEqdtUlbRSPr94Q9WP9Lzr1A6wDFUr+Z6vq+gEcuw i6yYq4WWwyFYzry/S10eOUsCzAh4cmkXevEwE6XkCxLUxI37rYE= =+mvl -----END PGP SIGNATURE----- Merge tag 'phy-fixes-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into char-misc-linus Vinod writes: phy: fixes for 5.9 *) platform_no_drv_owner.cocci and return value check qcom ipq806x-usb driver *) correcting register programming for ipq8074 phy *) disable PHY charger detect for omap-usb2-phy * tag 'phy-fixes-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: phy: omap-usb2-phy: disable PHY charger detect phy: qcom-qmp: Use correct values for ipq8074 PCIe Gen2 PHY init phy: qualcomm: fix return value check in qcom_ipq806x_usb_phy_probe() phy: qualcomm: fix platform_no_drv_owner.cocci warnings
This commit is contained in:
Greg Kroah-Hartman
Коммит
e22a220515
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@ -505,9 +505,9 @@ static int qcom_ipq806x_usb_phy_probe(struct platform_device *pdev)
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size = resource_size(res);
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phy_dwc3->base = devm_ioremap(phy_dwc3->dev, res->start, size);
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if (IS_ERR(phy_dwc3->base)) {
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if (!phy_dwc3->base) {
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dev_err(phy_dwc3->dev, "failed to map reg\n");
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return PTR_ERR(phy_dwc3->base);
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return -ENOMEM;
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}
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phy_dwc3->ref_clk = devm_clk_get(phy_dwc3->dev, "ref");
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@ -557,7 +557,6 @@ static struct platform_driver qcom_ipq806x_usb_phy_driver = {
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.probe = qcom_ipq806x_usb_phy_probe,
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.driver = {
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.name = "qcom-ipq806x-usb-phy",
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.owner = THIS_MODULE,
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.of_match_table = qcom_ipq806x_usb_phy_table,
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},
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};
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@ -604,8 +604,8 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
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QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
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QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
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QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0x1f),
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QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
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QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
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QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
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QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
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QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
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QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
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@ -631,7 +631,6 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
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QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
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QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
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QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0xa),
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QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
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QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
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QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
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@ -640,7 +639,6 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
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QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
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QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
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QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x7),
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};
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static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
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@ -648,6 +646,8 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
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QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
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QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
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QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
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QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
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};
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static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
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@ -658,7 +658,6 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
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QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
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QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
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QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x4),
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};
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static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
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@ -2046,6 +2045,9 @@ static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
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.pwrdn_ctrl = SW_PWRDN,
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};
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static const char * const ipq8074_pciephy_clk_l[] = {
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"aux", "cfg_ahb",
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};
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/* list of resets */
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static const char * const ipq8074_pciephy_reset_l[] = {
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"phy", "common",
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@ -2063,8 +2065,8 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
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.rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
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.pcs_tbl = ipq8074_pcie_pcs_tbl,
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.pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
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.clk_list = NULL,
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.num_clks = 0,
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.clk_list = ipq8074_pciephy_clk_l,
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.num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
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.reset_list = ipq8074_pciephy_reset_l,
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.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
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.vreg_list = NULL,
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@ -77,6 +77,8 @@
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#define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc
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/* Only for QMP V2 PHY - TX registers */
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#define QSERDES_TX_EMP_POST1_LVL 0x018
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#define QSERDES_TX_SLEW_CNTL 0x040
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#define QSERDES_TX_RES_CODE_LANE_OFFSET 0x054
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#define QSERDES_TX_DEBUG_BUS_SEL 0x064
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#define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068
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@ -22,10 +22,15 @@
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include <linux/of_platform.h>
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#include <linux/sys_soc.h>
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#define USB2PHY_ANA_CONFIG1 0x4c
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#define USB2PHY_DISCON_BYP_LATCH BIT(31)
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#define USB2PHY_CHRG_DET 0x14
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#define USB2PHY_CHRG_DET_USE_CHG_DET_REG BIT(29)
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#define USB2PHY_CHRG_DET_DIS_CHG_DET BIT(28)
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/* SoC Specific USB2_OTG register definitions */
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#define AM654_USB2_OTG_PD BIT(8)
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#define AM654_USB2_VBUS_DET_EN BIT(5)
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@ -43,6 +48,7 @@
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#define OMAP_USB2_HAS_START_SRP BIT(0)
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#define OMAP_USB2_HAS_SET_VBUS BIT(1)
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#define OMAP_USB2_CALIBRATE_FALSE_DISCONNECT BIT(2)
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#define OMAP_USB2_DISABLE_CHRG_DET BIT(3)
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struct omap_usb {
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struct usb_phy phy;
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@ -236,6 +242,13 @@ static int omap_usb_init(struct phy *x)
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omap_usb_writel(phy->phy_base, USB2PHY_ANA_CONFIG1, val);
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}
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if (phy->flags & OMAP_USB2_DISABLE_CHRG_DET) {
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val = omap_usb_readl(phy->phy_base, USB2PHY_CHRG_DET);
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val |= USB2PHY_CHRG_DET_USE_CHG_DET_REG |
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USB2PHY_CHRG_DET_DIS_CHG_DET;
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omap_usb_writel(phy->phy_base, USB2PHY_CHRG_DET, val);
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}
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return 0;
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}
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@ -329,6 +342,26 @@ static const struct of_device_id omap_usb2_id_table[] = {
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};
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MODULE_DEVICE_TABLE(of, omap_usb2_id_table);
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static void omap_usb2_init_errata(struct omap_usb *phy)
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{
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static const struct soc_device_attribute am65x_sr10_soc_devices[] = {
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{ .family = "AM65X", .revision = "SR1.0" },
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{ /* sentinel */ }
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};
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/*
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* Errata i2075: USB2PHY: USB2PHY Charger Detect is Enabled by
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* Default Without VBUS Presence.
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*
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* AM654x SR1.0 has a silicon bug due to which D+ is pulled high after
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* POR, which could cause enumeration failure with some USB hubs.
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* Disabling the USB2_PHY Charger Detect function will put D+
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* into the normal state.
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*/
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if (soc_device_match(am65x_sr10_soc_devices))
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phy->flags |= OMAP_USB2_DISABLE_CHRG_DET;
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}
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static int omap_usb2_probe(struct platform_device *pdev)
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{
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struct omap_usb *phy;
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@ -366,14 +399,14 @@ static int omap_usb2_probe(struct platform_device *pdev)
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phy->mask = phy_data->mask;
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phy->power_on = phy_data->power_on;
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phy->power_off = phy_data->power_off;
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phy->flags = phy_data->flags;
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if (phy_data->flags & OMAP_USB2_CALIBRATE_FALSE_DISCONNECT) {
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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phy->phy_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(phy->phy_base))
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return PTR_ERR(phy->phy_base);
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phy->flags |= OMAP_USB2_CALIBRATE_FALSE_DISCONNECT;
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}
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omap_usb2_init_errata(phy);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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phy->phy_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(phy->phy_base))
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return PTR_ERR(phy->phy_base);
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phy->syscon_phy_power = syscon_regmap_lookup_by_phandle(node,
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"syscon-phy-power");
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