ARM: at91/aic: add irq domain and device tree support
Add an irqdomain for the AIC interrupt controller. The device tree support is mapping the registers and is using the irq_domain_add_legacy() to manage hwirq translation. The documentation is describing the meaning of the two cells required for using this "interrupt-controller" in a device tree node. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
This commit is contained in:
Nicolas Ferre
Родитель
89d4a1753b
Коммит
e261501d05
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@ -0,0 +1,38 @@
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* Advanced Interrupt Controller (AIC)
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Required properties:
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- compatible: Should be "atmel,<chip>-aic"
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- interrupt-controller: Identifies the node as an interrupt controller.
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- interrupt-parent: For single AIC system, it is an empty property.
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- #interrupt-cells: The number of cells to define the interrupts. It sould be 2.
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The first cell is the IRQ number (aka "Peripheral IDentifier" on datasheet).
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The second cell is used to specify flags:
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bits[3:0] trigger type and level flags:
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1 = low-to-high edge triggered.
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2 = high-to-low edge triggered.
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4 = active high level-sensitive.
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8 = active low level-sensitive.
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Valid combinations are 1, 2, 3, 4, 8.
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Default flag for internal sources should be set to 4 (active high).
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- reg: Should contain AIC registers location and length
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Examples:
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/*
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* AIC
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*/
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aic: interrupt-controller@fffff000 {
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compatible = "atmel,at91rm9200-aic";
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interrupt-controller;
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interrupt-parent;
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#interrupt-cells = <2>;
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reg = <0xfffff000 0x200>;
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};
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/*
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* An interrupt generating device that is wired to an AIC.
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*/
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dma: dma-controller@ffffec00 {
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compatible = "atmel,at91sam9g45-dma";
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reg = <0xffffec00 0x200>;
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interrupts = <21 4>;
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};
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@ -322,6 +322,7 @@ config ARCH_AT91
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select ARCH_REQUIRE_GPIOLIB
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select HAVE_CLK
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select CLKDEV_LOOKUP
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select IRQ_DOMAIN
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help
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This enables support for systems based on the Atmel AT91RM9200,
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AT91SAM9 processors.
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@ -47,7 +47,7 @@
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ranges;
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aic: interrupt-controller@fffff000 {
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#interrupt-cells = <1>;
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#interrupt-cells = <2>;
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compatible = "atmel,at91rm9200-aic";
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interrupt-controller;
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interrupt-parent;
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@ -57,14 +57,14 @@
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dbgu: serial@fffff200 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xfffff200 0x200>;
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interrupts = <1>;
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interrupts = <1 4>;
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status = "disabled";
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};
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usart0: serial@fffb0000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xfffb0000 0x200>;
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interrupts = <6>;
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interrupts = <6 4>;
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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status = "disabled";
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@ -73,7 +73,7 @@
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usart1: serial@fffb4000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xfffb4000 0x200>;
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interrupts = <7>;
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interrupts = <7 4>;
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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status = "disabled";
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@ -82,7 +82,7 @@
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usart2: serial@fffb8000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xfffb8000 0x200>;
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interrupts = <8>;
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interrupts = <8 4>;
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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status = "disabled";
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@ -91,7 +91,7 @@
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usart3: serial@fffd0000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xfffd0000 0x200>;
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interrupts = <23>;
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interrupts = <23 4>;
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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status = "disabled";
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@ -100,7 +100,7 @@
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usart4: serial@fffd4000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xfffd4000 0x200>;
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interrupts = <24>;
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interrupts = <24 4>;
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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status = "disabled";
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@ -109,7 +109,7 @@
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usart5: serial@fffd8000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xfffd8000 0x200>;
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interrupts = <25>;
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interrupts = <25 4>;
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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status = "disabled";
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@ -118,7 +118,7 @@
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macb0: ethernet@fffc4000 {
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compatible = "cdns,at32ap7000-macb", "cdns,macb";
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reg = <0xfffc4000 0x100>;
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interrupts = <21>;
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interrupts = <21 4>;
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status = "disabled";
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};
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};
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@ -46,7 +46,7 @@
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ranges;
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aic: interrupt-controller@fffff000 {
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#interrupt-cells = <1>;
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#interrupt-cells = <2>;
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compatible = "atmel,at91rm9200-aic";
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interrupt-controller;
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interrupt-parent;
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@ -56,20 +56,20 @@
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dma: dma-controller@ffffec00 {
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compatible = "atmel,at91sam9g45-dma";
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reg = <0xffffec00 0x200>;
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interrupts = <21>;
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interrupts = <21 4>;
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};
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dbgu: serial@ffffee00 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xffffee00 0x200>;
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interrupts = <1>;
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interrupts = <1 4>;
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status = "disabled";
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};
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usart0: serial@fff8c000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xfff8c000 0x200>;
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interrupts = <7>;
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interrupts = <7 4>;
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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status = "disabled";
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@ -78,7 +78,7 @@
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usart1: serial@fff90000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xfff90000 0x200>;
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interrupts = <8>;
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interrupts = <8 4>;
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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status = "disabled";
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@ -87,7 +87,7 @@
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usart2: serial@fff94000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xfff94000 0x200>;
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interrupts = <9>;
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interrupts = <9 4>;
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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status = "disabled";
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@ -96,7 +96,7 @@
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usart3: serial@fff98000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xfff98000 0x200>;
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interrupts = <10>;
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interrupts = <10 4>;
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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status = "disabled";
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@ -105,7 +105,7 @@
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macb0: ethernet@fffbc000 {
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compatible = "cdns,at32ap7000-macb", "cdns,macb";
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reg = <0xfffbc000 0x100>;
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interrupts = <25>;
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interrupts = <25 4>;
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status = "disabled";
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};
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};
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@ -24,6 +24,12 @@
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#include <linux/module.h>
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#include <linux/mm.h>
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#include <linux/types.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/err.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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@ -34,22 +40,24 @@
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#include <asm/mach/map.h>
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void __iomem *at91_aic_base;
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static struct irq_domain *at91_aic_domain;
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static struct device_node *at91_aic_np;
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static void at91_aic_mask_irq(struct irq_data *d)
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{
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/* Disable interrupt on AIC */
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at91_aic_write(AT91_AIC_IDCR, 1 << d->irq);
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at91_aic_write(AT91_AIC_IDCR, 1 << d->hwirq);
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}
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static void at91_aic_unmask_irq(struct irq_data *d)
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{
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/* Enable interrupt on AIC */
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at91_aic_write(AT91_AIC_IECR, 1 << d->irq);
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at91_aic_write(AT91_AIC_IECR, 1 << d->hwirq);
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}
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unsigned int at91_extern_irq;
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#define is_extern_irq(irq) ((1 << (irq)) & at91_extern_irq)
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#define is_extern_irq(hwirq) ((1 << (hwirq)) & at91_extern_irq)
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static int at91_aic_set_type(struct irq_data *d, unsigned type)
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{
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@ -63,13 +71,13 @@ static int at91_aic_set_type(struct irq_data *d, unsigned type)
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srctype = AT91_AIC_SRCTYPE_RISING;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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if ((d->irq == AT91_ID_FIQ) || is_extern_irq(d->irq)) /* only supported on external interrupts */
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if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq)) /* only supported on external interrupts */
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srctype = AT91_AIC_SRCTYPE_LOW;
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else
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return -EINVAL;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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if ((d->irq == AT91_ID_FIQ) || is_extern_irq(d->irq)) /* only supported on external interrupts */
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if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq)) /* only supported on external interrupts */
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srctype = AT91_AIC_SRCTYPE_FALLING;
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else
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return -EINVAL;
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@ -78,8 +86,8 @@ static int at91_aic_set_type(struct irq_data *d, unsigned type)
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return -EINVAL;
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}
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smr = at91_aic_read(AT91_AIC_SMR(d->irq)) & ~AT91_AIC_SRCTYPE;
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at91_aic_write(AT91_AIC_SMR(d->irq), smr | srctype);
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smr = at91_aic_read(AT91_AIC_SMR(d->hwirq)) & ~AT91_AIC_SRCTYPE;
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at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype);
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return 0;
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}
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@ -90,13 +98,13 @@ static u32 backups;
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static int at91_aic_set_wake(struct irq_data *d, unsigned value)
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{
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if (unlikely(d->irq >= 32))
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if (unlikely(d->hwirq >= NR_AIC_IRQS))
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return -EINVAL;
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if (value)
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wakeups |= (1 << d->irq);
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wakeups |= (1 << d->hwirq);
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else
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wakeups &= ~(1 << d->irq);
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wakeups &= ~(1 << d->hwirq);
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return 0;
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}
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@ -127,24 +135,64 @@ static struct irq_chip at91_aic_chip = {
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.irq_set_wake = at91_aic_set_wake,
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};
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#if defined(CONFIG_OF)
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static int __init __at91_aic_of_init(struct device_node *node,
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struct device_node *parent)
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{
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at91_aic_base = of_iomap(node, 0);
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at91_aic_np = node;
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return 0;
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}
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static const struct of_device_id aic_ids[] __initconst = {
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{ .compatible = "atmel,at91rm9200-aic", .data = __at91_aic_of_init },
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{ /*sentinel*/ }
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};
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static void __init at91_aic_of_init(void)
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{
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of_irq_init(aic_ids);
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}
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#else
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static void __init at91_aic_of_init(void) {}
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#endif
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/*
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* Initialize the AIC interrupt controller.
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*/
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void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
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{
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unsigned int i;
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int irq_base;
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at91_aic_base = ioremap(AT91_AIC, 512);
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if (of_have_populated_dt())
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at91_aic_of_init();
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else
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at91_aic_base = ioremap(AT91_AIC, 512);
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if (!at91_aic_base)
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panic("Impossible to ioremap AT91_AIC\n");
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panic("Unable to ioremap AIC registers\n");
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/* Add irq domain for AIC */
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irq_base = irq_alloc_descs(-1, 0, NR_AIC_IRQS, 0);
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if (irq_base < 0) {
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WARN(1, "Cannot allocate irq_descs, assuming pre-allocated\n");
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irq_base = 0;
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}
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at91_aic_domain = irq_domain_add_legacy(at91_aic_np, NR_AIC_IRQS,
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irq_base, 0,
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&irq_domain_simple_ops, NULL);
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if (!at91_aic_domain)
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panic("Unable to add AIC irq domain\n");
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/*
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* The IVR is used by macro get_irqnr_and_base to read and verify.
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* The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
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*/
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for (i = 0; i < NR_AIC_IRQS; i++) {
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/* Put irq number in Source Vector Register: */
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/* Put hardware irq number in Source Vector Register: */
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at91_aic_write(AT91_AIC_SVR(i), i);
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/* Active Low interrupt, with the specified priority */
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at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
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