pci-v4.11-fixes-1
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJYuZvtAAoJEFmIoMA60/r8CUoP/0n8jRKH98KGQdjP14IvfjNY XivyQzQGRPhEUgOopIPUzQYHZTS3R0uL3RJcJy6ZuZDGUKrPacayv0nMikBJDVHn KrnVJYkLpCvQZV5TyOq18BVFHNOxG9vMOKo73quy9nLrmDiVtQ+F6mFL3z8CRKS1 r9QOGW0/tVtbHxwGINKFo572DXHKVkQAvhL36hYXmLzrFFUuvUK8XMxQz4Bgudo/ TsRNkES5h4pdBwnRNVjrMUl/uIIfUFrP//Q1OUTitcEVep4PsOV7WJKvGqL2HtGY 5xq0lfEIP9aLEgBJd9jydPXgWnNXXbC2PV2MtoTCw3kw4Jxq//sNRWVycbRgjLoA nfQ2vsvhaX3eE7CHz2w8e4Jpi4/lz2QPq2U3oTbwco+HoX2jsPiufGhQ2CSSBKJP 13AKBbfMpLkgDmG/eTwvb5Lqsvzj2aSFKkKuhFV5KGx7iXjLQu2G6hXr/3PgsQfB cI0hbL34sExydsYxD0wPhr+PsPzxymumcJ0cCpN4omErl2Ovt5fIoKdI+/olhTNO zvIZquE9GMTDh3ajWn5hSIqTiohZlJ0jyo06QMxoy7lmwloI0OTK0xpRY3ZfSncZ WvWRg4BN1m6E5IFJvMLSzVJ5lTZgjm7h6RvSskfOfV/zMykd2d6E7j9v4cOMU1Hl MG/amy4uXcWbkhMse2kp =hgdy -----END PGP SIGNATURE----- Merge tag 'pci-v4.11-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI fixes from Bjorn Helgaas: - fix NULL pointer dereferences in many DesignWare-based drivers due to refactoring error - fix Altera config write breakage due to my refactoring error * tag 'pci-v4.11-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: PCI: altera: Fix TLP_CFG_DW0 for TLP write PCI: dwc: Fix crashes seen due to missing assignments
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Коммит
e27fd02d92
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@ -668,6 +668,7 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
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pci->dev = dev;
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pci->ops = &dw_pcie_ops;
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ep->pci = pci;
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ep->ops = (const struct exynos_pcie_ops *)
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of_device_get_match_data(dev);
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@ -605,6 +605,7 @@ static int __init imx6_pcie_probe(struct platform_device *pdev)
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pci->dev = dev;
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pci->ops = &dw_pcie_ops;
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imx6_pcie->pci = pci;
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imx6_pcie->variant =
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(enum imx6_pcie_variants)of_device_get_match_data(dev);
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@ -401,6 +401,8 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
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pci->dev = dev;
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pci->ops = &dw_pcie_ops;
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ks_pcie->pci = pci;
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/* initialize SerDes Phy if present */
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phy = devm_phy_get(dev, "pcie-phy");
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if (PTR_ERR_OR_ZERO(phy) == -EPROBE_DEFER)
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@ -280,6 +280,8 @@ static int __init ls_pcie_probe(struct platform_device *pdev)
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pci->dev = dev;
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pci->ops = pcie->drvdata->dw_pcie_ops;
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pcie->pci = pci;
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dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
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pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
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if (IS_ERR(pci->dbi_base))
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@ -220,6 +220,8 @@ static int armada8k_pcie_probe(struct platform_device *pdev)
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pci->dev = dev;
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pci->ops = &dw_pcie_ops;
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pcie->pci = pci;
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pcie->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(pcie->clk))
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return PTR_ERR(pcie->clk);
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@ -253,6 +253,8 @@ static int artpec6_pcie_probe(struct platform_device *pdev)
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pci->dev = dev;
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artpec6_pcie->pci = pci;
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dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
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pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
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if (IS_ERR(pci->dbi_base))
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@ -104,6 +104,8 @@ static int dw_plat_pcie_probe(struct platform_device *pdev)
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pci->dev = dev;
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dw_plat_pcie->pci = pci;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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pci->dbi_base = devm_ioremap_resource(dev, res);
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if (IS_ERR(pci->dbi_base))
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@ -284,6 +284,8 @@ static int hisi_pcie_probe(struct platform_device *pdev)
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driver = dev->driver;
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hisi_pcie->pci = pci;
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hisi_pcie->soc_ops = of_device_get_match_data(dev);
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hisi_pcie->subctrl =
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@ -686,6 +686,8 @@ static int qcom_pcie_probe(struct platform_device *pdev)
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pci->ops = &dw_pcie_ops;
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pp = &pci->pp;
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pcie->pci = pci;
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pcie->ops = (struct qcom_pcie_ops *)of_device_get_match_data(dev);
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pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_LOW);
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@ -247,6 +247,8 @@ static int spear13xx_pcie_probe(struct platform_device *pdev)
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pci->dev = dev;
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pci->ops = &dw_pcie_ops;
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spear13xx_pcie->pci = pci;
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spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
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if (IS_ERR(spear13xx_pcie->phy)) {
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ret = PTR_ERR(spear13xx_pcie->phy);
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@ -57,10 +57,14 @@
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#define TLP_WRITE_TAG 0x10
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#define RP_DEVFN 0
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#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
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#define TLP_CFG_DW0(pcie, bus) \
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#define TLP_CFGRD_DW0(pcie, bus) \
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((((bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGRD0 \
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: TLP_FMTTYPE_CFGRD1) << 24) | \
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TLP_PAYLOAD_SIZE)
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#define TLP_CFGWR_DW0(pcie, bus) \
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((((bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGWR0 \
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: TLP_FMTTYPE_CFGWR1) << 24) | \
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TLP_PAYLOAD_SIZE)
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#define TLP_CFG_DW1(pcie, tag, be) \
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(((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
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#define TLP_CFG_DW2(bus, devfn, offset) \
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@ -222,7 +226,7 @@ static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn,
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{
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u32 headers[TLP_HDR_SIZE];
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headers[0] = TLP_CFG_DW0(pcie, bus);
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headers[0] = TLP_CFGRD_DW0(pcie, bus);
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headers[1] = TLP_CFG_DW1(pcie, TLP_READ_TAG, byte_en);
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headers[2] = TLP_CFG_DW2(bus, devfn, where);
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@ -237,7 +241,7 @@ static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn,
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u32 headers[TLP_HDR_SIZE];
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int ret;
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headers[0] = TLP_CFG_DW0(pcie, bus);
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headers[0] = TLP_CFGWR_DW0(pcie, bus);
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headers[1] = TLP_CFG_DW1(pcie, TLP_WRITE_TAG, byte_en);
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headers[2] = TLP_CFG_DW2(bus, devfn, where);
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