net/mlx5_core: HW data structs/types definitions cleanup
mlx5_ifc.h was heavily modified here since it is now generated by a script from the device specification (PRM rev 0.25). This specification is backward compatible to existing hardware. Some structures/fields were added here in order to enable the Ethernet functionality of the driver. Signed-off-by: Saeed Mahameed <saeedm@mellanox.com> Signed-off-by: Amir Vadai <amirv@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Saeed Mahameed
David S. Miller
Родитель
db058a186f
Коммит
e281682bf2
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@ -390,8 +390,17 @@ const char *mlx5_command_str(int command)
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case MLX5_CMD_OP_ARM_RQ:
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return "ARM_RQ";
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case MLX5_CMD_OP_RESIZE_SRQ:
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return "RESIZE_SRQ";
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case MLX5_CMD_OP_CREATE_XRC_SRQ:
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return "CREATE_XRC_SRQ";
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case MLX5_CMD_OP_DESTROY_XRC_SRQ:
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return "DESTROY_XRC_SRQ";
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case MLX5_CMD_OP_QUERY_XRC_SRQ:
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return "QUERY_XRC_SRQ";
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case MLX5_CMD_OP_ARM_XRC_SRQ:
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return "ARM_XRC_SRQ";
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case MLX5_CMD_OP_ALLOC_PD:
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return "ALLOC_PD";
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@ -408,8 +417,8 @@ const char *mlx5_command_str(int command)
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case MLX5_CMD_OP_ATTACH_TO_MCG:
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return "ATTACH_TO_MCG";
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case MLX5_CMD_OP_DETACH_FROM_MCG:
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return "DETACH_FROM_MCG";
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case MLX5_CMD_OP_DETTACH_FROM_MCG:
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return "DETTACH_FROM_MCG";
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case MLX5_CMD_OP_ALLOC_XRCD:
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return "ALLOC_XRCD";
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@ -95,7 +95,7 @@ int mlx5_query_odp_caps(struct mlx5_core_dev *dev, struct mlx5_odp_caps *caps)
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goto out;
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}
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memcpy(caps, MLX5_ADDR_OF(query_hca_cap_out, out, capability_struct),
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memcpy(caps, MLX5_ADDR_OF(query_hca_cap_out, out, capability),
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sizeof(*caps));
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mlx5_core_dbg(dev, "on-demand paging capabilities:\nrc: %08x\nuc: %08x\nud: %08x\n",
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@ -319,8 +319,7 @@ static void fw2drv_caps(struct mlx5_caps *caps, void *out)
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gen->max_srq_wqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_srq_sz);
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gen->max_wqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_qp_sz);
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gen->log_max_qp = MLX5_GET_PR(cmd_hca_cap, out, log_max_qp);
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gen->log_max_strq = MLX5_GET_PR(cmd_hca_cap, out, log_max_strq_sz);
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gen->log_max_srq = MLX5_GET_PR(cmd_hca_cap, out, log_max_srqs);
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gen->log_max_srq = MLX5_GET_PR(cmd_hca_cap, out, log_max_srq);
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gen->max_cqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_cq_sz);
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gen->log_max_cq = MLX5_GET_PR(cmd_hca_cap, out, log_max_cq);
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gen->max_eqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_eq_sz);
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@ -391,7 +390,7 @@ int mlx5_core_get_caps(struct mlx5_core_dev *dev, struct mlx5_caps *caps,
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goto query_ex;
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}
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mlx5_core_dbg(dev, "%s\n", caps_opmod_str(opmod));
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fw2drv_caps(caps, MLX5_ADDR_OF(query_hca_cap_out, out, capability_struct));
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fw2drv_caps(caps, MLX5_ADDR_OF(query_hca_cap_out, out, capability));
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query_ex:
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kfree(out);
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@ -453,7 +452,7 @@ static int handle_hca_cap(struct mlx5_core_dev *dev)
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/* disable checksum */
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cur_caps->gen.flags &= ~MLX5_DEV_CAP_FLAG_CMDIF_CSUM;
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copy_rw_fields(MLX5_ADDR_OF(set_hca_cap_in, set_ctx, hca_capability_struct),
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copy_rw_fields(MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability),
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cur_caps);
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err = set_caps(dev, set_ctx, set_sz);
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@ -91,7 +91,7 @@ int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn)
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memset(&in, 0, sizeof(in));
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memset(&out, 0, sizeof(out));
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in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DETACH_FROM_MCG);
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in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DETTACH_FROM_MCG);
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memcpy(in.gid, mgid, sizeof(*mgid));
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in.qpn = cpu_to_be32(qpn);
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err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
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@ -223,3 +223,40 @@ int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari)
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return 0;
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}
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int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar)
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{
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phys_addr_t pfn;
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phys_addr_t uar_bar_start;
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int err;
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err = mlx5_cmd_alloc_uar(mdev, &uar->index);
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if (err) {
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mlx5_core_warn(mdev, "mlx5_cmd_alloc_uar() failed, %d\n", err);
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return err;
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}
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uar_bar_start = pci_resource_start(mdev->pdev, 0);
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pfn = (uar_bar_start >> PAGE_SHIFT) + uar->index;
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uar->map = ioremap(pfn << PAGE_SHIFT, PAGE_SIZE);
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if (!uar->map) {
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mlx5_core_warn(mdev, "ioremap() failed, %d\n", err);
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err = -ENOMEM;
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goto err_free_uar;
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}
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return 0;
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err_free_uar:
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mlx5_cmd_free_uar(mdev, uar->index);
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return err;
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}
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EXPORT_SYMBOL(mlx5_alloc_map_uar);
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void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar)
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{
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iounmap(uar->map);
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mlx5_cmd_free_uar(mdev, uar->index);
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}
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EXPORT_SYMBOL(mlx5_unmap_free_uar);
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@ -35,6 +35,7 @@
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#include <linux/types.h>
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#include <rdma/ib_verbs.h>
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#include <linux/mlx5/mlx5_ifc.h>
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#if defined(__LITTLE_ENDIAN)
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#define MLX5_SET_HOST_ENDIANNESS 0
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@ -70,6 +71,14 @@
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<< __mlx5_dw_bit_off(typ, fld))); \
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} while (0)
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#define MLX5_SET_TO_ONES(typ, p, fld) do { \
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BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
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*((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
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cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
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(~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
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<< __mlx5_dw_bit_off(typ, fld))); \
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} while (0)
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#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
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__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
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__mlx5_mask(typ, fld))
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@ -264,6 +273,7 @@ enum {
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MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
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MLX5_OPCODE_SEND = 0x0a,
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MLX5_OPCODE_SEND_IMM = 0x0b,
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MLX5_OPCODE_LSO = 0x0e,
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MLX5_OPCODE_RDMA_READ = 0x10,
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MLX5_OPCODE_ATOMIC_CS = 0x11,
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MLX5_OPCODE_ATOMIC_FA = 0x12,
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@ -541,6 +551,10 @@ struct mlx5_cmd_prot_block {
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u8 sig;
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};
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enum {
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MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
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};
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struct mlx5_err_cqe {
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u8 rsvd0[32];
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__be32 srqn;
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@ -554,13 +568,22 @@ struct mlx5_err_cqe {
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};
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struct mlx5_cqe64 {
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u8 rsvd0[17];
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u8 rsvd0[4];
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u8 lro_tcppsh_abort_dupack;
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u8 lro_min_ttl;
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__be16 lro_tcp_win;
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__be32 lro_ack_seq_num;
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__be32 rss_hash_result;
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u8 rss_hash_type;
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u8 ml_path;
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u8 rsvd20[4];
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u8 rsvd20[2];
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__be16 check_sum;
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__be16 slid;
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__be32 flags_rqpn;
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u8 rsvd28[4];
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__be32 srqn;
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u8 hds_ip_ext;
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u8 l4_hdr_type_etc;
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__be16 vlan_info;
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__be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
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__be32 imm_inval_pkey;
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u8 rsvd40[4];
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__be32 byte_cnt;
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@ -571,6 +594,40 @@ struct mlx5_cqe64 {
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u8 op_own;
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};
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static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
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{
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return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
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}
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static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
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{
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return (cqe->l4_hdr_type_etc >> 4) & 0x7;
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}
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static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
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{
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return !!(cqe->l4_hdr_type_etc & 0x1);
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}
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enum {
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CQE_L4_HDR_TYPE_NONE = 0x0,
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CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
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CQE_L4_HDR_TYPE_UDP = 0x2,
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CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
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CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
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};
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enum {
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CQE_RSS_HTYPE_IP = 0x3 << 6,
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CQE_RSS_HTYPE_L4 = 0x3 << 2,
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};
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enum {
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CQE_L2_OK = 1 << 0,
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CQE_L3_OK = 1 << 1,
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CQE_L4_OK = 1 << 2,
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};
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struct mlx5_sig_err_cqe {
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u8 rsvd0[16];
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__be32 expected_trans_sig;
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@ -996,4 +1053,52 @@ struct mlx5_destroy_psv_out {
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u8 rsvd[8];
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};
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#define MLX5_CMD_OP_MAX 0x920
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enum {
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VPORT_STATE_DOWN = 0x0,
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VPORT_STATE_UP = 0x1,
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};
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enum {
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MLX5_L3_PROT_TYPE_IPV4 = 0,
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MLX5_L3_PROT_TYPE_IPV6 = 1,
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};
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enum {
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MLX5_L4_PROT_TYPE_TCP = 0,
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MLX5_L4_PROT_TYPE_UDP = 1,
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};
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enum {
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MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
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MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
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MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
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MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
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MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
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};
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enum {
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MLX5_MATCH_OUTER_HEADERS = 1 << 0,
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MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
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MLX5_MATCH_INNER_HEADERS = 1 << 2,
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};
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enum {
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MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
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MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
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};
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enum {
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MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
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MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
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MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
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};
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enum {
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MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
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MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
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};
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#endif /* MLX5_DEVICE_H */
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@ -44,7 +44,6 @@
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#include <linux/mlx5/device.h>
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#include <linux/mlx5/doorbell.h>
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#include <linux/mlx5/mlx5_ifc.h>
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enum {
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MLX5_BOARD_ID_LEN = 64,
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@ -278,7 +277,6 @@ struct mlx5_general_caps {
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u8 log_max_mkey;
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u8 log_max_pd;
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u8 log_max_srq;
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u8 log_max_strq;
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u8 log_max_mrw_sz;
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u8 log_max_bsf_list_size;
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u8 log_max_klm_list_size;
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@ -664,6 +662,8 @@ int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
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int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
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int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
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int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
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int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
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void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
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void mlx5_health_cleanup(void);
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void __init mlx5_health_init(void);
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void mlx5_start_health_poll(struct mlx5_core_dev *dev);
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Разница между файлами не показана из-за своего большого размера
Загрузить разницу
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@ -134,13 +134,21 @@ enum {
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enum {
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MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2,
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MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2,
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MLX5_WQE_CTRL_SOLICITED = 1 << 1,
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};
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enum {
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MLX5_SEND_WQE_DS = 16,
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MLX5_SEND_WQE_BB = 64,
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};
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#define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS)
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enum {
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MLX5_SEND_WQE_MAX_WQEBBS = 16,
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};
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enum {
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MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
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MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
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@ -200,6 +208,23 @@ struct mlx5_wqe_ctrl_seg {
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#define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff00
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#define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8
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enum {
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MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 4,
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MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 5,
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MLX5_ETH_WQE_L3_CSUM = 1 << 6,
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MLX5_ETH_WQE_L4_CSUM = 1 << 7,
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};
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struct mlx5_wqe_eth_seg {
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u8 rsvd0[4];
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u8 cs_flags;
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u8 rsvd1;
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__be16 mss;
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__be32 rsvd2;
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__be16 inline_hdr_sz;
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u8 inline_hdr_start[2];
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};
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struct mlx5_wqe_xrc_seg {
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__be32 xrc_srqn;
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u8 rsvd[12];
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