i2c: brcmstb: Adding support for CM and DSL SoCs
Broadcoms DSL, CM (cable modem)and STB I2C core implementation have 8 data in/out registers that can transfer 8 bytes or 32 bytes max. Cable and DSL "Peripheral" i2c cores use single byte per data register and the STB can use 4 byte per data register transfer. Adding support to take care of this difference. Accordingly added the compatible string for SoCs using the "Peripheral" I2C block. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This commit is contained in:
Kamal Dasu
Wolfram Sang
Родитель
8378d01f60
Коммит
e2e5a2c618
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@ -2,7 +2,7 @@ Broadcom stb bsc iic master controller
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Required properties:
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- compatible: should be "brcm,brcmstb-i2c"
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- compatible: should be "brcm,brcmstb-i2c" or "brcm,brcmper-i2c"
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- clock-frequency: 32-bit decimal value of iic master clock freqency in Hz
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valid values are 375000, 390000, 187500, 200000
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93750, 97500, 46875 and 50000
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@ -25,13 +25,16 @@
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#include <linux/version.h>
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#define N_DATA_REGS 8
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#define N_DATA_BYTES (N_DATA_REGS * 4)
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/* BSC count register field definitions */
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#define BSC_CNT_REG1_MASK 0x0000003f
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#define BSC_CNT_REG1_SHIFT 0
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#define BSC_CNT_REG2_MASK 0x00000fc0
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#define BSC_CNT_REG2_SHIFT 6
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/*
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* PER_I2C/BSC count register mask depends on 1 byte/4 byte data register
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* size. Cable modem and DSL SoCs with Peripheral i2c cores use 1 byte per
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* data register whereas STB SoCs use 4 byte per data register transfer,
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* account for this difference in total count per transaction and mask to
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* use.
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*/
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#define BSC_CNT_REG1_MASK(nb) (nb == 1 ? GENMASK(3, 0) : GENMASK(5, 0))
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#define BSC_CNT_REG1_SHIFT 0
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/* BSC CTL register field definitions */
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#define BSC_CTL_REG_DTF_MASK 0x00000003
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@ -41,7 +44,7 @@
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#define BSC_CTL_REG_INT_EN_SHIFT 6
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#define BSC_CTL_REG_DIV_CLK_MASK 0x00000080
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/* BSC_IIC_ENABLE r/w enable and interrupt field defintions */
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/* BSC_IIC_ENABLE r/w enable and interrupt field definitions */
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#define BSC_IIC_EN_RESTART_MASK 0x00000040
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#define BSC_IIC_EN_NOSTART_MASK 0x00000020
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#define BSC_IIC_EN_NOSTOP_MASK 0x00000010
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@ -169,6 +172,7 @@ struct brcmstb_i2c_dev {
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struct completion done;
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bool is_suspended;
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u32 clk_freq_hz;
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int data_regsz;
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};
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/* register accessors for both be and le cpu arch */
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@ -186,6 +190,16 @@ struct brcmstb_i2c_dev {
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#define bsc_writel(_dev, _val, _reg) \
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__bsc_writel(_val, _dev->base + offsetof(struct bsc_regs, _reg))
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static inline int brcmstb_i2c_get_xfersz(struct brcmstb_i2c_dev *dev)
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{
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return (N_DATA_REGS * dev->data_regsz);
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}
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static inline int brcmstb_i2c_get_data_regsz(struct brcmstb_i2c_dev *dev)
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{
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return dev->data_regsz;
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}
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static void brcmstb_i2c_enable_disable_irq(struct brcmstb_i2c_dev *dev,
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bool int_en)
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{
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@ -323,14 +337,16 @@ static int brcmstb_i2c_xfer_bsc_data(struct brcmstb_i2c_dev *dev,
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u8 *buf, unsigned int len,
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struct i2c_msg *pmsg)
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{
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int cnt, byte, rc;
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int cnt, byte, i, rc;
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enum bsc_xfer_cmd cmd;
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u32 ctl_reg;
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struct bsc_regs *pi2creg = dev->bsc_regmap;
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int no_ack = pmsg->flags & I2C_M_IGNORE_NAK;
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int data_regsz = brcmstb_i2c_get_data_regsz(dev);
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int xfersz = brcmstb_i2c_get_xfersz(dev);
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/* see if the transaction needs to check NACK conditions */
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if (no_ack || len <= N_DATA_BYTES) {
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if (no_ack || len <= xfersz) {
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cmd = (pmsg->flags & I2C_M_RD) ? CMD_RD_NOACK
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: CMD_WR_NOACK;
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pi2creg->ctlhi_reg |= BSC_CTLHI_REG_IGNORE_ACK_MASK;
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@ -348,20 +364,22 @@ static int brcmstb_i2c_xfer_bsc_data(struct brcmstb_i2c_dev *dev,
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pi2creg->ctl_reg = ctl_reg | DTF_RD_MASK;
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/* set the read/write length */
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bsc_writel(dev, BSC_CNT_REG1_MASK & (len << BSC_CNT_REG1_SHIFT),
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cnt_reg);
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bsc_writel(dev, BSC_CNT_REG1_MASK(data_regsz) &
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(len << BSC_CNT_REG1_SHIFT), cnt_reg);
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/* Write data into data_in register */
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if (cmd == CMD_WR || cmd == CMD_WR_NOACK) {
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for (cnt = 0; cnt < len; cnt += 4) {
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for (cnt = 0, i = 0; cnt < len; cnt += data_regsz, i++) {
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u32 word = 0;
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for (byte = 0; byte < 4; byte++) {
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word >>= 8;
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for (byte = 0; byte < data_regsz; byte++) {
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word >>= BITS_PER_BYTE;
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if ((cnt + byte) < len)
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word |= buf[cnt + byte] << 24;
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word |= buf[cnt + byte] <<
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(BITS_PER_BYTE * (data_regsz - 1));
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}
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bsc_writel(dev, word, data_in[cnt >> 2]);
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bsc_writel(dev, word, data_in[i]);
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}
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}
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@ -373,14 +391,15 @@ static int brcmstb_i2c_xfer_bsc_data(struct brcmstb_i2c_dev *dev,
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return rc;
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}
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/* Read data from data_out register */
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if (cmd == CMD_RD || cmd == CMD_RD_NOACK) {
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for (cnt = 0; cnt < len; cnt += 4) {
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u32 data = bsc_readl(dev, data_out[cnt >> 2]);
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for (cnt = 0, i = 0; cnt < len; cnt += data_regsz, i++) {
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u32 data = bsc_readl(dev, data_out[i]);
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for (byte = 0; byte < 4 &&
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for (byte = 0; byte < data_regsz &&
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(byte + cnt) < len; byte++) {
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buf[cnt + byte] = data & 0xff;
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data >>= 8;
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data >>= BITS_PER_BYTE;
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}
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}
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}
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@ -448,6 +467,7 @@ static int brcmstb_i2c_xfer(struct i2c_adapter *adapter,
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int bytes_to_xfer;
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u8 *tmp_buf;
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int len = 0;
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int xfersz = brcmstb_i2c_get_xfersz(dev);
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if (dev->is_suspended)
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return -EBUSY;
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@ -482,9 +502,9 @@ static int brcmstb_i2c_xfer(struct i2c_adapter *adapter,
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/* Perform data transfer */
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while (len) {
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bytes_to_xfer = min(len, N_DATA_BYTES);
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bytes_to_xfer = min(len, xfersz);
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if (len <= N_DATA_BYTES && i == (num - 1))
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if (len <= xfersz && i == (num - 1))
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brcmstb_set_i2c_start_stop(dev,
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~(COND_START_STOP));
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@ -542,8 +562,12 @@ static void brcmstb_i2c_set_bus_speed(struct brcmstb_i2c_dev *dev)
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static void brcmstb_i2c_set_bsc_reg_defaults(struct brcmstb_i2c_dev *dev)
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{
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/* 4 byte data register */
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dev->bsc_regmap->ctlhi_reg = BSC_CTLHI_REG_DATAREG_SIZE_MASK;
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if (brcmstb_i2c_get_data_regsz(dev) == sizeof(u32))
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/* set 4 byte data in/out xfers */
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dev->bsc_regmap->ctlhi_reg = BSC_CTLHI_REG_DATAREG_SIZE_MASK;
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else
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dev->bsc_regmap->ctlhi_reg &= ~BSC_CTLHI_REG_DATAREG_SIZE_MASK;
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bsc_writel(dev, dev->bsc_regmap->ctlhi_reg, ctlhi_reg);
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/* set bus speed */
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brcmstb_i2c_set_bus_speed(dev);
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@ -608,6 +632,13 @@ static int brcmstb_i2c_probe(struct platform_device *pdev)
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dev->clk_freq_hz = bsc_clk[0].hz;
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}
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/* set the data in/out register size for compatible SoCs */
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if (of_device_is_compatible(dev->device->of_node,
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"brcmstb,brcmper-i2c"))
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dev->data_regsz = sizeof(u8);
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else
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dev->data_regsz = sizeof(u32);
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brcmstb_i2c_set_bsc_reg_defaults(dev);
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/* Add the i2c adapter */
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@ -674,6 +705,7 @@ static SIMPLE_DEV_PM_OPS(brcmstb_i2c_pm, brcmstb_i2c_suspend,
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static const struct of_device_id brcmstb_i2c_of_match[] = {
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{.compatible = "brcm,brcmstb-i2c"},
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{.compatible = "brcm,brcmper-i2c"},
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{},
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};
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MODULE_DEVICE_TABLE(of, brcmstb_i2c_of_match);
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