IIO: ADC: add STM32 DFSDM sigma delta ADC support
Add DFSDM driver to handle sigma delta ADC. Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Arnaud Pouliquen
Mark Brown
Родитель
bed73904e7
Коммит
e2e6771c64
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@ -680,6 +680,19 @@ config STM32_DFSDM_CORE
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This driver can also be built as a module. If so, the module
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will be called stm32-dfsdm-core.
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config STM32_DFSDM_ADC
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tristate "STMicroelectronics STM32 dfsdm adc"
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depends on (ARCH_STM32 && OF) || COMPILE_TEST
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select STM32_DFSDM_CORE
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select REGMAP_MMIO
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select IIO_BUFFER_HW_CONSUMER
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help
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Select this option to support ADCSigma delta modulator for
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STMicroelectronics STM32 digital filter for sigma delta converter.
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This driver can also be built as a module. If so, the module
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will be called stm32-dfsdm-adc.
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config STX104
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tristate "Apex Embedded Systems STX104 driver"
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depends on PC104 && X86 && ISA_BUS_API
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@ -65,6 +65,7 @@ obj-$(CONFIG_SUN4I_GPADC) += sun4i-gpadc-iio.o
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obj-$(CONFIG_STM32_ADC_CORE) += stm32-adc-core.o
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obj-$(CONFIG_STM32_ADC) += stm32-adc.o
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obj-$(CONFIG_STM32_DFSDM_CORE) += stm32-dfsdm-core.o
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obj-$(CONFIG_STM32_DFSDM_ADC) += stm32-dfsdm-adc.o
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obj-$(CONFIG_TI_ADC081C) += ti-adc081c.o
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obj-$(CONFIG_TI_ADC0832) += ti-adc0832.o
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obj-$(CONFIG_TI_ADC084S021) += ti-adc084s021.o
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@ -0,0 +1,728 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* This file is the ADC part of the STM32 DFSDM driver
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*
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* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
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* Author: Arnaud Pouliquen <arnaud.pouliquen@st.com>.
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*/
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#include <linux/interrupt.h>
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#include <linux/iio/buffer.h>
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#include <linux/iio/hw-consumer.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include "stm32-dfsdm.h"
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/* Conversion timeout */
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#define DFSDM_TIMEOUT_US 100000
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#define DFSDM_TIMEOUT (msecs_to_jiffies(DFSDM_TIMEOUT_US / 1000))
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/* Oversampling attribute default */
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#define DFSDM_DEFAULT_OVERSAMPLING 100
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/* Oversampling max values */
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#define DFSDM_MAX_INT_OVERSAMPLING 256
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#define DFSDM_MAX_FL_OVERSAMPLING 1024
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/* Max sample resolutions */
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#define DFSDM_MAX_RES BIT(31)
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#define DFSDM_DATA_RES BIT(23)
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enum sd_converter_type {
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DFSDM_AUDIO,
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DFSDM_IIO,
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};
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struct stm32_dfsdm_dev_data {
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int type;
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int (*init)(struct iio_dev *indio_dev);
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unsigned int num_channels;
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const struct regmap_config *regmap_cfg;
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};
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struct stm32_dfsdm_adc {
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struct stm32_dfsdm *dfsdm;
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const struct stm32_dfsdm_dev_data *dev_data;
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unsigned int fl_id;
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unsigned int ch_id;
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/* ADC specific */
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unsigned int oversamp;
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struct iio_hw_consumer *hwc;
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struct completion completion;
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u32 *buffer;
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};
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struct stm32_dfsdm_str2field {
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const char *name;
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unsigned int val;
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};
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/* DFSDM channel serial interface type */
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static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_type[] = {
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{ "SPI_R", 0 }, /* SPI with data on rising edge */
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{ "SPI_F", 1 }, /* SPI with data on falling edge */
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{ "MANCH_R", 2 }, /* Manchester codec, rising edge = logic 0 */
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{ "MANCH_F", 3 }, /* Manchester codec, falling edge = logic 1 */
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{},
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};
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/* DFSDM channel clock source */
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static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_src[] = {
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/* External SPI clock (CLKIN x) */
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{ "CLKIN", DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL },
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/* Internal SPI clock (CLKOUT) */
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{ "CLKOUT", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL },
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/* Internal SPI clock divided by 2 (falling edge) */
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{ "CLKOUT_F", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING },
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/* Internal SPI clock divided by 2 (falling edge) */
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{ "CLKOUT_R", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING },
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{},
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};
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static int stm32_dfsdm_str2val(const char *str,
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const struct stm32_dfsdm_str2field *list)
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{
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const struct stm32_dfsdm_str2field *p = list;
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for (p = list; p && p->name; p++)
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if (!strcmp(p->name, str))
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return p->val;
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return -EINVAL;
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}
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static int stm32_dfsdm_set_osrs(struct stm32_dfsdm_filter *fl,
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unsigned int fast, unsigned int oversamp)
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{
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unsigned int i, d, fosr, iosr;
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u64 res;
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s64 delta;
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unsigned int m = 1; /* multiplication factor */
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unsigned int p = fl->ford; /* filter order (ford) */
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pr_debug("%s: Requested oversampling: %d\n", __func__, oversamp);
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/*
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* This function tries to compute filter oversampling and integrator
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* oversampling, base on oversampling ratio requested by user.
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*
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* Decimation d depends on the filter order and the oversampling ratios.
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* ford: filter order
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* fosr: filter over sampling ratio
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* iosr: integrator over sampling ratio
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*/
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if (fl->ford == DFSDM_FASTSINC_ORDER) {
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m = 2;
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p = 2;
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}
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/*
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* Look for filter and integrator oversampling ratios which allows
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* to reach 24 bits data output resolution.
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* Leave as soon as if exact resolution if reached.
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* Otherwise the higher resolution below 32 bits is kept.
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*/
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for (fosr = 1; fosr <= DFSDM_MAX_FL_OVERSAMPLING; fosr++) {
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for (iosr = 1; iosr <= DFSDM_MAX_INT_OVERSAMPLING; iosr++) {
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if (fast)
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d = fosr * iosr;
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else if (fl->ford == DFSDM_FASTSINC_ORDER)
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d = fosr * (iosr + 3) + 2;
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else
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d = fosr * (iosr - 1 + p) + p;
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if (d > oversamp)
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break;
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else if (d != oversamp)
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continue;
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/*
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* Check resolution (limited to signed 32 bits)
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* res <= 2^31
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* Sincx filters:
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* res = m * fosr^p x iosr (with m=1, p=ford)
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* FastSinc filter
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* res = m * fosr^p x iosr (with m=2, p=2)
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*/
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res = fosr;
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for (i = p - 1; i > 0; i--) {
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res = res * (u64)fosr;
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if (res > DFSDM_MAX_RES)
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break;
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}
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if (res > DFSDM_MAX_RES)
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continue;
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res = res * (u64)m * (u64)iosr;
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if (res > DFSDM_MAX_RES)
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continue;
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delta = res - DFSDM_DATA_RES;
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if (res >= fl->res) {
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fl->res = res;
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fl->fosr = fosr;
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fl->iosr = iosr;
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fl->fast = fast;
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pr_debug("%s: fosr = %d, iosr = %d\n",
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__func__, fl->fosr, fl->iosr);
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}
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if (!delta)
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return 0;
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}
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}
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if (!fl->fosr)
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return -EINVAL;
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return 0;
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}
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static int stm32_dfsdm_start_channel(struct stm32_dfsdm *dfsdm,
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unsigned int ch_id)
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{
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return regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(ch_id),
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DFSDM_CHCFGR1_CHEN_MASK,
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DFSDM_CHCFGR1_CHEN(1));
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}
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static void stm32_dfsdm_stop_channel(struct stm32_dfsdm *dfsdm,
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unsigned int ch_id)
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{
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regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(ch_id),
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DFSDM_CHCFGR1_CHEN_MASK, DFSDM_CHCFGR1_CHEN(0));
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}
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static int stm32_dfsdm_chan_configure(struct stm32_dfsdm *dfsdm,
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struct stm32_dfsdm_channel *ch)
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{
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unsigned int id = ch->id;
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struct regmap *regmap = dfsdm->regmap;
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int ret;
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ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
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DFSDM_CHCFGR1_SITP_MASK,
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DFSDM_CHCFGR1_SITP(ch->type));
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if (ret < 0)
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return ret;
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ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
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DFSDM_CHCFGR1_SPICKSEL_MASK,
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DFSDM_CHCFGR1_SPICKSEL(ch->src));
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if (ret < 0)
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return ret;
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return regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
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DFSDM_CHCFGR1_CHINSEL_MASK,
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DFSDM_CHCFGR1_CHINSEL(ch->alt_si));
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}
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static int stm32_dfsdm_start_filter(struct stm32_dfsdm *dfsdm,
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unsigned int fl_id)
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{
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int ret;
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/* Enable filter */
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ret = regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
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DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(1));
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if (ret < 0)
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return ret;
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/* Start conversion */
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return regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
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DFSDM_CR1_RSWSTART_MASK,
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DFSDM_CR1_RSWSTART(1));
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}
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void stm32_dfsdm_stop_filter(struct stm32_dfsdm *dfsdm, unsigned int fl_id)
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{
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/* Disable conversion */
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regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
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DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(0));
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}
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static int stm32_dfsdm_filter_configure(struct stm32_dfsdm *dfsdm,
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unsigned int fl_id, unsigned int ch_id)
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{
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struct regmap *regmap = dfsdm->regmap;
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struct stm32_dfsdm_filter *fl = &dfsdm->fl_list[fl_id];
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int ret;
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/* Average integrator oversampling */
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ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_IOSR_MASK,
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DFSDM_FCR_IOSR(fl->iosr - 1));
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if (ret)
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return ret;
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/* Filter order and Oversampling */
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ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FOSR_MASK,
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DFSDM_FCR_FOSR(fl->fosr - 1));
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if (ret)
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return ret;
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ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FORD_MASK,
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DFSDM_FCR_FORD(fl->ford));
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if (ret)
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return ret;
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/* No scan mode supported for the moment */
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ret = regmap_update_bits(regmap, DFSDM_CR1(fl_id), DFSDM_CR1_RCH_MASK,
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DFSDM_CR1_RCH(ch_id));
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if (ret)
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return ret;
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return regmap_update_bits(regmap, DFSDM_CR1(fl_id),
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DFSDM_CR1_RSYNC_MASK,
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DFSDM_CR1_RSYNC(fl->sync_mode));
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}
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int stm32_dfsdm_channel_parse_of(struct stm32_dfsdm *dfsdm,
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struct iio_dev *indio_dev,
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struct iio_chan_spec *ch)
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{
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struct stm32_dfsdm_channel *df_ch;
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const char *of_str;
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int chan_idx = ch->scan_index;
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int ret, val;
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ret = of_property_read_u32_index(indio_dev->dev.of_node,
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"st,adc-channels", chan_idx,
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&ch->channel);
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if (ret < 0) {
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dev_err(&indio_dev->dev,
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" Error parsing 'st,adc-channels' for idx %d\n",
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chan_idx);
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return ret;
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}
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if (ch->channel >= dfsdm->num_chs) {
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dev_err(&indio_dev->dev,
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" Error bad channel number %d (max = %d)\n",
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ch->channel, dfsdm->num_chs);
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return -EINVAL;
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}
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ret = of_property_read_string_index(indio_dev->dev.of_node,
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"st,adc-channel-names", chan_idx,
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&ch->datasheet_name);
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if (ret < 0) {
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dev_err(&indio_dev->dev,
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" Error parsing 'st,adc-channel-names' for idx %d\n",
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chan_idx);
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return ret;
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}
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df_ch = &dfsdm->ch_list[ch->channel];
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df_ch->id = ch->channel;
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ret = of_property_read_string_index(indio_dev->dev.of_node,
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"st,adc-channel-types", chan_idx,
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&of_str);
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if (!ret) {
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val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_type);
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if (val < 0)
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return val;
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} else {
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val = 0;
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}
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df_ch->type = val;
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ret = of_property_read_string_index(indio_dev->dev.of_node,
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"st,adc-channel-clk-src", chan_idx,
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&of_str);
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if (!ret) {
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val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_src);
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if (val < 0)
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return val;
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} else {
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val = 0;
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}
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df_ch->src = val;
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ret = of_property_read_u32_index(indio_dev->dev.of_node,
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"st,adc-alt-channel", chan_idx,
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&df_ch->alt_si);
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if (ret < 0)
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df_ch->alt_si = 0;
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return 0;
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}
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static int stm32_dfsdm_start_conv(struct stm32_dfsdm_adc *adc, bool dma)
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{
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struct regmap *regmap = adc->dfsdm->regmap;
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int ret;
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ret = stm32_dfsdm_start_channel(adc->dfsdm, adc->ch_id);
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if (ret < 0)
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return ret;
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ret = stm32_dfsdm_filter_configure(adc->dfsdm, adc->fl_id,
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adc->ch_id);
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if (ret < 0)
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goto stop_channels;
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ret = stm32_dfsdm_start_filter(adc->dfsdm, adc->fl_id);
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if (ret < 0)
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goto stop_channels;
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return 0;
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stop_channels:
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regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
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DFSDM_CR1_RDMAEN_MASK, 0);
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regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
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DFSDM_CR1_RCONT_MASK, 0);
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stm32_dfsdm_stop_channel(adc->dfsdm, adc->fl_id);
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return ret;
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}
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static void stm32_dfsdm_stop_conv(struct stm32_dfsdm_adc *adc)
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{
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struct regmap *regmap = adc->dfsdm->regmap;
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stm32_dfsdm_stop_filter(adc->dfsdm, adc->fl_id);
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/* Clean conversion options */
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regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
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DFSDM_CR1_RDMAEN_MASK, 0);
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regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
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DFSDM_CR1_RCONT_MASK, 0);
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stm32_dfsdm_stop_channel(adc->dfsdm, adc->ch_id);
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}
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static int stm32_dfsdm_single_conv(struct iio_dev *indio_dev,
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const struct iio_chan_spec *chan, int *res)
|
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{
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struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
|
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long timeout;
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int ret;
|
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|
||||
reinit_completion(&adc->completion);
|
||||
|
||||
adc->buffer = res;
|
||||
|
||||
ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
|
||||
DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(1));
|
||||
if (ret < 0)
|
||||
goto stop_dfsdm;
|
||||
|
||||
ret = stm32_dfsdm_start_conv(adc, false);
|
||||
if (ret < 0) {
|
||||
regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
|
||||
DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
|
||||
goto stop_dfsdm;
|
||||
}
|
||||
|
||||
timeout = wait_for_completion_interruptible_timeout(&adc->completion,
|
||||
DFSDM_TIMEOUT);
|
||||
|
||||
/* Mask IRQ for regular conversion achievement*/
|
||||
regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
|
||||
DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
|
||||
|
||||
if (timeout == 0)
|
||||
ret = -ETIMEDOUT;
|
||||
else if (timeout < 0)
|
||||
ret = timeout;
|
||||
else
|
||||
ret = IIO_VAL_INT;
|
||||
|
||||
stm32_dfsdm_stop_conv(adc);
|
||||
|
||||
stop_dfsdm:
|
||||
stm32_dfsdm_stop_dfsdm(adc->dfsdm);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int stm32_dfsdm_write_raw(struct iio_dev *indio_dev,
|
||||
struct iio_chan_spec const *chan,
|
||||
int val, int val2, long mask)
|
||||
{
|
||||
struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
|
||||
struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
|
||||
int ret = -EINVAL;
|
||||
|
||||
if (mask == IIO_CHAN_INFO_OVERSAMPLING_RATIO) {
|
||||
ret = stm32_dfsdm_set_osrs(fl, 0, val);
|
||||
if (!ret)
|
||||
adc->oversamp = val;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int stm32_dfsdm_read_raw(struct iio_dev *indio_dev,
|
||||
struct iio_chan_spec const *chan, int *val,
|
||||
int *val2, long mask)
|
||||
{
|
||||
struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
|
||||
int ret;
|
||||
|
||||
switch (mask) {
|
||||
case IIO_CHAN_INFO_RAW:
|
||||
ret = iio_hw_consumer_enable(adc->hwc);
|
||||
if (ret < 0) {
|
||||
dev_err(&indio_dev->dev,
|
||||
"%s: IIO enable failed (channel %d)\n",
|
||||
__func__, chan->channel);
|
||||
return ret;
|
||||
}
|
||||
ret = stm32_dfsdm_single_conv(indio_dev, chan, val);
|
||||
iio_hw_consumer_disable(adc->hwc);
|
||||
if (ret < 0) {
|
||||
dev_err(&indio_dev->dev,
|
||||
"%s: Conversion failed (channel %d)\n",
|
||||
__func__, chan->channel);
|
||||
return ret;
|
||||
}
|
||||
return IIO_VAL_INT;
|
||||
|
||||
case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
|
||||
*val = adc->oversamp;
|
||||
|
||||
return IIO_VAL_INT;
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static const struct iio_info stm32_dfsdm_info_adc = {
|
||||
.read_raw = stm32_dfsdm_read_raw,
|
||||
.write_raw = stm32_dfsdm_write_raw,
|
||||
};
|
||||
|
||||
static irqreturn_t stm32_dfsdm_irq(int irq, void *arg)
|
||||
{
|
||||
struct stm32_dfsdm_adc *adc = arg;
|
||||
struct iio_dev *indio_dev = iio_priv_to_dev(adc);
|
||||
struct regmap *regmap = adc->dfsdm->regmap;
|
||||
unsigned int status, int_en;
|
||||
|
||||
regmap_read(regmap, DFSDM_ISR(adc->fl_id), &status);
|
||||
regmap_read(regmap, DFSDM_CR2(adc->fl_id), &int_en);
|
||||
|
||||
if (status & DFSDM_ISR_REOCF_MASK) {
|
||||
/* Read the data register clean the IRQ status */
|
||||
regmap_read(regmap, DFSDM_RDATAR(adc->fl_id), adc->buffer);
|
||||
complete(&adc->completion);
|
||||
}
|
||||
|
||||
if (status & DFSDM_ISR_ROVRF_MASK) {
|
||||
if (int_en & DFSDM_CR2_ROVRIE_MASK)
|
||||
dev_warn(&indio_dev->dev, "Overrun detected\n");
|
||||
regmap_update_bits(regmap, DFSDM_ICR(adc->fl_id),
|
||||
DFSDM_ICR_CLRROVRF_MASK,
|
||||
DFSDM_ICR_CLRROVRF_MASK);
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int stm32_dfsdm_adc_chan_init_one(struct iio_dev *indio_dev,
|
||||
struct iio_chan_spec *ch)
|
||||
{
|
||||
struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
|
||||
int ret;
|
||||
|
||||
ret = stm32_dfsdm_channel_parse_of(adc->dfsdm, indio_dev, ch);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ch->type = IIO_VOLTAGE;
|
||||
ch->indexed = 1;
|
||||
|
||||
/*
|
||||
* IIO_CHAN_INFO_RAW: used to compute regular conversion
|
||||
* IIO_CHAN_INFO_OVERSAMPLING_RATIO: used to set oversampling
|
||||
*/
|
||||
ch->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
|
||||
ch->info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO);
|
||||
|
||||
ch->scan_type.sign = 'u';
|
||||
ch->scan_type.realbits = 24;
|
||||
ch->scan_type.storagebits = 32;
|
||||
adc->ch_id = ch->channel;
|
||||
|
||||
return stm32_dfsdm_chan_configure(adc->dfsdm,
|
||||
&adc->dfsdm->ch_list[ch->channel]);
|
||||
}
|
||||
|
||||
static int stm32_dfsdm_adc_init(struct iio_dev *indio_dev)
|
||||
{
|
||||
struct iio_chan_spec *ch;
|
||||
struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
|
||||
int num_ch;
|
||||
int ret, chan_idx;
|
||||
|
||||
adc->oversamp = DFSDM_DEFAULT_OVERSAMPLING;
|
||||
ret = stm32_dfsdm_set_osrs(&adc->dfsdm->fl_list[adc->fl_id], 0,
|
||||
adc->oversamp);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
num_ch = of_property_count_u32_elems(indio_dev->dev.of_node,
|
||||
"st,adc-channels");
|
||||
if (num_ch < 0 || num_ch > adc->dfsdm->num_chs) {
|
||||
dev_err(&indio_dev->dev, "Bad st,adc-channels\n");
|
||||
return num_ch < 0 ? num_ch : -EINVAL;
|
||||
}
|
||||
|
||||
/* Bind to SD modulator IIO device */
|
||||
adc->hwc = devm_iio_hw_consumer_alloc(&indio_dev->dev);
|
||||
if (IS_ERR(adc->hwc))
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
ch = devm_kcalloc(&indio_dev->dev, num_ch, sizeof(*ch),
|
||||
GFP_KERNEL);
|
||||
if (!ch)
|
||||
return -ENOMEM;
|
||||
|
||||
for (chan_idx = 0; chan_idx < num_ch; chan_idx++) {
|
||||
ch->scan_index = chan_idx;
|
||||
ret = stm32_dfsdm_adc_chan_init_one(indio_dev, ch);
|
||||
if (ret < 0) {
|
||||
dev_err(&indio_dev->dev, "Channels init failed\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
indio_dev->num_channels = num_ch;
|
||||
indio_dev->channels = ch;
|
||||
|
||||
init_completion(&adc->completion);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_adc_data = {
|
||||
.type = DFSDM_IIO,
|
||||
.init = stm32_dfsdm_adc_init,
|
||||
};
|
||||
|
||||
static const struct of_device_id stm32_dfsdm_adc_match[] = {
|
||||
{
|
||||
.compatible = "st,stm32-dfsdm-adc",
|
||||
.data = &stm32h7_dfsdm_adc_data,
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
||||
static int stm32_dfsdm_adc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct stm32_dfsdm_adc *adc;
|
||||
struct device_node *np = dev->of_node;
|
||||
const struct stm32_dfsdm_dev_data *dev_data;
|
||||
struct iio_dev *iio;
|
||||
const struct of_device_id *of_id;
|
||||
char *name;
|
||||
int ret, irq, val;
|
||||
|
||||
of_id = of_match_node(stm32_dfsdm_adc_match, np);
|
||||
if (!of_id->data) {
|
||||
dev_err(&pdev->dev, "Data associated to device is missing\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
dev_data = (const struct stm32_dfsdm_dev_data *)of_id->data;
|
||||
|
||||
iio = devm_iio_device_alloc(dev, sizeof(*adc));
|
||||
if (IS_ERR(iio)) {
|
||||
dev_err(dev, "%s: Failed to allocate IIO\n", __func__);
|
||||
return PTR_ERR(iio);
|
||||
}
|
||||
|
||||
adc = iio_priv(iio);
|
||||
if (IS_ERR(adc)) {
|
||||
dev_err(dev, "%s: Failed to allocate ADC\n", __func__);
|
||||
return PTR_ERR(adc);
|
||||
}
|
||||
adc->dfsdm = dev_get_drvdata(dev->parent);
|
||||
|
||||
iio->dev.parent = dev;
|
||||
iio->dev.of_node = np;
|
||||
iio->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
|
||||
|
||||
platform_set_drvdata(pdev, adc);
|
||||
|
||||
ret = of_property_read_u32(dev->of_node, "reg", &adc->fl_id);
|
||||
if (ret != 0) {
|
||||
dev_err(dev, "Missing reg property\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
name = devm_kzalloc(dev, sizeof("dfsdm-adc0"), GFP_KERNEL);
|
||||
if (!name)
|
||||
return -ENOMEM;
|
||||
iio->info = &stm32_dfsdm_info_adc;
|
||||
snprintf(name, sizeof("dfsdm-adc0"), "dfsdm-adc%d", adc->fl_id);
|
||||
iio->name = name;
|
||||
|
||||
/*
|
||||
* In a first step IRQs generated for channels are not treated.
|
||||
* So IRQ associated to filter instance 0 is dedicated to the Filter 0.
|
||||
*/
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
ret = devm_request_irq(dev, irq, stm32_dfsdm_irq,
|
||||
0, pdev->name, adc);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "Failed to request IRQ\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = of_property_read_u32(dev->of_node, "st,filter-order", &val);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "Failed to set filter order\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
adc->dfsdm->fl_list[adc->fl_id].ford = val;
|
||||
|
||||
ret = of_property_read_u32(dev->of_node, "st,filter0-sync", &val);
|
||||
if (!ret)
|
||||
adc->dfsdm->fl_list[adc->fl_id].sync_mode = val;
|
||||
|
||||
adc->dev_data = dev_data;
|
||||
ret = dev_data->init(iio);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
return iio_device_register(iio);
|
||||
}
|
||||
|
||||
static int stm32_dfsdm_adc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct stm32_dfsdm_adc *adc = platform_get_drvdata(pdev);
|
||||
struct iio_dev *indio_dev = iio_priv_to_dev(adc);
|
||||
|
||||
iio_device_unregister(indio_dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver stm32_dfsdm_adc_driver = {
|
||||
.driver = {
|
||||
.name = "stm32-dfsdm-adc",
|
||||
.of_match_table = stm32_dfsdm_adc_match,
|
||||
},
|
||||
.probe = stm32_dfsdm_adc_probe,
|
||||
.remove = stm32_dfsdm_adc_remove,
|
||||
};
|
||||
module_platform_driver(stm32_dfsdm_adc_driver);
|
||||
|
||||
MODULE_DESCRIPTION("STM32 sigma delta ADC");
|
||||
MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen@st.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Загрузка…
Ссылка в новой задаче