Pin control bulk changes for the v5.17 kernel cycle
Core changes:
- New standard enumerator and corresponding device tree bindings
for output impedance pin configuration. (Implemented and used
in the Renesas rzg2l driver.)
- Cleanup of Kconfig and Makefile to be somewhat orderly and
alphabetic.
New drivers:
- Samsung Exynos 7885 pin controller.
- Ocelot LAN966x pin controller.
- Qualcomm SDX65 pin controller.
- Qualcomm SM8450 pin controller.
- Qualcomm PM8019, PM8226 and PM2250 pin controllers.
- NXP/Freescale i.MXRT1050 pin controller.
- Intel Thunder Bay pin controller.
Enhancements:
- Introduction of the string library helper function
"kasprintf_strarray()" and subsequent use in Rockchip, ST and
Armada pin control drivers, as well as the GPIO mockup driver.
- The Ocelot pin controller has been extensively rewritten to
use regmap and other modern kernel infrastructure.
- The Microchip SGPIO driver has been converted to use regmap.
- The SPEAr driver had been converted to use regmap.
- Substantial cleanups and janitorial on the Apple pin control
driver that was merged for v5.16.
- Janitorial to remove of_node assignments in the GPIO portions
that anyway get this handled in the GPIO core.
- Minor cleanups and improvements in several pin controllers.
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Merge tag 'pinctrl-v5.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control bulk updates from Linus Walleij:
"Core changes:
- New standard enumerator and corresponding device tree bindings for
output impedance pin configuration. (Implemented and used in the
Renesas rzg2l driver.)
- Cleanup of Kconfig and Makefile to be somewhat orderly and
alphabetic.
New drivers:
- Samsung Exynos 7885 pin controller.
- Ocelot LAN966x pin controller.
- Qualcomm SDX65 pin controller.
- Qualcomm SM8450 pin controller.
- Qualcomm PM8019, PM8226 and PM2250 pin controllers.
- NXP/Freescale i.MXRT1050 pin controller.
- Intel Thunder Bay pin controller.
Enhancements:
- Introduction of the string library helper function
"kasprintf_strarray()" and subsequent use in Rockchip, ST and
Armada pin control drivers, as well as the GPIO mockup driver.
- The Ocelot pin controller has been extensively rewritten to use
regmap and other modern kernel infrastructure.
- The Microchip SGPIO driver has been converted to use regmap.
- The SPEAr driver had been converted to use regmap.
- Substantial cleanups and janitorial on the Apple pin control driver
that was merged for v5.16.
- Janitorial to remove of_node assignments in the GPIO portions that
anyway get this handled in the GPIO core.
- Minor cleanups and improvements in several pin controllers"
* tag 'pinctrl-v5.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (98 commits)
pinctrl: imx: fix assigning groups names
dt-bindings: pinctrl: mt8195: add wrapping node of pin configurations
pinctrl: bcm: ns: use generic groups & functions helpers
pinctrl: imx: fix allocation result check
pinctrl: samsung: Use platform_get_irq_optional() to get the interrupt
pinctrl: Propagate firmware node from a parent device
dt-bindings: pinctrl: qcom: Add SDX65 pinctrl bindings
pinctrl: add one more "const" for generic function groups
pinctrl: keembay: rework loops looking for groups names
pinctrl: keembay: comment process of building functions a bit
pinctrl: imx: prepare for making "group_names" in "function_desc" const
ARM: dts: gpio-ranges property is now required
pinctrl: aspeed: fix unmet dependencies on MFD_SYSCON for PINCTRL_ASPEED
pinctrl: Get rid of duplicate of_node assignment in the drivers
pinctrl-sunxi: don't call pinctrl_gpio_direction()
pinctrl-bcm2835: don't call pinctrl_gpio_direction()
pinctrl: bcm2835: Silence uninit warning
pinctrl: Sort Kconfig and Makefile entries alphabetically
pinctrl: Add Intel Thunder Bay pinctrl driver
dt-bindings: pinctrl: Add bindings for Intel Thunderbay pinctrl driver
...
This commit is contained in:
Linus Torvalds
Коммит
e3084ed48f
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@ -184,6 +184,9 @@ patternProperties:
|
|||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
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required:
|
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- compatible
|
||||
- reg
|
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|
|
|
|||
|
|
@ -147,6 +147,7 @@ allOf:
|
|||
# boards are defining it at the moment so it would generate a lot of
|
||||
# warnings.
|
||||
|
||||
- $ref: "pinctrl.yaml#"
|
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- if:
|
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properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -72,6 +72,9 @@ patternProperties:
|
|||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -50,6 +50,9 @@ patternProperties:
|
|||
TXD3, TXD4, UART6, USB11D1, USB11H2, USB2D1, USB2H1, USBCKI, VGABIOS_ROM,
|
||||
VGAHS, VGAVS, VPI18, VPI24, VPI30, VPO12, VPO24, WDTRST1, WDTRST2]
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
|
|
|
|||
|
|
@ -62,6 +62,9 @@ patternProperties:
|
|||
USB11BHID, USB2AD, USB2AH, USB2BD, USB2BH, USBCKI, VGABIOSROM, VGAHS,
|
||||
VGAVS, VPI24, VPO, WDTRST1, WDTRST2]
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- aspeed,external-nodes
|
||||
|
|
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|||
|
|
@ -83,6 +83,9 @@ patternProperties:
|
|||
UART7, UART8, UART9, USBA, USBB, VB, VGAHS, VGAVS, WDTRST1, WDTRST2,
|
||||
WDTRST3, WDTRST4]
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
|
|
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|||
|
|
@ -37,6 +37,9 @@ patternProperties:
|
|||
enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7,
|
||||
gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio40 ]
|
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|
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allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
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- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -41,6 +41,9 @@ patternProperties:
|
|||
vdsl_phy_override_1_grp, vdsl_phy_override_2_grp,
|
||||
vdsl_phy_override_3_grp, dsl_gpio8, dsl_gpio9 ]
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
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|
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required:
|
||||
- compatible
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- reg
|
||||
|
|
|
|||
|
|
@ -36,6 +36,9 @@ patternProperties:
|
|||
gpio20, gpio25, gpio26, gpio27, gpio28, hsspi_cs1,
|
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usb_port1 ]
|
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|
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allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
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|
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required:
|
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- compatible
|
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- reg
|
||||
|
|
|
|||
|
|
@ -34,6 +34,9 @@ patternProperties:
|
|||
enum: [ ebi_cs_grp, uart1_grp, serial_led_grp, legacy_led_grp,
|
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led_grp, spi_cs_grp, utopia_grp, pwm_syn_clk, sys_irq_grp ]
|
||||
|
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allOf:
|
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- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -41,6 +41,9 @@ patternProperties:
|
|||
gpio15, gpio16, gpio17, gpio18, gpio19, gpio20, gpio21,
|
||||
gpio22, gpio23, gpio24, gpio25, gpio26, gpio27, nand_grp ]
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -42,6 +42,9 @@ patternProperties:
|
|||
gpio24, gpio25, gpio26, gpio27, gpio28, gpio29, gpio30,
|
||||
gpio31, uart1_grp ]
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -53,6 +53,7 @@ patternProperties:
|
|||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
- if:
|
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properties:
|
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compatible:
|
||||
|
|
@ -77,7 +78,7 @@ additionalProperties: false
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|||
|
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examples:
|
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- |
|
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pin-controller@1800c1c0 {
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pinctrl@1800c1c0 {
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compatible = "brcm,bcm4708-pinmux";
|
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reg = <0x1800c1c0 0x24>;
|
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reg-names = "cru_gpio_control";
|
||||
|
|
|
|||
|
|
@ -137,6 +137,9 @@ patternProperties:
|
|||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
@ -151,9 +154,9 @@ examples:
|
|||
#include <dt-bindings/clock/k210-clk.h>
|
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#include <dt-bindings/reset/k210-rst.h>
|
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|
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fpioa: pinmux@502B0000 {
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fpioa: pinmux@502b0000 {
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compatible = "canaan,k210-fpioa";
|
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reg = <0x502B0000 0x100>;
|
||||
reg = <0x502b0000 0x100>;
|
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clocks = <&sysclk K210_CLK_FPIOA>,
|
||||
<&sysclk K210_CLK_APB0>;
|
||||
clock-names = "ref", "pclk";
|
||||
|
|
|
|||
|
|
@ -181,6 +181,9 @@ properties:
|
|||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- gpio-controller
|
||||
|
|
|
|||
|
|
@ -117,6 +117,9 @@ properties:
|
|||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- pinctrl-0
|
||||
- pinctrl-names
|
||||
|
|
|
|||
|
|
@ -58,6 +58,9 @@ patternProperties:
|
|||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -58,6 +58,9 @@ patternProperties:
|
|||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -58,6 +58,9 @@ patternProperties:
|
|||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -58,6 +58,9 @@ patternProperties:
|
|||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -56,6 +56,9 @@ patternProperties:
|
|||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -0,0 +1,79 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/fsl,imxrt1050.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale IMXRT1050 IOMUX Controller
|
||||
|
||||
maintainers:
|
||||
- Giulio Benetti <giulio.benetti@benettiengineering.com>
|
||||
- Jesse Taube <Mr.Bossman075@gmail.com>
|
||||
|
||||
description:
|
||||
Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
|
||||
for common binding part and usage.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imxrt1050-iomuxc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
# Client device subnode's properties
|
||||
patternProperties:
|
||||
'grp$':
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
|
||||
properties:
|
||||
fsl,pins:
|
||||
description:
|
||||
each entry consists of 6 integers and represents the mux and config
|
||||
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
|
||||
mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
|
||||
be found in <include/dt-bindings/pinctrl/pins-imxrt1050.h>. The last
|
||||
integer CONFIG is the pad setting value like pull-up on this pin. Please
|
||||
refer to i.MXRT1050 Reference Manual for detailed CONFIG settings.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-matrix
|
||||
items:
|
||||
items:
|
||||
- description: |
|
||||
"mux_reg" indicates the offset of mux register.
|
||||
- description: |
|
||||
"conf_reg" indicates the offset of pad configuration register.
|
||||
- description: |
|
||||
"input_reg" indicates the offset of select input register.
|
||||
- description: |
|
||||
"mux_val" indicates the mux value to be applied.
|
||||
- description: |
|
||||
"input_val" indicates the select input value to be applied.
|
||||
- description: |
|
||||
"pad_setting" indicates the pad configuration value to be applied.
|
||||
|
||||
required:
|
||||
- fsl,pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
iomuxc: iomuxc@401f8000 {
|
||||
compatible = "fsl,imxrt1050-iomuxc";
|
||||
reg = <0x401f8000 0x4000>;
|
||||
|
||||
pinctrl_lpuart1: lpuart1grp {
|
||||
fsl,pins =
|
||||
<0x0EC 0x2DC 0x000 0x2 0x0 0xf1>,
|
||||
<0x0F0 0x2E0 0x000 0x2 0x0 0xf1>;
|
||||
};
|
||||
};
|
||||
|
|
@ -28,9 +28,6 @@ maintainers:
|
|||
- Paul Cercueil <paul@crapouillou.net>
|
||||
|
||||
properties:
|
||||
nodename:
|
||||
pattern: "^pinctrl@[0-9a-f]+$"
|
||||
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
|
|
@ -121,6 +118,9 @@ patternProperties:
|
|||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
@ -169,7 +169,7 @@ additionalProperties:
|
|||
|
||||
examples:
|
||||
- |
|
||||
pin-controller@10010000 {
|
||||
pinctrl@10010000 {
|
||||
compatible = "ingenic,jz4770-pinctrl";
|
||||
reg = <0x10010000 0x600>;
|
||||
|
||||
|
|
|
|||
|
|
@ -47,6 +47,9 @@ patternProperties:
|
|||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -0,0 +1,119 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-thunderbay.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Intel Thunder Bay pin controller Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
|
||||
|
||||
description: |
|
||||
Intel Thunder Bay SoC integrates a pin controller which enables control
|
||||
of pin directions, input/output values and configuration
|
||||
for a total of 67 pins.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: intel,thunderbay-pinctrl
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
'#gpio-cells':
|
||||
const: 2
|
||||
|
||||
gpio-ranges:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
description:
|
||||
Specifies the interrupt lines to be used by the controller.
|
||||
maxItems: 2
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
'#interrupt-cells':
|
||||
const: 2
|
||||
|
||||
patternProperties:
|
||||
'^gpio@[0-9a-f]*$':
|
||||
type: object
|
||||
|
||||
description:
|
||||
Child nodes can be specified to contain pin configuration information,
|
||||
which can then be utilized by pinctrl client devices.
|
||||
The following properties are supported.
|
||||
|
||||
properties:
|
||||
pins:
|
||||
description: |
|
||||
The name(s) of the pins to be configured in the child node.
|
||||
Supported pin names are "GPIO0" up to "GPIO66".
|
||||
|
||||
bias-disable: true
|
||||
|
||||
bias-pull-down: true
|
||||
|
||||
bias-pull-up: true
|
||||
|
||||
drive-strength:
|
||||
description: Drive strength for the pad.
|
||||
enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
|
||||
|
||||
bias-bus-hold:
|
||||
type: boolean
|
||||
|
||||
input-schmitt-enable:
|
||||
type: boolean
|
||||
|
||||
slew-rate:
|
||||
description: GPIO slew rate control.
|
||||
0 - Slow
|
||||
1 - Fast
|
||||
enum: [0, 1]
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- gpio-controller
|
||||
- '#gpio-cells'
|
||||
- gpio-ranges
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- '#interrupt-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
// Example 1
|
||||
pinctrl0: gpio@0 {
|
||||
compatible = "intel,thunderbay-pinctrl";
|
||||
reg = <0x600b0000 0x88>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <0x2>;
|
||||
gpio-ranges = <&pinctrl0 0 0 67>;
|
||||
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
// Example 2
|
||||
pinctrl1: gpio@1 {
|
||||
compatible = "intel,thunderbay-pinctrl";
|
||||
reg = <0x600c0000 0x88>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <0x2>;
|
||||
gpio-ranges = <&pinctrl1 0 0 53>;
|
||||
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
|
@ -64,6 +64,9 @@ required:
|
|||
- gpio-controller
|
||||
- "#gpio-cells"
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
patternProperties:
|
||||
'-[0-9]+$':
|
||||
type: object
|
||||
|
|
|
|||
|
|
@ -59,6 +59,9 @@ properties:
|
|||
"#interrupt-cells":
|
||||
const: 2
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -45,6 +45,9 @@ properties:
|
|||
"#interrupt-cells":
|
||||
const: 2
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -42,6 +42,9 @@ properties:
|
|||
"#interrupt-cells":
|
||||
const: 2
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -56,6 +56,9 @@ properties:
|
|||
"#interrupt-cells":
|
||||
const: 2
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -56,6 +56,9 @@ properties:
|
|||
"#interrupt-cells":
|
||||
const: 2
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -4,7 +4,8 @@ Microsemi Ocelot pin controller Device Tree Bindings
|
|||
Required properties:
|
||||
- compatible : Should be "mscc,ocelot-pinctrl",
|
||||
"mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl",
|
||||
"mscc,luton-pinctrl" or "mscc,serval-pinctrl"
|
||||
"mscc,luton-pinctrl", "mscc,serval-pinctrl" or
|
||||
"microchip,lan966x-pinctrl"
|
||||
- reg : Address and length of the register set for the device
|
||||
- gpio-controller : Indicates this device is a GPIO controller
|
||||
- #gpio-cells : Must be 2.
|
||||
|
|
|
|||
|
|
@ -114,6 +114,9 @@ properties:
|
|||
description: enable output on a pin without actively driving it
|
||||
(such as enabling an output buffer)
|
||||
|
||||
output-impedance-ohms:
|
||||
description: set the output impedance of a pin to at most X ohms
|
||||
|
||||
output-low:
|
||||
type: boolean
|
||||
description: set the pin to output mode with low level
|
||||
|
|
|
|||
|
|
@ -97,47 +97,8 @@ For example:
|
|||
};
|
||||
|
||||
== Pin controller devices ==
|
||||
Required properties: See the pin controller driver specific documentation
|
||||
|
||||
Optional properties:
|
||||
#pinctrl-cells: Number of pin control cells in addition to the index within the
|
||||
pin controller device instance
|
||||
|
||||
pinctrl-use-default: Boolean. Indicates that the OS can use the boot default
|
||||
pin configuration. This allows using an OS that does not have a
|
||||
driver for the pin controller. This property can be set either
|
||||
globally for the pin controller or in child nodes for individual
|
||||
pin group control.
|
||||
|
||||
Pin controller devices should contain the pin configuration nodes that client
|
||||
devices reference.
|
||||
|
||||
For example:
|
||||
|
||||
pincontroller {
|
||||
... /* Standard DT properties for the device itself elided */
|
||||
|
||||
state_0_node_a {
|
||||
...
|
||||
};
|
||||
state_1_node_a {
|
||||
...
|
||||
};
|
||||
state_1_node_b {
|
||||
...
|
||||
};
|
||||
}
|
||||
|
||||
The contents of each of those pin configuration child nodes is defined
|
||||
entirely by the binding for the individual pin controller device. There
|
||||
exists no common standard for this content. The pinctrl framework only
|
||||
provides generic helper bindings that the pin controller driver can use.
|
||||
|
||||
The pin configuration nodes need not be direct children of the pin controller
|
||||
device; they may be grandchildren, for example. Whether this is legal, and
|
||||
whether there is any interaction between the child and intermediate parent
|
||||
nodes, is again defined entirely by the binding for the individual pin
|
||||
controller device.
|
||||
See pinctrl.yaml
|
||||
|
||||
== Generic pin multiplexing node content ==
|
||||
|
||||
|
|
|
|||
|
|
@ -108,6 +108,9 @@ patternProperties:
|
|||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -55,137 +55,162 @@ properties:
|
|||
Identifying i2c pins pull up/down type which is RSEL. It can support
|
||||
RSEL define or si unit value(ohm) to set different resistance.
|
||||
|
||||
#PIN CONFIGURATION NODES
|
||||
# PIN CONFIGURATION NODES
|
||||
patternProperties:
|
||||
'-pins$':
|
||||
type: object
|
||||
description: |
|
||||
A pinctrl node should contain at least one subnodes representing the
|
||||
pinctrl groups available on the machine. Each subnode will list the
|
||||
pins it needs, and how they should be configured, with regard to muxer
|
||||
configuration, pullups, drive strength, input enable/disable and
|
||||
input schmitt.
|
||||
An example of using macro:
|
||||
pincontroller {
|
||||
/* GPIO0 set as multifunction GPIO0 */
|
||||
gpio_pin {
|
||||
pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
|
||||
};
|
||||
/* GPIO8 set as multifunction SDA0 */
|
||||
i2c0_pin {
|
||||
pinmux = <PINMUX_GPIO8__FUNC_SDA0>;
|
||||
};
|
||||
};
|
||||
$ref: "pinmux-node.yaml"
|
||||
|
||||
properties:
|
||||
pinmux:
|
||||
description: |
|
||||
Integer array, represents gpio pin number and mux setting.
|
||||
Supported pin number and mux varies for different SoCs, and are defined
|
||||
as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
|
||||
|
||||
drive-strength:
|
||||
enum: [2, 4, 6, 8, 10, 12, 14, 16]
|
||||
|
||||
bias-pull-down:
|
||||
description: |
|
||||
For pull down type is normal, it don't need add RSEL & R1R0 define
|
||||
and resistance value.
|
||||
For pull down type is PUPD/R0/R1 type, it can add R1R0 define to
|
||||
set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
|
||||
"MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & "MTK_PUPD_SET_R1R0_11"
|
||||
define in mt8195.
|
||||
For pull down type is RSEL, it can add RSEL define & resistance value(ohm)
|
||||
to set different resistance by identifying property "mediatek,rsel_resistance_in_si_unit".
|
||||
It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001"
|
||||
& "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & "MTK_PULL_SET_RSEL_100"
|
||||
& "MTK_PULL_SET_RSEL_101" & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111"
|
||||
define in mt8195. It can also support resistance value(ohm) "75000" & "5000" in mt8195.
|
||||
oneOf:
|
||||
- enum: [100, 101, 102, 103]
|
||||
- description: mt8195 pull down PUPD/R0/R1 type define value.
|
||||
- enum: [200, 201, 202, 203, 204, 205, 206, 207]
|
||||
- description: mt8195 pull down RSEL type define value.
|
||||
- enum: [75000, 5000]
|
||||
- description: mt8195 pull down RSEL type si unit value(ohm).
|
||||
|
||||
An example of using RSEL define:
|
||||
pincontroller {
|
||||
i2c0_pin {
|
||||
pinmux = <PINMUX_GPIO8__FUNC_SDA0>;
|
||||
bias-pull-down = <MTK_PULL_SET_RSEL_001>;
|
||||
};
|
||||
};
|
||||
An example of using si unit resistance value(ohm):
|
||||
&pio {
|
||||
mediatek,rsel_resistance_in_si_unit;
|
||||
}
|
||||
pincontroller {
|
||||
i2c0_pin {
|
||||
pinmux = <PINMUX_GPIO8__FUNC_SDA0>;
|
||||
bias-pull-down = <75000>;
|
||||
};
|
||||
};
|
||||
|
||||
bias-pull-up:
|
||||
description: |
|
||||
For pull up type is normal, it don't need add RSEL & R1R0 define
|
||||
and resistance value.
|
||||
For pull up type is PUPD/R0/R1 type, it can add R1R0 define to
|
||||
set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
|
||||
"MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & "MTK_PUPD_SET_R1R0_11"
|
||||
define in mt8195.
|
||||
For pull up type is RSEL, it can add RSEL define & resistance value(ohm)
|
||||
to set different resistance by identifying property "mediatek,rsel_resistance_in_si_unit".
|
||||
It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001"
|
||||
& "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & "MTK_PULL_SET_RSEL_100"
|
||||
& "MTK_PULL_SET_RSEL_101" & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111"
|
||||
define in mt8195. It can also support resistance value(ohm)
|
||||
"1000" & "1500" & "2000" & "3000" & "4000" & "5000" & "10000" & "75000" in mt8195.
|
||||
oneOf:
|
||||
- enum: [100, 101, 102, 103]
|
||||
- description: mt8195 pull up PUPD/R0/R1 type define value.
|
||||
- enum: [200, 201, 202, 203, 204, 205, 206, 207]
|
||||
- description: mt8195 pull up RSEL type define value.
|
||||
- enum: [1000, 1500, 2000, 3000, 4000, 5000, 10000, 75000]
|
||||
- description: mt8195 pull up RSEL type si unit value(ohm).
|
||||
An example of using RSEL define:
|
||||
pincontroller {
|
||||
i2c0_pin {
|
||||
pinmux = <PINMUX_GPIO8__FUNC_SDA0>;
|
||||
bias-pull-up = <MTK_PULL_SET_RSEL_001>;
|
||||
};
|
||||
};
|
||||
An example of using si unit resistance value(ohm):
|
||||
&pio {
|
||||
mediatek,rsel_resistance_in_si_unit;
|
||||
}
|
||||
pincontroller {
|
||||
i2c0_pin {
|
||||
pinmux = <PINMUX_GPIO8__FUNC_SDA0>;
|
||||
bias-pull-up = <1000>;
|
||||
};
|
||||
};
|
||||
|
||||
bias-disable: true
|
||||
|
||||
output-high: true
|
||||
|
||||
output-low: true
|
||||
|
||||
input-enable: true
|
||||
|
||||
input-disable: true
|
||||
|
||||
input-schmitt-enable: true
|
||||
|
||||
input-schmitt-disable: true
|
||||
|
||||
required:
|
||||
- pinmux
|
||||
|
||||
additionalProperties: false
|
||||
patternProperties:
|
||||
'^pins':
|
||||
type: object
|
||||
additionalProperties: false
|
||||
description: |
|
||||
A pinctrl node should contain at least one subnodes representing the
|
||||
pinctrl groups available on the machine. Each subnode will list the
|
||||
pins it needs, and how they should be configured, with regard to muxer
|
||||
configuration, pullups, drive strength, input enable/disable and
|
||||
input schmitt.
|
||||
An example of using macro:
|
||||
pincontroller {
|
||||
/* GPIO0 set as multifunction GPIO0 */
|
||||
gpio-pins {
|
||||
pins {
|
||||
pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
|
||||
}
|
||||
};
|
||||
/* GPIO8 set as multifunction SDA0 */
|
||||
i2c0-pins {
|
||||
pins {
|
||||
pinmux = <PINMUX_GPIO8__FUNC_SDA0>;
|
||||
}
|
||||
};
|
||||
};
|
||||
$ref: "pinmux-node.yaml"
|
||||
|
||||
properties:
|
||||
pinmux:
|
||||
description: |
|
||||
Integer array, represents gpio pin number and mux setting.
|
||||
Supported pin number and mux varies for different SoCs, and are
|
||||
defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h
|
||||
directly.
|
||||
|
||||
drive-strength:
|
||||
enum: [2, 4, 6, 8, 10, 12, 14, 16]
|
||||
|
||||
bias-pull-down:
|
||||
description: |
|
||||
For pull down type is normal, it don't need add RSEL & R1R0 define
|
||||
and resistance value.
|
||||
For pull down type is PUPD/R0/R1 type, it can add R1R0 define to
|
||||
set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
|
||||
"MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
|
||||
"MTK_PUPD_SET_R1R0_11" define in mt8195.
|
||||
For pull down type is RSEL, it can add RSEL define & resistance
|
||||
value(ohm) to set different resistance by identifying property
|
||||
"mediatek,rsel_resistance_in_si_unit".
|
||||
It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001"
|
||||
& "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011"
|
||||
& "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101"
|
||||
& "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111"
|
||||
define in mt8195. It can also support resistance value(ohm)
|
||||
"75000" & "5000" in mt8195.
|
||||
oneOf:
|
||||
- enum: [100, 101, 102, 103]
|
||||
- description: mt8195 pull down PUPD/R0/R1 type define value.
|
||||
- enum: [200, 201, 202, 203, 204, 205, 206, 207]
|
||||
- description: mt8195 pull down RSEL type define value.
|
||||
- enum: [75000, 5000]
|
||||
- description: mt8195 pull down RSEL type si unit value(ohm).
|
||||
|
||||
An example of using RSEL define:
|
||||
pincontroller {
|
||||
i2c0_pin {
|
||||
pins {
|
||||
pinmux = <PINMUX_GPIO8__FUNC_SDA0>;
|
||||
bias-pull-down = <MTK_PULL_SET_RSEL_001>;
|
||||
}
|
||||
};
|
||||
};
|
||||
An example of using si unit resistance value(ohm):
|
||||
&pio {
|
||||
mediatek,rsel_resistance_in_si_unit;
|
||||
}
|
||||
pincontroller {
|
||||
i2c0_pin {
|
||||
pins {
|
||||
pinmux = <PINMUX_GPIO8__FUNC_SDA0>;
|
||||
bias-pull-down = <75000>;
|
||||
}
|
||||
};
|
||||
};
|
||||
|
||||
bias-pull-up:
|
||||
description: |
|
||||
For pull up type is normal, it don't need add RSEL & R1R0 define
|
||||
and resistance value.
|
||||
For pull up type is PUPD/R0/R1 type, it can add R1R0 define to
|
||||
set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
|
||||
"MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
|
||||
"MTK_PUPD_SET_R1R0_11" define in mt8195.
|
||||
For pull up type is RSEL, it can add RSEL define & resistance
|
||||
value(ohm) to set different resistance by identifying property
|
||||
"mediatek,rsel_resistance_in_si_unit".
|
||||
It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001"
|
||||
& "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011"
|
||||
& "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101"
|
||||
& "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111"
|
||||
define in mt8195. It can also support resistance value(ohm)
|
||||
"1000" & "1500" & "2000" & "3000" & "4000" & "5000" & "10000" &
|
||||
"75000" in mt8195.
|
||||
oneOf:
|
||||
- enum: [100, 101, 102, 103]
|
||||
- description: mt8195 pull up PUPD/R0/R1 type define value.
|
||||
- enum: [200, 201, 202, 203, 204, 205, 206, 207]
|
||||
- description: mt8195 pull up RSEL type define value.
|
||||
- enum: [1000, 1500, 2000, 3000, 4000, 5000, 10000, 75000]
|
||||
- description: mt8195 pull up RSEL type si unit value(ohm).
|
||||
An example of using RSEL define:
|
||||
pincontroller {
|
||||
i2c0-pins {
|
||||
pins {
|
||||
pinmux = <PINMUX_GPIO8__FUNC_SDA0>;
|
||||
bias-pull-up = <MTK_PULL_SET_RSEL_001>;
|
||||
}
|
||||
};
|
||||
};
|
||||
An example of using si unit resistance value(ohm):
|
||||
&pio {
|
||||
mediatek,rsel_resistance_in_si_unit;
|
||||
}
|
||||
pincontroller {
|
||||
i2c0-pins {
|
||||
pins {
|
||||
pinmux = <PINMUX_GPIO8__FUNC_SDA0>;
|
||||
bias-pull-up = <1000>;
|
||||
}
|
||||
};
|
||||
};
|
||||
|
||||
bias-disable: true
|
||||
|
||||
output-high: true
|
||||
|
||||
output-low: true
|
||||
|
||||
input-enable: true
|
||||
|
||||
input-disable: true
|
||||
|
||||
input-schmitt-enable: true
|
||||
|
||||
input-schmitt-disable: true
|
||||
|
||||
required:
|
||||
- pinmux
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
|
@ -201,30 +226,46 @@ additionalProperties: false
|
|||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
pio: pinctrl@10005000 {
|
||||
compatible = "mediatek,mt8195-pinctrl";
|
||||
reg = <0x10005000 0x1000>,
|
||||
<0x11d10000 0x1000>,
|
||||
<0x11d30000 0x1000>,
|
||||
<0x11d40000 0x1000>,
|
||||
<0x11e20000 0x1000>,
|
||||
<0x11eb0000 0x1000>,
|
||||
<0x11f40000 0x1000>,
|
||||
<0x1000b000 0x1000>;
|
||||
reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
|
||||
"iocfg_br", "iocfg_lm", "iocfg_rb",
|
||||
"iocfg_tl", "eint";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pio 0 0 144>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
#interrupt-cells = <2>;
|
||||
#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#
|
||||
pio: pinctrl@10005000 {
|
||||
compatible = "mediatek,mt8195-pinctrl";
|
||||
reg = <0x10005000 0x1000>,
|
||||
<0x11d10000 0x1000>,
|
||||
<0x11d30000 0x1000>,
|
||||
<0x11d40000 0x1000>,
|
||||
<0x11e20000 0x1000>,
|
||||
<0x11eb0000 0x1000>,
|
||||
<0x11f40000 0x1000>,
|
||||
<0x1000b000 0x1000>;
|
||||
reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
|
||||
"iocfg_br", "iocfg_lm", "iocfg_rb",
|
||||
"iocfg_tl", "eint";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pio 0 0 144>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
pio-pins {
|
||||
pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
|
||||
output-low;
|
||||
};
|
||||
};
|
||||
pio-pins {
|
||||
pins {
|
||||
pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
|
||||
output-low;
|
||||
};
|
||||
};
|
||||
|
||||
spi0-pins {
|
||||
pins-spi {
|
||||
pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>,
|
||||
<PINMUX_GPIO134__FUNC_SPIM0_MO>,
|
||||
<PINMUX_GPIO133__FUNC_SPIM0_CLK>;
|
||||
bias-disable;
|
||||
};
|
||||
pins-spi-mi {
|
||||
pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,45 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Pin controller device
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
- Rafał Miłecki <rafal@milecki.pl>
|
||||
|
||||
description: |
|
||||
Pin controller devices should contain the pin configuration nodes that client
|
||||
devices reference.
|
||||
|
||||
The contents of each of those pin configuration child nodes is defined
|
||||
entirely by the binding for the individual pin controller device. There
|
||||
exists no common standard for this content. The pinctrl framework only
|
||||
provides generic helper bindings that the pin controller driver can use.
|
||||
|
||||
The pin configuration nodes need not be direct children of the pin controller
|
||||
device; they may be grandchildren, for example. Whether this is legal, and
|
||||
whether there is any interaction between the child and intermediate parent
|
||||
nodes, is again defined entirely by the binding for the individual pin
|
||||
controller device.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^(pinctrl|pinmux)(@[0-9a-f]+)?$"
|
||||
|
||||
"#pinctrl-cells":
|
||||
description: >
|
||||
Number of pin control cells in addition to the index within the pin
|
||||
controller device instance.
|
||||
|
||||
pinctrl-use-default:
|
||||
type: boolean
|
||||
description: >
|
||||
Indicates that the OS can use the boot default pin configuration. This
|
||||
allows using an OS that does not have a driver for the pin controller.
|
||||
This property can be set either globally for the pin controller or in
|
||||
child nodes for individual pin group control.
|
||||
|
||||
additionalProperties: true
|
||||
|
|
@ -118,6 +118,9 @@ patternProperties:
|
|||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -103,6 +103,9 @@ patternProperties:
|
|||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@ description: |
|
|||
MDM9607 platform.
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
properties:
|
||||
|
|
|
|||
|
|
@ -97,6 +97,9 @@ patternProperties:
|
|||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -133,6 +133,9 @@ patternProperties:
|
|||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@ properties:
|
|||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- qcom,pm2250-gpio
|
||||
- qcom,pm660-gpio
|
||||
- qcom,pm660l-gpio
|
||||
- qcom,pm6150-gpio
|
||||
|
|
@ -26,10 +27,12 @@ properties:
|
|||
- qcom,pm8005-gpio
|
||||
- qcom,pm8008-gpio
|
||||
- qcom,pm8018-gpio
|
||||
- qcom,pm8019-gpio
|
||||
- qcom,pm8038-gpio
|
||||
- qcom,pm8058-gpio
|
||||
- qcom,pm8150-gpio
|
||||
- qcom,pm8150b-gpio
|
||||
- qcom,pm8226-gpio
|
||||
- qcom,pm8350-gpio
|
||||
- qcom,pm8350b-gpio
|
||||
- qcom,pm8350c-gpio
|
||||
|
|
|
|||
|
|
@ -118,6 +118,9 @@ patternProperties:
|
|||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -123,6 +123,9 @@ patternProperties:
|
|||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@ description: |
|
|||
SC8180X platform.
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
properties:
|
||||
|
|
|
|||
|
|
@ -118,6 +118,9 @@ patternProperties:
|
|||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -0,0 +1,191 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,sdx65-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. SDX65 TLMM block
|
||||
|
||||
maintainers:
|
||||
- Vamsi krishna Lanka <quic_vamslank@quicinc.com>
|
||||
|
||||
description:
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
SDX65 platform.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sdx65-tlmm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
'#interrupt-cells':
|
||||
description: Specifies the PIN numbers and Flags, as defined in
|
||||
include/dt-bindings/interrupt-controller/irq.h
|
||||
const: 2
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
'#gpio-cells':
|
||||
description: Specifying the pin number and flags, as defined in
|
||||
include/dt-bindings/gpio/gpio.h
|
||||
const: 2
|
||||
|
||||
gpio-ranges:
|
||||
maxItems: 1
|
||||
|
||||
gpio-reserved-ranges:
|
||||
maxItems: 1
|
||||
|
||||
#PIN CONFIGURATION NODES
|
||||
patternProperties:
|
||||
'-state$':
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-sdx65-tlmm-state"
|
||||
- patternProperties:
|
||||
".*":
|
||||
$ref: "#/$defs/qcom-sdx65-tlmm-state"
|
||||
'$defs':
|
||||
qcom-sdx65-tlmm-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
|
||||
|
||||
properties:
|
||||
pins:
|
||||
description:
|
||||
List of gpio pins affected by the properties specified in this subnode.
|
||||
items:
|
||||
oneOf:
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|10[0-7])$"
|
||||
- enum: [ ufs_reset, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data, sdc1_rclk ]
|
||||
minItems: 1
|
||||
maxItems: 150
|
||||
|
||||
function:
|
||||
description:
|
||||
Specify the alternative function to be configured for the specified
|
||||
pins. Functions are only valid for gpio pins.
|
||||
enum: [ blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens,
|
||||
bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8,
|
||||
qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b,
|
||||
dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10,
|
||||
blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12,
|
||||
mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11,
|
||||
atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char,
|
||||
cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b,
|
||||
pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c,
|
||||
qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4,
|
||||
qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5,
|
||||
atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6,
|
||||
atest_usb20, atest_char0, dac_calib10, qdss_stm10,
|
||||
qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6,
|
||||
blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11,
|
||||
qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1,
|
||||
qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11,
|
||||
dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6,
|
||||
qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14,
|
||||
dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem,
|
||||
dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto,
|
||||
dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0,
|
||||
dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25,
|
||||
sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2,
|
||||
qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3,
|
||||
uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9,
|
||||
blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7,
|
||||
qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11,
|
||||
blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0,
|
||||
cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4,
|
||||
blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4,
|
||||
qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus,
|
||||
isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s,
|
||||
qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b,
|
||||
sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b,
|
||||
gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12,
|
||||
qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29,
|
||||
tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27,
|
||||
qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk,
|
||||
sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b,
|
||||
sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b,
|
||||
ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b,
|
||||
blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt,
|
||||
pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11,
|
||||
qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx,
|
||||
qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3,
|
||||
gpio ]
|
||||
|
||||
drive-strength:
|
||||
enum: [2, 4, 6, 8, 10, 12, 14, 16]
|
||||
default: 2
|
||||
description:
|
||||
Selects the drive strength for the specified pins, in mA.
|
||||
|
||||
bias-pull-down: true
|
||||
|
||||
bias-pull-up: true
|
||||
|
||||
bias-disable: true
|
||||
|
||||
output-high: true
|
||||
|
||||
output-low: true
|
||||
|
||||
required:
|
||||
- pins
|
||||
- function
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- '#interrupt-cells'
|
||||
- gpio-controller
|
||||
- '#gpio-cells'
|
||||
- gpio-ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
tlmm: pinctrl@f100000 {
|
||||
compatible = "qcom,sdx65-tlmm";
|
||||
reg = <0x03000000 0xdc2000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&tlmm 0 0 109>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
gpio-wo-subnode-state {
|
||||
pins = "gpio1";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
uart-w-subnodes-state {
|
||||
rx {
|
||||
pins = "gpio4";
|
||||
function = "blsp_uart1";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
tx {
|
||||
pins = "gpio5";
|
||||
function = "blsp_uart1";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -121,6 +121,9 @@ patternProperties:
|
|||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@ description: |
|
|||
in the SM6125 platform.
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
properties:
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@ description: |
|
|||
in the SM6350 platform.
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
properties:
|
||||
|
|
|
|||
|
|
@ -115,6 +115,9 @@ patternProperties:
|
|||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@ description: |
|
|||
in the SM8350 platform.
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
properties:
|
||||
|
|
|
|||
|
|
@ -0,0 +1,143 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. SM8450 TLMM block
|
||||
|
||||
maintainers:
|
||||
- Vinod Koul <vkoul@kernel.org>
|
||||
|
||||
description: |
|
||||
This binding describes the Top Level Mode Multiplexer (TLMM) block found
|
||||
in the SM8450 platform.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8450-tlmm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupt-controller: true
|
||||
'#interrupt-cells': true
|
||||
gpio-controller: true
|
||||
gpio-reserved-ranges: true
|
||||
'#gpio-cells': true
|
||||
gpio-ranges: true
|
||||
wakeup-parent: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
patternProperties:
|
||||
'-state$':
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-sm8450-tlmm-state"
|
||||
- patternProperties:
|
||||
".*":
|
||||
$ref: "#/$defs/qcom-sm8450-tlmm-state"
|
||||
|
||||
$defs:
|
||||
qcom-sm8450-tlmm-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
|
||||
|
||||
properties:
|
||||
pins:
|
||||
description:
|
||||
List of gpio pins affected by the properties specified in this
|
||||
subnode.
|
||||
items:
|
||||
oneOf:
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
|
||||
- enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
|
||||
minItems: 1
|
||||
maxItems: 36
|
||||
|
||||
function:
|
||||
description:
|
||||
Specify the alternative function to be configured for the specified
|
||||
pins.
|
||||
enum: [ aon_cam, atest_char, atest_usb, audio_ref, cam_mclk, cci_async,
|
||||
cci_i2c, cci_timer, cmu_rng, coex_uart1, coex_uart2, cri_trng,
|
||||
cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
|
||||
ddr_pxi2, ddr_pxi3, dp_hot, gcc_gp1, gcc_gp2, gcc_gp3,
|
||||
gpio, ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0, mdp_vsync1,
|
||||
mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1, mi2s0_sck,
|
||||
mi2s0_ws, mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws,
|
||||
mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12,
|
||||
mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6,
|
||||
mss_grfc7, mss_grfc8, mss_grfc9, nav, pcie0_clkreqn,
|
||||
pcie1_clkreqn, phase_flag, pll_bist, pll_clk, pri_mi2s,
|
||||
prng_rosc, qdss_cti, qdss_gpio, qlink0_enable, qlink0_request,
|
||||
qlink0_wmss, qlink1_enable, qlink1_request, qlink1_wmss,
|
||||
qlink2_enable, qlink2_request, qlink2_wmss, qspi0, qspi1,
|
||||
qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10, qup11,
|
||||
qup12, qup13, qup14, qup15, qup16, qup17, qup18, qup19, qup2,
|
||||
qup20, qup21, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4,
|
||||
qup_l5, qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk,
|
||||
sdc4_cmd, sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2,
|
||||
tgu_ch3, tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3,
|
||||
tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data, uim0_present,
|
||||
uim0_reset, uim1_clk, uim1_data, uim1_present, uim1_reset,
|
||||
usb2phy_ac, usb_phy, vfr_0, vfr_1, vsense_trigger ]
|
||||
|
||||
bias-disable: true
|
||||
bias-pull-down: true
|
||||
bias-pull-up: true
|
||||
drive-strength: true
|
||||
input-enable: true
|
||||
output-high: true
|
||||
output-low: true
|
||||
|
||||
required:
|
||||
- pins
|
||||
- function
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
pinctrl@f100000 {
|
||||
compatible = "qcom,sm8450-tlmm";
|
||||
reg = <0x0f100000 0x300000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&tlmm 0 0 211>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
gpio-wo-subnode-state {
|
||||
pins = "gpio1";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
uart-w-subnodes-state {
|
||||
rx {
|
||||
pins = "gpio26";
|
||||
function = "qup7";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
tx {
|
||||
pins = "gpio27";
|
||||
function = "qup7";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -51,6 +51,9 @@ properties:
|
|||
should not be accessed by the OS. Please see the ../gpio/gpio.txt for more
|
||||
information.
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
|
|
|
|||
|
|
@ -44,6 +44,9 @@ patternProperties:
|
|||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
|
|
|
|||
|
|
@ -70,6 +70,9 @@ properties:
|
|||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -31,6 +31,9 @@ properties:
|
|||
reg:
|
||||
maxItems: 1
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -72,6 +72,9 @@ patternProperties:
|
|||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -73,6 +73,8 @@ additionalProperties:
|
|||
pins: true
|
||||
drive-strength:
|
||||
enum: [ 2, 4, 8, 12 ]
|
||||
output-impedance-ohms:
|
||||
enum: [ 33, 50, 66, 100 ]
|
||||
power-source:
|
||||
enum: [ 1800, 2500, 3300 ]
|
||||
slew-rate: true
|
||||
|
|
@ -90,6 +92,9 @@ additionalProperties:
|
|||
additionalProperties:
|
||||
$ref: "#/additionalProperties/anyOf/0"
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -31,6 +31,9 @@ properties:
|
|||
description:
|
||||
The bus clock, sometimes described as pclk, for register accesses.
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -67,6 +67,9 @@ properties:
|
|||
|
||||
ranges: true
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- rockchip,grf
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@ Required Properties:
|
|||
- "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
|
||||
- "samsung,exynos5433-pinctrl": for Exynos5433 compatible pin-controller.
|
||||
- "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller.
|
||||
- "samsung,exynos7885-pinctrl": for Exynos7885 compatible pin-controller.
|
||||
- "samsung,exynos850-pinctrl": for Exynos850 compatible pin-controller.
|
||||
- "samsung,exynosautov9-pinctrl": for ExynosAutov9 compatible pin-controller.
|
||||
|
||||
|
|
|
|||
|
|
@ -10,9 +10,6 @@ maintainers:
|
|||
- Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "pinctrl"
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- socionext,uniphier-ld4-pinctrl
|
||||
|
|
@ -26,11 +23,48 @@ properties:
|
|||
- socionext,uniphier-pxs3-pinctrl
|
||||
- socionext,uniphier-nx1-pinctrl
|
||||
|
||||
additionalProperties:
|
||||
type: object
|
||||
|
||||
allOf:
|
||||
- $ref: pincfg-node.yaml#
|
||||
- $ref: pinmux-node.yaml#
|
||||
|
||||
properties:
|
||||
phandle: true
|
||||
function: true
|
||||
groups: true
|
||||
pins: true
|
||||
bias-pull-up: true
|
||||
bias-pull-down: true
|
||||
bias-pull-pin-default: true
|
||||
drive-strength: true
|
||||
|
||||
additionalProperties:
|
||||
type: object
|
||||
|
||||
allOf:
|
||||
- $ref: pincfg-node.yaml#
|
||||
- $ref: pinmux-node.yaml#
|
||||
|
||||
properties:
|
||||
phandle: true
|
||||
function: true
|
||||
groups: true
|
||||
pins: true
|
||||
bias-pull-up: true
|
||||
bias-pull-down: true
|
||||
bias-pull-pin-default: true
|
||||
drive-strength: true
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
// The UniPhier pinctrl should be a subnode of a "syscon" compatible node.
|
||||
|
|
|
|||
|
|
@ -183,6 +183,9 @@ patternProperties:
|
|||
required:
|
||||
- pinmux
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#address-cells'
|
||||
|
|
|
|||
|
|
@ -20,6 +20,9 @@ properties:
|
|||
reg:
|
||||
maxItems: 1
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
@ -80,7 +83,7 @@ examples:
|
|||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pmux: pmux@24190000 {
|
||||
pmux: pinmux@24190000 {
|
||||
compatible = "toshiba,tmpv7708-pinctrl";
|
||||
reg = <0 0x24190000 0 0x10000>;
|
||||
|
||||
|
|
|
|||
|
|
@ -167,6 +167,9 @@ patternProperties:
|
|||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -290,6 +290,9 @@ patternProperties:
|
|||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: pinctrl.yaml#
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
|
|
|
|||
|
|
@ -15241,6 +15241,11 @@ L: linux-omap@vger.kernel.org
|
|||
S: Maintained
|
||||
F: drivers/pinctrl/pinctrl-single.c
|
||||
|
||||
PIN CONTROLLER - THUNDERBAY
|
||||
M: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
|
||||
S: Supported
|
||||
F: drivers/pinctrl/pinctrl-thunderbay.c
|
||||
|
||||
PKTCDVD DRIVER
|
||||
M: linux-block@vger.kernel.org
|
||||
S: Orphan
|
||||
|
|
|
|||
|
|
@ -491,27 +491,6 @@ static void gpio_mockup_unregister_pdevs(void)
|
|||
}
|
||||
}
|
||||
|
||||
static __init char **gpio_mockup_make_line_names(const char *label,
|
||||
unsigned int num_lines)
|
||||
{
|
||||
unsigned int i;
|
||||
char **names;
|
||||
|
||||
names = kcalloc(num_lines + 1, sizeof(char *), GFP_KERNEL);
|
||||
if (!names)
|
||||
return NULL;
|
||||
|
||||
for (i = 0; i < num_lines; i++) {
|
||||
names[i] = kasprintf(GFP_KERNEL, "%s-%u", label, i);
|
||||
if (!names[i]) {
|
||||
kfree_strarray(names, i);
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
return names;
|
||||
}
|
||||
|
||||
static int __init gpio_mockup_register_chip(int idx)
|
||||
{
|
||||
struct property_entry properties[GPIO_MOCKUP_MAX_PROP];
|
||||
|
|
@ -538,7 +517,7 @@ static int __init gpio_mockup_register_chip(int idx)
|
|||
properties[prop++] = PROPERTY_ENTRY_U16("nr-gpios", ngpio);
|
||||
|
||||
if (gpio_mockup_named_lines) {
|
||||
line_names = gpio_mockup_make_line_names(chip_label, ngpio);
|
||||
line_names = kasprintf_strarray(GFP_KERNEL, chip_label, ngpio);
|
||||
if (!line_names)
|
||||
return -ENOMEM;
|
||||
|
||||
|
|
|
|||
|
|
@ -31,6 +31,24 @@ config DEBUG_PINCTRL
|
|||
help
|
||||
Say Y here to add some extra checks and diagnostics to PINCTRL calls.
|
||||
|
||||
config PINCTRL_AMD
|
||||
tristate "AMD GPIO pin control"
|
||||
depends on HAS_IOMEM
|
||||
depends on ACPI || COMPILE_TEST
|
||||
select GPIOLIB
|
||||
select GPIOLIB_IRQCHIP
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
select GENERIC_PINCONF
|
||||
help
|
||||
The driver for memory mapped GPIO functionality on AMD platforms
|
||||
(x86 or arm). Most of the pins are usually muxed to some other
|
||||
functionality by firmware, so only a small amount is available
|
||||
for GPIO use.
|
||||
|
||||
Requires ACPI/FDT device enumeration code to set up a platform
|
||||
device.
|
||||
|
||||
config PINCTRL_APPLE_GPIO
|
||||
tristate "Apple SoC GPIO pin controller driver"
|
||||
depends on ARCH_APPLE
|
||||
|
|
@ -69,20 +87,6 @@ config PINCTRL_AS3722
|
|||
open drain configuration for the GPIO pins of AS3722 devices. It also
|
||||
supports the GPIO functionality through gpiolib.
|
||||
|
||||
config PINCTRL_AXP209
|
||||
tristate "X-Powers AXP209 PMIC pinctrl and GPIO Support"
|
||||
depends on MFD_AXP20X
|
||||
depends on OF
|
||||
select PINMUX
|
||||
select GENERIC_PINCONF
|
||||
select GPIOLIB
|
||||
help
|
||||
AXP PMICs provides multiple GPIOs that can be muxed for different
|
||||
functions. This driver bundles a pinctrl driver to select the function
|
||||
muxing and a GPIO driver to handle the GPIO when the GPIO function is
|
||||
selected.
|
||||
Say yes to enable pinctrl and GPIO support for the AXP209 PMIC
|
||||
|
||||
config PINCTRL_AT91
|
||||
bool "AT91 pinctrl driver"
|
||||
depends on OF
|
||||
|
|
@ -109,23 +113,19 @@ config PINCTRL_AT91PIO4
|
|||
Say Y here to enable the at91 pinctrl/gpio driver for Atmel PIO4
|
||||
controller available on sama5d2 SoC.
|
||||
|
||||
config PINCTRL_AMD
|
||||
tristate "AMD GPIO pin control"
|
||||
depends on HAS_IOMEM
|
||||
depends on ACPI || COMPILE_TEST
|
||||
select GPIOLIB
|
||||
select GPIOLIB_IRQCHIP
|
||||
config PINCTRL_AXP209
|
||||
tristate "X-Powers AXP209 PMIC pinctrl and GPIO Support"
|
||||
depends on MFD_AXP20X
|
||||
depends on OF
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
select GENERIC_PINCONF
|
||||
select GPIOLIB
|
||||
help
|
||||
driver for memory mapped GPIO functionality on AMD platforms
|
||||
(x86 or arm).Most pins are usually muxed to some other
|
||||
functionality by firmware,so only a small amount is available
|
||||
for gpio use.
|
||||
|
||||
Requires ACPI/FDT device enumeration code to set up a platform
|
||||
device.
|
||||
AXP PMICs provides multiple GPIOs that can be muxed for different
|
||||
functions. This driver bundles a pinctrl driver to select the function
|
||||
muxing and a GPIO driver to handle the GPIO when the GPIO function is
|
||||
selected.
|
||||
Say Y to enable pinctrl and GPIO support for the AXP209 PMIC.
|
||||
|
||||
config PINCTRL_BM1880
|
||||
bool "Bitmain BM1880 Pinctrl driver"
|
||||
|
|
@ -136,13 +136,13 @@ config PINCTRL_BM1880
|
|||
Pinctrl driver for Bitmain BM1880 SoC.
|
||||
|
||||
config PINCTRL_DA850_PUPD
|
||||
tristate "TI DA850/OMAP-L138/AM18XX pullup/pulldown groups"
|
||||
tristate "TI DA850/OMAP-L138/AM18XX pull-up and pull-down groups"
|
||||
depends on OF && (ARCH_DAVINCI_DA850 || COMPILE_TEST)
|
||||
select PINCONF
|
||||
select GENERIC_PINCONF
|
||||
help
|
||||
Driver for TI DA850/OMAP-L138/AM18XX pinconf. Used to control
|
||||
pullup/pulldown pin groups.
|
||||
pull-up and pull-down pin groups.
|
||||
|
||||
config PINCTRL_DA9062
|
||||
tristate "Dialog Semiconductor DA9062 PMIC pinctrl and GPIO Support"
|
||||
|
|
@ -154,7 +154,7 @@ config PINCTRL_DA9062
|
|||
function muxing and a GPIO driver to handle the GPIO when the GPIO
|
||||
function is selected.
|
||||
|
||||
Say yes to enable pinctrl and GPIO support for the DA9062 PMIC.
|
||||
Say Y to enable pinctrl and GPIO support for the DA9062 PMIC.
|
||||
|
||||
config PINCTRL_DIGICOLOR
|
||||
bool
|
||||
|
|
@ -162,12 +162,93 @@ config PINCTRL_DIGICOLOR
|
|||
select PINMUX
|
||||
select GENERIC_PINCONF
|
||||
|
||||
config PINCTRL_EQUILIBRIUM
|
||||
tristate "Generic pinctrl and GPIO driver for Intel Lightning Mountain SoC"
|
||||
depends on OF && HAS_IOMEM
|
||||
depends on X86 || COMPILE_TEST
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
select GPIOLIB
|
||||
select GPIO_GENERIC
|
||||
select GPIOLIB_IRQCHIP
|
||||
select GENERIC_PINCONF
|
||||
select GENERIC_PINCTRL_GROUPS
|
||||
select GENERIC_PINMUX_FUNCTIONS
|
||||
help
|
||||
Equilibrium driver is a pinctrl and GPIO driver for Intel Lightning
|
||||
Mountain network processor SoC that supports both the GPIO and pin
|
||||
control frameworks. It provides interfaces to setup pin muxing, assign
|
||||
desired pin functions, configure GPIO attributes for LGM SoC pins.
|
||||
Pin muxing and pin config settings are retrieved from device tree.
|
||||
|
||||
config PINCTRL_GEMINI
|
||||
bool
|
||||
depends on ARCH_GEMINI
|
||||
default ARCH_GEMINI
|
||||
select PINMUX
|
||||
select GENERIC_PINCONF
|
||||
select MFD_SYSCON
|
||||
|
||||
config PINCTRL_INGENIC
|
||||
bool "Pinctrl driver for the Ingenic JZ47xx SoCs"
|
||||
default MACH_INGENIC
|
||||
depends on OF
|
||||
depends on MIPS || COMPILE_TEST
|
||||
select GENERIC_PINCONF
|
||||
select GENERIC_PINCTRL_GROUPS
|
||||
select GENERIC_PINMUX_FUNCTIONS
|
||||
select GPIOLIB
|
||||
select GPIOLIB_IRQCHIP
|
||||
select REGMAP_MMIO
|
||||
|
||||
config PINCTRL_K210
|
||||
bool "Pinctrl driver for the Canaan Kendryte K210 SoC"
|
||||
depends on RISCV && SOC_CANAAN && OF
|
||||
select GENERIC_PINMUX_FUNCTIONS
|
||||
select GENERIC_PINCONF
|
||||
select GPIOLIB
|
||||
select OF_GPIO
|
||||
select REGMAP_MMIO
|
||||
default SOC_CANAAN
|
||||
help
|
||||
Add support for the Canaan Kendryte K210 RISC-V SOC Field
|
||||
Programmable IO Array (FPIOA) controller.
|
||||
|
||||
config PINCTRL_KEEMBAY
|
||||
tristate "Pinctrl driver for Intel Keem Bay SoC"
|
||||
depends on ARCH_KEEMBAY || (ARM64 && COMPILE_TEST)
|
||||
depends on HAS_IOMEM
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
select GENERIC_PINCONF
|
||||
select GENERIC_PINCTRL_GROUPS
|
||||
select GENERIC_PINMUX_FUNCTIONS
|
||||
select GPIOLIB
|
||||
select GPIOLIB_IRQCHIP
|
||||
select GPIO_GENERIC
|
||||
help
|
||||
This selects pin control driver for the Intel Keem Bay SoC.
|
||||
It provides pin config functions such as pull-up, pull-down,
|
||||
interrupt, drive strength, sec lock, Schmitt trigger, slew
|
||||
rate control and direction control. This module will be
|
||||
called as pinctrl-keembay.
|
||||
|
||||
config PINCTRL_LANTIQ
|
||||
bool
|
||||
depends on LANTIQ
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
|
||||
config PINCTRL_FALCON
|
||||
bool
|
||||
depends on SOC_FALCON
|
||||
depends on PINCTRL_LANTIQ
|
||||
|
||||
config PINCTRL_XWAY
|
||||
bool
|
||||
depends on SOC_TYPE_XWAY
|
||||
depends on PINCTRL_LANTIQ
|
||||
|
||||
config PINCTRL_LPC18XX
|
||||
bool "NXP LPC18XX/43XX SCU pinctrl driver"
|
||||
depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
|
||||
|
|
@ -177,18 +258,16 @@ config PINCTRL_LPC18XX
|
|||
help
|
||||
Pinctrl driver for NXP LPC18xx/43xx System Control Unit (SCU).
|
||||
|
||||
config PINCTRL_FALCON
|
||||
bool
|
||||
depends on SOC_FALCON
|
||||
depends on PINCTRL_LANTIQ
|
||||
|
||||
config PINCTRL_GEMINI
|
||||
bool
|
||||
depends on ARCH_GEMINI
|
||||
default ARCH_GEMINI
|
||||
config PINCTRL_MAX77620
|
||||
tristate "MAX77620/MAX20024 Pincontrol support"
|
||||
depends on MFD_MAX77620 && OF
|
||||
select PINMUX
|
||||
select GENERIC_PINCONF
|
||||
select MFD_SYSCON
|
||||
help
|
||||
Say Y here to enable Pin control support for Maxim MAX77620 PMIC.
|
||||
This PMIC has 8 GPIO pins that work as GPIO as well as special
|
||||
function in alternate mode. This driver also configure push-pull,
|
||||
open drain, FPS slots etc.
|
||||
|
||||
config PINCTRL_MCP23S08_I2C
|
||||
tristate
|
||||
|
|
@ -212,6 +291,37 @@ config PINCTRL_MCP23S08
|
|||
This provides a GPIO interface supporting inputs and outputs and a
|
||||
corresponding interrupt-controller.
|
||||
|
||||
config PINCTRL_MICROCHIP_SGPIO
|
||||
bool "Pinctrl driver for Microsemi/Microchip Serial GPIO"
|
||||
depends on OF
|
||||
depends on HAS_IOMEM
|
||||
select GPIOLIB
|
||||
select GPIOLIB_IRQCHIP
|
||||
select GENERIC_PINCONF
|
||||
select GENERIC_PINCTRL_GROUPS
|
||||
select GENERIC_PINMUX_FUNCTIONS
|
||||
select OF_GPIO
|
||||
help
|
||||
Support for the serial GPIO interface used on Microsemi and
|
||||
Microchip SoCs. By using a serial interface, the SIO
|
||||
controller significantly extends the number of available
|
||||
GPIOs with a minimum number of additional pins on the
|
||||
device. The primary purpose of the SIO controller is to
|
||||
connect control signals from SFP modules and to act as an
|
||||
LED controller.
|
||||
|
||||
config PINCTRL_OCELOT
|
||||
bool "Pinctrl driver for the Microsemi Ocelot and Jaguar2 SoCs"
|
||||
depends on OF
|
||||
depends on HAS_IOMEM
|
||||
select GPIOLIB
|
||||
select GPIOLIB_IRQCHIP
|
||||
select GENERIC_PINCONF
|
||||
select GENERIC_PINCTRL_GROUPS
|
||||
select GENERIC_PINMUX_FUNCTIONS
|
||||
select OF_GPIO
|
||||
select REGMAP_MMIO
|
||||
|
||||
config PINCTRL_OXNAS
|
||||
bool
|
||||
depends on OF
|
||||
|
|
@ -223,6 +333,54 @@ config PINCTRL_OXNAS
|
|||
select GPIOLIB_IRQCHIP
|
||||
select MFD_SYSCON
|
||||
|
||||
config PINCTRL_PALMAS
|
||||
tristate "Pinctrl driver for the PALMAS Series MFD devices"
|
||||
depends on OF && MFD_PALMAS
|
||||
select PINMUX
|
||||
select GENERIC_PINCONF
|
||||
help
|
||||
Palmas device supports the configuration of pins for different
|
||||
functionality. This driver supports the pinmux, push-pull and
|
||||
open drain configuration for the Palmas series devices like
|
||||
TPS65913, TPS80036 etc.
|
||||
|
||||
config PINCTRL_PIC32
|
||||
bool "Microchip PIC32 pin controller driver"
|
||||
depends on OF
|
||||
depends on MACH_PIC32
|
||||
select PINMUX
|
||||
select GENERIC_PINCONF
|
||||
select GPIOLIB_IRQCHIP
|
||||
select OF_GPIO
|
||||
help
|
||||
This is the pin controller and gpio driver for Microchip PIC32
|
||||
microcontrollers. This option is selected automatically when specific
|
||||
machine and arch are selected to build.
|
||||
|
||||
config PINCTRL_PIC32MZDA
|
||||
def_bool y if PIC32MZDA
|
||||
select PINCTRL_PIC32
|
||||
|
||||
config PINCTRL_PISTACHIO
|
||||
bool "IMG Pistachio SoC pinctrl driver"
|
||||
depends on OF && (MIPS || COMPILE_TEST)
|
||||
depends on GPIOLIB
|
||||
select PINMUX
|
||||
select GENERIC_PINCONF
|
||||
select GPIOLIB_IRQCHIP
|
||||
select OF_GPIO
|
||||
help
|
||||
This support pinctrl and GPIO driver for IMG Pistachio SoC.
|
||||
|
||||
config PINCTRL_RK805
|
||||
tristate "Pinctrl and GPIO driver for RK805 PMIC"
|
||||
depends on MFD_RK808
|
||||
select GPIOLIB
|
||||
select PINMUX
|
||||
select GENERIC_PINCONF
|
||||
help
|
||||
This selects the pinctrl driver for RK805.
|
||||
|
||||
config PINCTRL_ROCKCHIP
|
||||
tristate "Rockchip gpio and pinctrl driver"
|
||||
depends on ARCH_ROCKCHIP || COMPILE_TEST
|
||||
|
|
@ -235,7 +393,7 @@ config PINCTRL_ROCKCHIP
|
|||
select OF_GPIO
|
||||
default ARCH_ROCKCHIP
|
||||
help
|
||||
This support pinctrl and gpio driver for Rockchip SoCs.
|
||||
This support pinctrl and GPIO driver for Rockchip SoCs.
|
||||
|
||||
config PINCTRL_SINGLE
|
||||
tristate "One-register-per-pin type device tree based pinctrl driver"
|
||||
|
|
@ -247,33 +405,6 @@ config PINCTRL_SINGLE
|
|||
help
|
||||
This selects the device tree based generic pinctrl driver.
|
||||
|
||||
config PINCTRL_SX150X
|
||||
bool "Semtech SX150x I2C GPIO expander pinctrl driver"
|
||||
depends on I2C=y
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
select GENERIC_PINCONF
|
||||
select GPIOLIB
|
||||
select GPIOLIB_IRQCHIP
|
||||
select REGMAP
|
||||
help
|
||||
Say yes here to provide support for Semtech SX150x-series I2C
|
||||
GPIO expanders as pinctrl module.
|
||||
Compatible models include:
|
||||
- 8 bits: sx1508q, sx1502q
|
||||
- 16 bits: sx1509q, sx1506q
|
||||
|
||||
config PINCTRL_PISTACHIO
|
||||
bool "IMG Pistachio SoC pinctrl driver"
|
||||
depends on OF && (MIPS || COMPILE_TEST)
|
||||
depends on GPIOLIB
|
||||
select PINMUX
|
||||
select GENERIC_PINCONF
|
||||
select GPIOLIB_IRQCHIP
|
||||
select OF_GPIO
|
||||
help
|
||||
This support pinctrl and gpio driver for IMG Pistachio SoC.
|
||||
|
||||
config PINCTRL_ST
|
||||
bool
|
||||
depends on OF
|
||||
|
|
@ -312,44 +443,45 @@ config PINCTRL_STMFX
|
|||
and configuring push-pull, open-drain, and can also be used as
|
||||
interrupt-controller.
|
||||
|
||||
config PINCTRL_MAX77620
|
||||
tristate "MAX77620/MAX20024 Pincontrol support"
|
||||
depends on MFD_MAX77620 && OF
|
||||
select PINMUX
|
||||
select GENERIC_PINCONF
|
||||
help
|
||||
Say Yes here to enable Pin control support for Maxim PMIC MAX77620.
|
||||
This PMIC has 8 GPIO pins that work as GPIO as well as special
|
||||
function in alternate mode. This driver also configure push-pull,
|
||||
open drain, FPS slots etc.
|
||||
|
||||
config PINCTRL_PALMAS
|
||||
tristate "Pinctrl driver for the PALMAS Series MFD devices"
|
||||
depends on OF && MFD_PALMAS
|
||||
select PINMUX
|
||||
select GENERIC_PINCONF
|
||||
help
|
||||
Palmas device supports the configuration of pins for different
|
||||
functionality. This driver supports the pinmux, push-pull and
|
||||
open drain configuration for the Palmas series devices like
|
||||
TPS65913, TPS80036 etc.
|
||||
|
||||
config PINCTRL_PIC32
|
||||
bool "Microchip PIC32 pin controller driver"
|
||||
depends on OF
|
||||
depends on MACH_PIC32
|
||||
config PINCTRL_SX150X
|
||||
bool "Semtech SX150x I2C GPIO expander pinctrl driver"
|
||||
depends on I2C=y
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
select GENERIC_PINCONF
|
||||
select GPIOLIB
|
||||
select GPIOLIB_IRQCHIP
|
||||
select OF_GPIO
|
||||
select REGMAP
|
||||
help
|
||||
This is the pin controller and gpio driver for Microchip PIC32
|
||||
microcontrollers. This option is selected automatically when specific
|
||||
machine and arch are selected to build.
|
||||
Say Y here to provide support for Semtech SX150x-series I2C
|
||||
GPIO expanders as pinctrl module.
|
||||
Compatible models include:
|
||||
- 8 bits: sx1508q, sx1502q
|
||||
- 16 bits: sx1509q, sx1506q
|
||||
|
||||
config PINCTRL_PIC32MZDA
|
||||
def_bool y if PIC32MZDA
|
||||
select PINCTRL_PIC32
|
||||
config PINCTRL_TB10X
|
||||
bool
|
||||
depends on OF && ARC_PLAT_TB10X
|
||||
select GPIOLIB
|
||||
|
||||
config PINCTRL_THUNDERBAY
|
||||
tristate "Generic pinctrl and GPIO driver for Intel Thunder Bay SoC"
|
||||
depends on ARCH_THUNDERBAY || (ARM64 && COMPILE_TEST)
|
||||
depends on HAS_IOMEM
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
select GENERIC_PINCONF
|
||||
select GENERIC_PINCTRL_GROUPS
|
||||
select GENERIC_PINMUX_FUNCTIONS
|
||||
select GPIOLIB
|
||||
select GPIOLIB_IRQCHIP
|
||||
select GPIO_GENERIC
|
||||
help
|
||||
This selects pin control driver for the Intel Thunder Bay SoC.
|
||||
It provides pin config functions such as pull-up, pull-down,
|
||||
interrupt, drive strength, sec lock, Schmitt trigger, slew
|
||||
rate control and direction control. This module will be
|
||||
called as pinctrl-thunderbay.
|
||||
|
||||
config PINCTRL_ZYNQ
|
||||
bool "Pinctrl driver for Xilinx Zynq"
|
||||
|
|
@ -375,96 +507,15 @@ config PINCTRL_ZYNQMP
|
|||
This driver can also be built as a module. If so, the module
|
||||
will be called pinctrl-zynqmp.
|
||||
|
||||
config PINCTRL_INGENIC
|
||||
bool "Pinctrl driver for the Ingenic JZ47xx SoCs"
|
||||
default MACH_INGENIC
|
||||
depends on OF
|
||||
depends on MIPS || COMPILE_TEST
|
||||
select GENERIC_PINCONF
|
||||
select GENERIC_PINCTRL_GROUPS
|
||||
select GENERIC_PINMUX_FUNCTIONS
|
||||
select GPIOLIB
|
||||
select GPIOLIB_IRQCHIP
|
||||
select REGMAP_MMIO
|
||||
|
||||
config PINCTRL_RK805
|
||||
tristate "Pinctrl and GPIO driver for RK805 PMIC"
|
||||
depends on MFD_RK808
|
||||
select GPIOLIB
|
||||
select PINMUX
|
||||
select GENERIC_PINCONF
|
||||
help
|
||||
This selects the pinctrl driver for RK805.
|
||||
|
||||
config PINCTRL_OCELOT
|
||||
bool "Pinctrl driver for the Microsemi Ocelot and Jaguar2 SoCs"
|
||||
depends on OF
|
||||
depends on HAS_IOMEM
|
||||
select GPIOLIB
|
||||
select GPIOLIB_IRQCHIP
|
||||
select GENERIC_PINCONF
|
||||
select GENERIC_PINCTRL_GROUPS
|
||||
select GENERIC_PINMUX_FUNCTIONS
|
||||
select OF_GPIO
|
||||
select REGMAP_MMIO
|
||||
|
||||
config PINCTRL_MICROCHIP_SGPIO
|
||||
bool "Pinctrl driver for Microsemi/Microchip Serial GPIO"
|
||||
depends on OF
|
||||
depends on HAS_IOMEM
|
||||
select GPIOLIB
|
||||
select GPIOLIB_IRQCHIP
|
||||
select GENERIC_PINCONF
|
||||
select GENERIC_PINCTRL_GROUPS
|
||||
select GENERIC_PINMUX_FUNCTIONS
|
||||
select OF_GPIO
|
||||
help
|
||||
Support for the serial GPIO interface used on Microsemi and
|
||||
Microchip SoC's. By using a serial interface, the SIO
|
||||
controller significantly extends the number of available
|
||||
GPIOs with a minimum number of additional pins on the
|
||||
device. The primary purpose of the SIO controller is to
|
||||
connect control signals from SFP modules and to act as an
|
||||
LED controller.
|
||||
|
||||
config PINCTRL_K210
|
||||
bool "Pinctrl driver for the Canaan Kendryte K210 SoC"
|
||||
depends on RISCV && SOC_CANAAN && OF
|
||||
select GENERIC_PINMUX_FUNCTIONS
|
||||
select GENERIC_PINCONF
|
||||
select GPIOLIB
|
||||
select OF_GPIO
|
||||
select REGMAP_MMIO
|
||||
default SOC_CANAAN
|
||||
help
|
||||
Add support for the Canaan Kendryte K210 RISC-V SOC Field
|
||||
Programmable IO Array (FPIOA) controller.
|
||||
|
||||
config PINCTRL_KEEMBAY
|
||||
tristate "Pinctrl driver for Intel Keem Bay SoC"
|
||||
depends on ARCH_KEEMBAY || (ARM64 && COMPILE_TEST)
|
||||
depends on HAS_IOMEM
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
select GENERIC_PINCONF
|
||||
select GENERIC_PINCTRL_GROUPS
|
||||
select GENERIC_PINMUX_FUNCTIONS
|
||||
select GPIOLIB
|
||||
select GPIOLIB_IRQCHIP
|
||||
select GPIO_GENERIC
|
||||
help
|
||||
This selects pin control driver for the Intel Keembay SoC.
|
||||
It provides pin config functions such as pullup, pulldown,
|
||||
interrupt, drive strength, sec lock, schmitt trigger, slew
|
||||
rate control and direction control. This module will be
|
||||
called as pinctrl-keembay.
|
||||
|
||||
source "drivers/pinctrl/actions/Kconfig"
|
||||
source "drivers/pinctrl/aspeed/Kconfig"
|
||||
source "drivers/pinctrl/bcm/Kconfig"
|
||||
source "drivers/pinctrl/berlin/Kconfig"
|
||||
source "drivers/pinctrl/cirrus/Kconfig"
|
||||
source "drivers/pinctrl/freescale/Kconfig"
|
||||
source "drivers/pinctrl/intel/Kconfig"
|
||||
source "drivers/pinctrl/mediatek/Kconfig"
|
||||
source "drivers/pinctrl/meson/Kconfig"
|
||||
source "drivers/pinctrl/mvebu/Kconfig"
|
||||
source "drivers/pinctrl/nomadik/Kconfig"
|
||||
source "drivers/pinctrl/nuvoton/Kconfig"
|
||||
|
|
@ -480,40 +531,7 @@ source "drivers/pinctrl/sunxi/Kconfig"
|
|||
source "drivers/pinctrl/tegra/Kconfig"
|
||||
source "drivers/pinctrl/ti/Kconfig"
|
||||
source "drivers/pinctrl/uniphier/Kconfig"
|
||||
source "drivers/pinctrl/vt8500/Kconfig"
|
||||
source "drivers/pinctrl/mediatek/Kconfig"
|
||||
source "drivers/pinctrl/meson/Kconfig"
|
||||
source "drivers/pinctrl/cirrus/Kconfig"
|
||||
source "drivers/pinctrl/visconti/Kconfig"
|
||||
|
||||
config PINCTRL_XWAY
|
||||
bool
|
||||
depends on SOC_TYPE_XWAY
|
||||
depends on PINCTRL_LANTIQ
|
||||
|
||||
config PINCTRL_TB10X
|
||||
bool
|
||||
depends on OF && ARC_PLAT_TB10X
|
||||
select GPIOLIB
|
||||
|
||||
config PINCTRL_EQUILIBRIUM
|
||||
tristate "Generic pinctrl and GPIO driver for Intel Lightning Mountain SoC"
|
||||
depends on OF && HAS_IOMEM
|
||||
depends on X86 || COMPILE_TEST
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
select GPIOLIB
|
||||
select GPIO_GENERIC
|
||||
select GPIOLIB_IRQCHIP
|
||||
select GENERIC_PINCONF
|
||||
select GENERIC_PINCTRL_GROUPS
|
||||
select GENERIC_PINMUX_FUNCTIONS
|
||||
|
||||
help
|
||||
Equilibrium pinctrl driver is a pinctrl & GPIO driver for Intel Lightning
|
||||
Mountain network processor SoC that supports both the linux GPIO and pin
|
||||
control frameworks. It provides interfaces to setup pinmux, assign desired
|
||||
pin functions, configure GPIO attributes for LGM SoC pins. Pinmux and
|
||||
pinconf settings are retrieved from device tree.
|
||||
source "drivers/pinctrl/vt8500/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -6,57 +6,60 @@ subdir-ccflags-$(CONFIG_DEBUG_PINCTRL) += -DDEBUG
|
|||
obj-y += core.o pinctrl-utils.o
|
||||
obj-$(CONFIG_PINMUX) += pinmux.o
|
||||
obj-$(CONFIG_PINCONF) += pinconf.o
|
||||
obj-$(CONFIG_OF) += devicetree.o
|
||||
obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o
|
||||
obj-$(CONFIG_OF) += devicetree.o
|
||||
|
||||
obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o
|
||||
obj-$(CONFIG_PINCTRL_APPLE_GPIO) += pinctrl-apple-gpio.o
|
||||
obj-$(CONFIG_PINCTRL_ARTPEC6) += pinctrl-artpec6.o
|
||||
obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o
|
||||
obj-$(CONFIG_PINCTRL_AXP209) += pinctrl-axp209.o
|
||||
obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
|
||||
obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o
|
||||
obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o
|
||||
obj-$(CONFIG_PINCTRL_AXP209) += pinctrl-axp209.o
|
||||
obj-$(CONFIG_PINCTRL_BM1880) += pinctrl-bm1880.o
|
||||
obj-$(CONFIG_PINCTRL_DA850_PUPD) += pinctrl-da850-pupd.o
|
||||
obj-$(CONFIG_PINCTRL_DA9062) += pinctrl-da9062.o
|
||||
obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o
|
||||
obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
|
||||
obj-$(CONFIG_PINCTRL_EQUILIBRIUM) += pinctrl-equilibrium.o
|
||||
obj-$(CONFIG_PINCTRL_GEMINI) += pinctrl-gemini.o
|
||||
obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o
|
||||
obj-$(CONFIG_PINCTRL_K210) += pinctrl-k210.o
|
||||
obj-$(CONFIG_PINCTRL_KEEMBAY) += pinctrl-keembay.o
|
||||
obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
|
||||
obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
|
||||
obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
|
||||
obj-$(CONFIG_PINCTRL_LPC18XX) += pinctrl-lpc18xx.o
|
||||
obj-$(CONFIG_PINCTRL_MAX77620) += pinctrl-max77620.o
|
||||
obj-$(CONFIG_PINCTRL_MCP23S08_I2C) += pinctrl-mcp23s08_i2c.o
|
||||
obj-$(CONFIG_PINCTRL_MCP23S08_SPI) += pinctrl-mcp23s08_spi.o
|
||||
obj-$(CONFIG_PINCTRL_MCP23S08) += pinctrl-mcp23s08.o
|
||||
obj-$(CONFIG_PINCTRL_MESON) += meson/
|
||||
obj-$(CONFIG_PINCTRL_MICROCHIP_SGPIO) += pinctrl-microchip-sgpio.o
|
||||
obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o
|
||||
obj-$(CONFIG_PINCTRL_OXNAS) += pinctrl-oxnas.o
|
||||
obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
|
||||
obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o
|
||||
obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
|
||||
obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o
|
||||
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
|
||||
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
|
||||
obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o
|
||||
obj-$(CONFIG_ARCH_TEGRA) += tegra/
|
||||
obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
|
||||
obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
|
||||
obj-$(CONFIG_PINCTRL_LPC18XX) += pinctrl-lpc18xx.o
|
||||
obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o
|
||||
obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
|
||||
obj-$(CONFIG_PINCTRL_STARFIVE) += pinctrl-starfive.o
|
||||
obj-$(CONFIG_PINCTRL_STMFX) += pinctrl-stmfx.o
|
||||
obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o
|
||||
obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
|
||||
obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o
|
||||
obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o
|
||||
obj-$(CONFIG_PINCTRL_THUNDERBAY) += pinctrl-thunderbay.o
|
||||
obj-$(CONFIG_PINCTRL_ZYNQMP) += pinctrl-zynqmp.o
|
||||
obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o
|
||||
obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o
|
||||
obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o
|
||||
obj-$(CONFIG_PINCTRL_MICROCHIP_SGPIO) += pinctrl-microchip-sgpio.o
|
||||
obj-$(CONFIG_PINCTRL_EQUILIBRIUM) += pinctrl-equilibrium.o
|
||||
obj-$(CONFIG_PINCTRL_K210) += pinctrl-k210.o
|
||||
obj-$(CONFIG_PINCTRL_KEEMBAY) += pinctrl-keembay.o
|
||||
obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o
|
||||
|
||||
obj-y += actions/
|
||||
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
|
||||
obj-y += bcm/
|
||||
obj-$(CONFIG_PINCTRL_BERLIN) += berlin/
|
||||
obj-y += cirrus/
|
||||
obj-y += freescale/
|
||||
obj-$(CONFIG_X86) += intel/
|
||||
obj-y += mediatek/
|
||||
obj-$(CONFIG_PINCTRL_MESON) += meson/
|
||||
obj-y += mvebu/
|
||||
obj-y += nomadik/
|
||||
obj-$(CONFIG_ARCH_NPCM7XX) += nuvoton/
|
||||
|
|
@ -69,9 +72,8 @@ obj-$(CONFIG_PINCTRL_SPEAR) += spear/
|
|||
obj-y += sprd/
|
||||
obj-$(CONFIG_PINCTRL_STM32) += stm32/
|
||||
obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/
|
||||
obj-$(CONFIG_ARCH_TEGRA) += tegra/
|
||||
obj-y += ti/
|
||||
obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
|
||||
obj-$(CONFIG_ARCH_VT8500) += vt8500/
|
||||
obj-y += mediatek/
|
||||
obj-y += cirrus/
|
||||
obj-$(CONFIG_PINCTRL_VISCONTI) += visconti/
|
||||
obj-$(CONFIG_ARCH_VT8500) += vt8500/
|
||||
|
|
|
|||
|
|
@ -874,7 +874,6 @@ static int owl_gpio_init(struct owl_pinctrl *pctrl)
|
|||
chip->label = dev_name(pctrl->dev);
|
||||
chip->parent = pctrl->dev;
|
||||
chip->owner = THIS_MODULE;
|
||||
chip->of_node = pctrl->dev->of_node;
|
||||
|
||||
pctrl->irq_chip.name = chip->of_node->name;
|
||||
pctrl->irq_chip.irq_ack = owl_gpio_irq_ack;
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
config PINCTRL_ASPEED
|
||||
bool
|
||||
depends on (ARCH_ASPEED || COMPILE_TEST) && OF
|
||||
depends on MFD_SYSCON
|
||||
select MFD_SYSCON
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
select GENERIC_PINCONF
|
||||
|
|
|
|||
|
|
@ -146,6 +146,8 @@ config PINCTRL_NS
|
|||
depends on OF && (ARCH_BCM_5301X || COMPILE_TEST)
|
||||
select PINMUX
|
||||
select GENERIC_PINCONF
|
||||
select GENERIC_PINCTRL_GROUPS
|
||||
select GENERIC_PINMUX_FUNCTIONS
|
||||
default ARCH_BCM_5301X
|
||||
help
|
||||
Say yes here to enable the Broadcom NS SoC pins driver.
|
||||
|
|
|
|||
|
|
@ -313,7 +313,10 @@ static inline void bcm2835_pinctrl_fsel_set(
|
|||
|
||||
static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
return pinctrl_gpio_direction_input(chip->base + offset);
|
||||
struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
|
||||
|
||||
bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
|
||||
|
|
@ -348,8 +351,11 @@ static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
|||
static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
|
||||
unsigned offset, int value)
|
||||
{
|
||||
bcm2835_gpio_set(chip, offset, value);
|
||||
return pinctrl_gpio_direction_output(chip->base + offset);
|
||||
struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
|
||||
|
||||
bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
|
||||
bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_OUT);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct gpio_chip bcm2835_gpio_chip = {
|
||||
|
|
@ -407,7 +413,7 @@ static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
|
|||
struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
|
||||
struct irq_chip *host_chip = irq_desc_get_chip(desc);
|
||||
int irq = irq_desc_get_irq(desc);
|
||||
int group;
|
||||
int group = 0;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < BCM2835_NUM_IRQS; i++) {
|
||||
|
|
@ -1222,7 +1228,6 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
|
|||
|
||||
pc->gpio_chip = *pdata->gpio_chip;
|
||||
pc->gpio_chip.parent = dev;
|
||||
pc->gpio_chip.of_node = np;
|
||||
|
||||
for (i = 0; i < BCM2835_NUM_BANKS; i++) {
|
||||
unsigned long events;
|
||||
|
|
|
|||
|
|
@ -836,7 +836,6 @@ static int iproc_gpio_probe(struct platform_device *pdev)
|
|||
chip->num_banks = (ngpios + NGPIOS_PER_BANK - 1) / NGPIOS_PER_BANK;
|
||||
gc->label = dev_name(dev);
|
||||
gc->parent = dev;
|
||||
gc->of_node = dev->of_node;
|
||||
gc->request = iproc_gpio_request;
|
||||
gc->free = iproc_gpio_free;
|
||||
gc->direction_input = iproc_gpio_direction_input;
|
||||
|
|
|
|||
|
|
@ -14,6 +14,9 @@
|
|||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include "../core.h"
|
||||
#include "../pinmux.h"
|
||||
|
||||
#define FLAG_BCM4708 BIT(1)
|
||||
#define FLAG_BCM4709 BIT(2)
|
||||
#define FLAG_BCM53012 BIT(3)
|
||||
|
|
@ -25,10 +28,6 @@ struct ns_pinctrl {
|
|||
void __iomem *base;
|
||||
|
||||
struct pinctrl_desc pctldesc;
|
||||
struct ns_pinctrl_group *groups;
|
||||
unsigned int num_groups;
|
||||
struct ns_pinctrl_function *functions;
|
||||
unsigned int num_functions;
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -65,22 +64,22 @@ static const struct pinctrl_pin_desc ns_pinctrl_pins[] = {
|
|||
|
||||
struct ns_pinctrl_group {
|
||||
const char *name;
|
||||
const unsigned int *pins;
|
||||
unsigned int *pins;
|
||||
const unsigned int num_pins;
|
||||
unsigned int chipsets;
|
||||
};
|
||||
|
||||
static const unsigned int spi_pins[] = { 0, 1, 2, 3 };
|
||||
static const unsigned int i2c_pins[] = { 4, 5 };
|
||||
static const unsigned int mdio_pins[] = { 6, 7 };
|
||||
static const unsigned int pwm0_pins[] = { 8 };
|
||||
static const unsigned int pwm1_pins[] = { 9 };
|
||||
static const unsigned int pwm2_pins[] = { 10 };
|
||||
static const unsigned int pwm3_pins[] = { 11 };
|
||||
static const unsigned int uart1_pins[] = { 12, 13, 14, 15 };
|
||||
static const unsigned int uart2_pins[] = { 16, 17 };
|
||||
static const unsigned int sdio_pwr_pins[] = { 22 };
|
||||
static const unsigned int sdio_1p8v_pins[] = { 23 };
|
||||
static unsigned int spi_pins[] = { 0, 1, 2, 3 };
|
||||
static unsigned int i2c_pins[] = { 4, 5 };
|
||||
static unsigned int mdio_pins[] = { 6, 7 };
|
||||
static unsigned int pwm0_pins[] = { 8 };
|
||||
static unsigned int pwm1_pins[] = { 9 };
|
||||
static unsigned int pwm2_pins[] = { 10 };
|
||||
static unsigned int pwm3_pins[] = { 11 };
|
||||
static unsigned int uart1_pins[] = { 12, 13, 14, 15 };
|
||||
static unsigned int uart2_pins[] = { 16, 17 };
|
||||
static unsigned int sdio_pwr_pins[] = { 22 };
|
||||
static unsigned int sdio_1p8v_pins[] = { 23 };
|
||||
|
||||
#define NS_GROUP(_name, _pins, _chipsets) \
|
||||
{ \
|
||||
|
|
@ -146,38 +145,10 @@ static const struct ns_pinctrl_function ns_pinctrl_functions[] = {
|
|||
* Groups code
|
||||
*/
|
||||
|
||||
static int ns_pinctrl_get_groups_count(struct pinctrl_dev *pctrl_dev)
|
||||
{
|
||||
struct ns_pinctrl *ns_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
|
||||
|
||||
return ns_pinctrl->num_groups;
|
||||
}
|
||||
|
||||
static const char *ns_pinctrl_get_group_name(struct pinctrl_dev *pctrl_dev,
|
||||
unsigned int selector)
|
||||
{
|
||||
struct ns_pinctrl *ns_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
|
||||
|
||||
return ns_pinctrl->groups[selector].name;
|
||||
}
|
||||
|
||||
static int ns_pinctrl_get_group_pins(struct pinctrl_dev *pctrl_dev,
|
||||
unsigned int selector,
|
||||
const unsigned int **pins,
|
||||
unsigned int *num_pins)
|
||||
{
|
||||
struct ns_pinctrl *ns_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
|
||||
|
||||
*pins = ns_pinctrl->groups[selector].pins;
|
||||
*num_pins = ns_pinctrl->groups[selector].num_pins;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct pinctrl_ops ns_pinctrl_ops = {
|
||||
.get_groups_count = ns_pinctrl_get_groups_count,
|
||||
.get_group_name = ns_pinctrl_get_group_name,
|
||||
.get_group_pins = ns_pinctrl_get_group_pins,
|
||||
.get_groups_count = pinctrl_generic_get_group_count,
|
||||
.get_group_name = pinctrl_generic_get_group_name,
|
||||
.get_group_pins = pinctrl_generic_get_group_pins,
|
||||
.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
|
||||
.dt_free_map = pinconf_generic_dt_free_map,
|
||||
};
|
||||
|
|
@ -186,48 +157,22 @@ static const struct pinctrl_ops ns_pinctrl_ops = {
|
|||
* Functions code
|
||||
*/
|
||||
|
||||
static int ns_pinctrl_get_functions_count(struct pinctrl_dev *pctrl_dev)
|
||||
{
|
||||
struct ns_pinctrl *ns_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
|
||||
|
||||
return ns_pinctrl->num_functions;
|
||||
}
|
||||
|
||||
static const char *ns_pinctrl_get_function_name(struct pinctrl_dev *pctrl_dev,
|
||||
unsigned int selector)
|
||||
{
|
||||
struct ns_pinctrl *ns_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
|
||||
|
||||
return ns_pinctrl->functions[selector].name;
|
||||
}
|
||||
|
||||
static int ns_pinctrl_get_function_groups(struct pinctrl_dev *pctrl_dev,
|
||||
unsigned int selector,
|
||||
const char * const **groups,
|
||||
unsigned * const num_groups)
|
||||
{
|
||||
struct ns_pinctrl *ns_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
|
||||
|
||||
*groups = ns_pinctrl->functions[selector].groups;
|
||||
*num_groups = ns_pinctrl->functions[selector].num_groups;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ns_pinctrl_set_mux(struct pinctrl_dev *pctrl_dev,
|
||||
unsigned int func_select,
|
||||
unsigned int grp_select)
|
||||
unsigned int group_selector)
|
||||
{
|
||||
struct ns_pinctrl *ns_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
|
||||
struct group_desc *group;
|
||||
u32 unset = 0;
|
||||
u32 tmp;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ns_pinctrl->groups[grp_select].num_pins; i++) {
|
||||
int pin_number = ns_pinctrl->groups[grp_select].pins[i];
|
||||
group = pinctrl_generic_get_group(pctrl_dev, group_selector);
|
||||
if (!group)
|
||||
return -EINVAL;
|
||||
|
||||
unset |= BIT(pin_number);
|
||||
}
|
||||
for (i = 0; i < group->num_pins; i++)
|
||||
unset |= BIT(group->pins[i]);
|
||||
|
||||
tmp = readl(ns_pinctrl->base);
|
||||
tmp &= ~unset;
|
||||
|
|
@ -237,9 +182,9 @@ static int ns_pinctrl_set_mux(struct pinctrl_dev *pctrl_dev,
|
|||
}
|
||||
|
||||
static const struct pinmux_ops ns_pinctrl_pmxops = {
|
||||
.get_functions_count = ns_pinctrl_get_functions_count,
|
||||
.get_function_name = ns_pinctrl_get_function_name,
|
||||
.get_function_groups = ns_pinctrl_get_function_groups,
|
||||
.get_functions_count = pinmux_generic_get_function_count,
|
||||
.get_function_name = pinmux_generic_get_function_name,
|
||||
.get_function_groups = pinmux_generic_get_function_groups,
|
||||
.set_mux = ns_pinctrl_set_mux,
|
||||
};
|
||||
|
||||
|
|
@ -267,8 +212,6 @@ static int ns_pinctrl_probe(struct platform_device *pdev)
|
|||
struct ns_pinctrl *ns_pinctrl;
|
||||
struct pinctrl_desc *pctldesc;
|
||||
struct pinctrl_pin_desc *pin;
|
||||
struct ns_pinctrl_group *group;
|
||||
struct ns_pinctrl_function *function;
|
||||
struct resource *res;
|
||||
int i;
|
||||
|
||||
|
|
@ -315,37 +258,6 @@ static int ns_pinctrl_probe(struct platform_device *pdev)
|
|||
}
|
||||
}
|
||||
|
||||
ns_pinctrl->groups = devm_kcalloc(dev, ARRAY_SIZE(ns_pinctrl_groups),
|
||||
sizeof(struct ns_pinctrl_group),
|
||||
GFP_KERNEL);
|
||||
if (!ns_pinctrl->groups)
|
||||
return -ENOMEM;
|
||||
for (i = 0, group = &ns_pinctrl->groups[0];
|
||||
i < ARRAY_SIZE(ns_pinctrl_groups); i++) {
|
||||
const struct ns_pinctrl_group *src = &ns_pinctrl_groups[i];
|
||||
|
||||
if (src->chipsets & ns_pinctrl->chipset_flag) {
|
||||
memcpy(group++, src, sizeof(*src));
|
||||
ns_pinctrl->num_groups++;
|
||||
}
|
||||
}
|
||||
|
||||
ns_pinctrl->functions = devm_kcalloc(dev,
|
||||
ARRAY_SIZE(ns_pinctrl_functions),
|
||||
sizeof(struct ns_pinctrl_function),
|
||||
GFP_KERNEL);
|
||||
if (!ns_pinctrl->functions)
|
||||
return -ENOMEM;
|
||||
for (i = 0, function = &ns_pinctrl->functions[0];
|
||||
i < ARRAY_SIZE(ns_pinctrl_functions); i++) {
|
||||
const struct ns_pinctrl_function *src = &ns_pinctrl_functions[i];
|
||||
|
||||
if (src->chipsets & ns_pinctrl->chipset_flag) {
|
||||
memcpy(function++, src, sizeof(*src));
|
||||
ns_pinctrl->num_functions++;
|
||||
}
|
||||
}
|
||||
|
||||
/* Register */
|
||||
|
||||
ns_pinctrl->pctldev = devm_pinctrl_register(dev, pctldesc, ns_pinctrl);
|
||||
|
|
@ -354,6 +266,27 @@ static int ns_pinctrl_probe(struct platform_device *pdev)
|
|||
return PTR_ERR(ns_pinctrl->pctldev);
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(ns_pinctrl_groups); i++) {
|
||||
const struct ns_pinctrl_group *group = &ns_pinctrl_groups[i];
|
||||
|
||||
if (!(group->chipsets & ns_pinctrl->chipset_flag))
|
||||
continue;
|
||||
|
||||
pinctrl_generic_add_group(ns_pinctrl->pctldev, group->name,
|
||||
group->pins, group->num_pins, NULL);
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(ns_pinctrl_functions); i++) {
|
||||
const struct ns_pinctrl_function *function = &ns_pinctrl_functions[i];
|
||||
|
||||
if (!(function->chipsets & ns_pinctrl->chipset_flag))
|
||||
continue;
|
||||
|
||||
pinmux_generic_add_function(ns_pinctrl->pctldev, function->name,
|
||||
function->groups,
|
||||
function->num_groups, NULL);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -648,7 +648,6 @@ static int nsp_gpio_probe(struct platform_device *pdev)
|
|||
gc->ngpio = val;
|
||||
gc->label = dev_name(dev);
|
||||
gc->parent = dev;
|
||||
gc->of_node = dev->of_node;
|
||||
gc->request = gpiochip_generic_request;
|
||||
gc->free = gpiochip_generic_free;
|
||||
gc->direction_input = nsp_gpio_direction_input;
|
||||
|
|
|
|||
|
|
@ -1161,9 +1161,6 @@ static int lochnagar_pin_probe(struct platform_device *pdev)
|
|||
priv->gpio_chip.can_sleep = true;
|
||||
priv->gpio_chip.parent = dev;
|
||||
priv->gpio_chip.base = -1;
|
||||
#ifdef CONFIG_OF_GPIO
|
||||
priv->gpio_chip.of_node = dev->of_node;
|
||||
#endif
|
||||
|
||||
switch (lochnagar->type) {
|
||||
case LOCHNAGAR1:
|
||||
|
|
|
|||
|
|
@ -8,8 +8,10 @@
|
|||
#include <linux/err.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/property.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include <linux/pinctrl/pinmux.h>
|
||||
|
|
@ -1004,13 +1006,14 @@ static int madera_pin_probe(struct platform_device *pdev)
|
|||
|
||||
dev_dbg(&pdev->dev, "%s\n", __func__);
|
||||
|
||||
device_set_node(&pdev->dev, dev_fwnode(pdev->dev.parent));
|
||||
|
||||
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->dev = &pdev->dev;
|
||||
priv->madera = madera;
|
||||
pdev->dev.of_node = madera->dev->of_node;
|
||||
|
||||
switch (madera->type) {
|
||||
case CS47L15:
|
||||
|
|
|
|||
|
|
@ -173,6 +173,13 @@ config PINCTRL_IMX8ULP
|
|||
help
|
||||
Say Y here to enable the imx8ulp pinctrl driver
|
||||
|
||||
config PINCTRL_IMXRT1050
|
||||
bool "IMXRT1050 pinctrl driver"
|
||||
depends on ARCH_MXC
|
||||
select PINCTRL_IMX
|
||||
help
|
||||
Say Y here to enable the imxrt1050 pinctrl driver
|
||||
|
||||
config PINCTRL_VF610
|
||||
bool "Freescale Vybrid VF610 pinctrl driver"
|
||||
depends on SOC_VF610
|
||||
|
|
|
|||
|
|
@ -30,3 +30,4 @@ obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
|
|||
obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
|
||||
obj-$(CONFIG_PINCTRL_IMX25) += pinctrl-imx25.o
|
||||
obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
|
||||
obj-$(CONFIG_PINCTRL_IMXRT1050) += pinctrl-imxrt1050.o
|
||||
|
|
|
|||
|
|
@ -648,7 +648,8 @@ static int imx_pinctrl_parse_functions(struct device_node *np,
|
|||
struct device_node *child;
|
||||
struct function_desc *func;
|
||||
struct group_desc *grp;
|
||||
u32 i = 0;
|
||||
const char **group_names;
|
||||
u32 i;
|
||||
|
||||
dev_dbg(pctl->dev, "parse function(%d): %pOFn\n", index, np);
|
||||
|
||||
|
|
@ -663,14 +664,18 @@ static int imx_pinctrl_parse_functions(struct device_node *np,
|
|||
dev_err(ipctl->dev, "no groups defined in %pOF\n", np);
|
||||
return -EINVAL;
|
||||
}
|
||||
func->group_names = devm_kcalloc(ipctl->dev, func->num_group_names,
|
||||
sizeof(char *), GFP_KERNEL);
|
||||
if (!func->group_names)
|
||||
|
||||
group_names = devm_kcalloc(ipctl->dev, func->num_group_names,
|
||||
sizeof(char *), GFP_KERNEL);
|
||||
if (!group_names)
|
||||
return -ENOMEM;
|
||||
i = 0;
|
||||
for_each_child_of_node(np, child)
|
||||
group_names[i++] = child->name;
|
||||
func->group_names = group_names;
|
||||
|
||||
i = 0;
|
||||
for_each_child_of_node(np, child) {
|
||||
func->group_names[i] = child->name;
|
||||
|
||||
grp = devm_kzalloc(ipctl->dev, sizeof(struct group_desc),
|
||||
GFP_KERNEL);
|
||||
if (!grp) {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,349 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2020
|
||||
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
|
||||
*/
|
||||
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "pinctrl-imx.h"
|
||||
|
||||
enum imxrt1050_pads {
|
||||
IMXRT1050_PAD_RESERVE0 = 0,
|
||||
IMXRT1050_PAD_RESERVE1 = 1,
|
||||
IMXRT1050_PAD_RESERVE2 = 2,
|
||||
IMXRT1050_PAD_RESERVE3 = 3,
|
||||
IMXRT1050_PAD_RESERVE4 = 4,
|
||||
IMXRT1050_PAD_RESERVE5 = 5,
|
||||
IMXRT1050_PAD_RESERVE6 = 6,
|
||||
IMXRT1050_PAD_RESERVE7 = 7,
|
||||
IMXRT1050_PAD_RESERVE8 = 8,
|
||||
IMXRT1050_PAD_RESERVE9 = 9,
|
||||
IMXRT1050_IOMUXC_GPIO1_IO00 = 10,
|
||||
IMXRT1050_IOMUXC_GPIO1_IO01 = 11,
|
||||
IMXRT1050_IOMUXC_GPIO1_IO02 = 12,
|
||||
IMXRT1050_IOMUXC_GPIO1_IO03 = 13,
|
||||
IMXRT1050_IOMUXC_GPIO1_IO04 = 14,
|
||||
IMXRT1050_IOMUXC_GPIO1_IO05 = 15,
|
||||
IMXRT1050_IOMUXC_GPIO1_IO06 = 16,
|
||||
IMXRT1050_IOMUXC_GPIO1_IO07 = 17,
|
||||
IMXRT1050_IOMUXC_GPIO1_IO08 = 18,
|
||||
IMXRT1050_IOMUXC_GPIO1_IO09 = 19,
|
||||
IMXRT1050_IOMUXC_GPIO1_IO10 = 20,
|
||||
IMXRT1050_IOMUXC_GPIO1_IO11 = 21,
|
||||
IMXRT1050_IOMUXC_GPIO1_IO12 = 22,
|
||||
IMXRT1050_IOMUXC_GPIO1_IO13 = 23,
|
||||
IMXRT1050_IOMUXC_GPIO1_IO14 = 24,
|
||||
IMXRT1050_IOMUXC_GPIO1_IO15 = 25,
|
||||
IMXRT1050_IOMUXC_ENET_MDC = 26,
|
||||
IMXRT1050_IOMUXC_ENET_MDIO = 27,
|
||||
IMXRT1050_IOMUXC_ENET_TD3 = 28,
|
||||
IMXRT1050_IOMUXC_ENET_TD2 = 29,
|
||||
IMXRT1050_IOMUXC_ENET_TD1 = 30,
|
||||
IMXRT1050_IOMUXC_ENET_TD0 = 31,
|
||||
IMXRT1050_IOMUXC_ENET_TX_CTL = 32,
|
||||
IMXRT1050_IOMUXC_ENET_TXC = 33,
|
||||
IMXRT1050_IOMUXC_ENET_RX_CTL = 34,
|
||||
IMXRT1050_IOMUXC_ENET_RXC = 35,
|
||||
IMXRT1050_IOMUXC_ENET_RD0 = 36,
|
||||
IMXRT1050_IOMUXC_ENET_RD1 = 37,
|
||||
IMXRT1050_IOMUXC_ENET_RD2 = 38,
|
||||
IMXRT1050_IOMUXC_ENET_RD3 = 39,
|
||||
IMXRT1050_IOMUXC_SD1_CLK = 40,
|
||||
IMXRT1050_IOMUXC_SD1_CMD = 41,
|
||||
IMXRT1050_IOMUXC_SD1_DATA0 = 42,
|
||||
IMXRT1050_IOMUXC_SD1_DATA1 = 43,
|
||||
IMXRT1050_IOMUXC_SD1_DATA2 = 44,
|
||||
IMXRT1050_IOMUXC_SD1_DATA3 = 45,
|
||||
IMXRT1050_IOMUXC_SD1_DATA4 = 46,
|
||||
IMXRT1050_IOMUXC_SD1_DATA5 = 47,
|
||||
IMXRT1050_IOMUXC_SD1_DATA6 = 48,
|
||||
IMXRT1050_IOMUXC_SD1_DATA7 = 49,
|
||||
IMXRT1050_IOMUXC_SD1_RESET_B = 50,
|
||||
IMXRT1050_IOMUXC_SD1_STROBE = 51,
|
||||
IMXRT1050_IOMUXC_SD2_CD_B = 52,
|
||||
IMXRT1050_IOMUXC_SD2_CLK = 53,
|
||||
IMXRT1050_IOMUXC_SD2_CMD = 54,
|
||||
IMXRT1050_IOMUXC_SD2_DATA0 = 55,
|
||||
IMXRT1050_IOMUXC_SD2_DATA1 = 56,
|
||||
IMXRT1050_IOMUXC_SD2_DATA2 = 57,
|
||||
IMXRT1050_IOMUXC_SD2_DATA3 = 58,
|
||||
IMXRT1050_IOMUXC_SD2_RESET_B = 59,
|
||||
IMXRT1050_IOMUXC_SD2_WP = 60,
|
||||
IMXRT1050_IOMUXC_NAND_ALE = 61,
|
||||
IMXRT1050_IOMUXC_NAND_CE0 = 62,
|
||||
IMXRT1050_IOMUXC_NAND_CE1 = 63,
|
||||
IMXRT1050_IOMUXC_NAND_CE2 = 64,
|
||||
IMXRT1050_IOMUXC_NAND_CE3 = 65,
|
||||
IMXRT1050_IOMUXC_NAND_CLE = 66,
|
||||
IMXRT1050_IOMUXC_NAND_DATA00 = 67,
|
||||
IMXRT1050_IOMUXC_NAND_DATA01 = 68,
|
||||
IMXRT1050_IOMUXC_NAND_DATA02 = 69,
|
||||
IMXRT1050_IOMUXC_NAND_DATA03 = 70,
|
||||
IMXRT1050_IOMUXC_NAND_DATA04 = 71,
|
||||
IMXRT1050_IOMUXC_NAND_DATA05 = 72,
|
||||
IMXRT1050_IOMUXC_NAND_DATA06 = 73,
|
||||
IMXRT1050_IOMUXC_NAND_DATA07 = 74,
|
||||
IMXRT1050_IOMUXC_NAND_DQS = 75,
|
||||
IMXRT1050_IOMUXC_NAND_RE_B = 76,
|
||||
IMXRT1050_IOMUXC_NAND_READY_B = 77,
|
||||
IMXRT1050_IOMUXC_NAND_WE_B = 78,
|
||||
IMXRT1050_IOMUXC_NAND_WP_B = 79,
|
||||
IMXRT1050_IOMUXC_SAI5_RXFS = 80,
|
||||
IMXRT1050_IOMUXC_SAI5_RXC = 81,
|
||||
IMXRT1050_IOMUXC_SAI5_RXD0 = 82,
|
||||
IMXRT1050_IOMUXC_SAI5_RXD1 = 83,
|
||||
IMXRT1050_IOMUXC_SAI5_RXD2 = 84,
|
||||
IMXRT1050_IOMUXC_SAI5_RXD3 = 85,
|
||||
IMXRT1050_IOMUXC_SAI5_MCLK = 86,
|
||||
IMXRT1050_IOMUXC_SAI1_RXFS = 87,
|
||||
IMXRT1050_IOMUXC_SAI1_RXC = 88,
|
||||
IMXRT1050_IOMUXC_SAI1_RXD0 = 89,
|
||||
IMXRT1050_IOMUXC_SAI1_RXD1 = 90,
|
||||
IMXRT1050_IOMUXC_SAI1_RXD2 = 91,
|
||||
IMXRT1050_IOMUXC_SAI1_RXD3 = 92,
|
||||
IMXRT1050_IOMUXC_SAI1_RXD4 = 93,
|
||||
IMXRT1050_IOMUXC_SAI1_RXD5 = 94,
|
||||
IMXRT1050_IOMUXC_SAI1_RXD6 = 95,
|
||||
IMXRT1050_IOMUXC_SAI1_RXD7 = 96,
|
||||
IMXRT1050_IOMUXC_SAI1_TXFS = 97,
|
||||
IMXRT1050_IOMUXC_SAI1_TXC = 98,
|
||||
IMXRT1050_IOMUXC_SAI1_TXD0 = 99,
|
||||
IMXRT1050_IOMUXC_SAI1_TXD1 = 100,
|
||||
IMXRT1050_IOMUXC_SAI1_TXD2 = 101,
|
||||
IMXRT1050_IOMUXC_SAI1_TXD3 = 102,
|
||||
IMXRT1050_IOMUXC_SAI1_TXD4 = 103,
|
||||
IMXRT1050_IOMUXC_SAI1_TXD5 = 104,
|
||||
IMXRT1050_IOMUXC_SAI1_TXD6 = 105,
|
||||
IMXRT1050_IOMUXC_SAI1_TXD7 = 106,
|
||||
IMXRT1050_IOMUXC_SAI1_MCLK = 107,
|
||||
IMXRT1050_IOMUXC_SAI2_RXFS = 108,
|
||||
IMXRT1050_IOMUXC_SAI2_RXC = 109,
|
||||
IMXRT1050_IOMUXC_SAI2_RXD0 = 110,
|
||||
IMXRT1050_IOMUXC_SAI2_TXFS = 111,
|
||||
IMXRT1050_IOMUXC_SAI2_TXC = 112,
|
||||
IMXRT1050_IOMUXC_SAI2_TXD0 = 113,
|
||||
IMXRT1050_IOMUXC_SAI2_MCLK = 114,
|
||||
IMXRT1050_IOMUXC_SAI3_RXFS = 115,
|
||||
IMXRT1050_IOMUXC_SAI3_RXC = 116,
|
||||
IMXRT1050_IOMUXC_SAI3_RXD = 117,
|
||||
IMXRT1050_IOMUXC_SAI3_TXFS = 118,
|
||||
IMXRT1050_IOMUXC_SAI3_TXC = 119,
|
||||
IMXRT1050_IOMUXC_SAI3_TXD = 120,
|
||||
IMXRT1050_IOMUXC_SAI3_MCLK = 121,
|
||||
IMXRT1050_IOMUXC_SPDIF_TX = 122,
|
||||
IMXRT1050_IOMUXC_SPDIF_RX = 123,
|
||||
IMXRT1050_IOMUXC_SPDIF_EXT_CLK = 124,
|
||||
IMXRT1050_IOMUXC_ECSPI1_SCLK = 125,
|
||||
IMXRT1050_IOMUXC_ECSPI1_MOSI = 126,
|
||||
IMXRT1050_IOMUXC_ECSPI1_MISO = 127,
|
||||
IMXRT1050_IOMUXC_ECSPI1_SS0 = 128,
|
||||
IMXRT1050_IOMUXC_ECSPI2_SCLK = 129,
|
||||
IMXRT1050_IOMUXC_ECSPI2_MOSI = 130,
|
||||
IMXRT1050_IOMUXC_ECSPI2_MISO = 131,
|
||||
IMXRT1050_IOMUXC_ECSPI2_SS0 = 132,
|
||||
IMXRT1050_IOMUXC_I2C1_SCL = 133,
|
||||
IMXRT1050_IOMUXC_I2C1_SDA = 134,
|
||||
IMXRT1050_IOMUXC_I2C2_SCL = 135,
|
||||
IMXRT1050_IOMUXC_I2C2_SDA = 136,
|
||||
IMXRT1050_IOMUXC_I2C3_SCL = 137,
|
||||
IMXRT1050_IOMUXC_I2C3_SDA = 138,
|
||||
IMXRT1050_IOMUXC_I2C4_SCL = 139,
|
||||
IMXRT1050_IOMUXC_I2C4_SDA = 140,
|
||||
IMXRT1050_IOMUXC_UART1_RXD = 141,
|
||||
IMXRT1050_IOMUXC_UART1_TXD = 142,
|
||||
IMXRT1050_IOMUXC_UART2_RXD = 143,
|
||||
IMXRT1050_IOMUXC_UART2_TXD = 144,
|
||||
IMXRT1050_IOMUXC_UART3_RXD = 145,
|
||||
IMXRT1050_IOMUXC_UART3_TXD = 146,
|
||||
IMXRT1050_IOMUXC_UART4_RXD = 147,
|
||||
IMXRT1050_IOMUXC_UART4_TXD = 148,
|
||||
};
|
||||
|
||||
/* Pad names for the pinmux subsystem */
|
||||
static const struct pinctrl_pin_desc imxrt1050_pinctrl_pads[] = {
|
||||
IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE0),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE1),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE2),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE3),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE4),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE5),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE6),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE7),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE8),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE9),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO00),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO01),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO02),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO03),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO04),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO05),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO06),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO07),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO08),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO09),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO10),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO11),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO12),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO13),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO14),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO15),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_MDC),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_MDIO),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TD3),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TD2),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TD1),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TD0),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TX_CTL),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TXC),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RX_CTL),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RXC),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RD0),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RD1),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RD2),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RD3),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_CLK),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_CMD),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA0),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA1),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA2),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA3),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA4),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA5),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA6),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA7),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_RESET_B),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_STROBE),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_CD_B),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_CLK),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_CMD),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_DATA0),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_DATA1),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_DATA2),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_DATA3),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_RESET_B),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_WP),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_ALE),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CE0),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CE1),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CE2),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CE3),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CLE),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA00),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA01),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA02),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA03),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA04),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA05),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA06),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA07),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DQS),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_RE_B),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_READY_B),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_WE_B),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_WP_B),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXFS),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXC),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXD0),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXD1),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXD2),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXD3),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_MCLK),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXFS),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXC),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD0),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD1),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD2),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD3),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD4),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD5),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD6),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD7),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXFS),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXC),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD0),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD1),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD2),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD3),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD4),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD5),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD6),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD7),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_MCLK),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_RXFS),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_RXC),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_RXD0),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_TXFS),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_TXC),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_TXD0),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_MCLK),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_RXFS),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_RXC),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_RXD),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_TXFS),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_TXC),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_TXD),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_MCLK),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SPDIF_TX),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SPDIF_RX),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SPDIF_EXT_CLK),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI1_SCLK),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI1_MOSI),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI1_MISO),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI1_SS0),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI2_SCLK),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI2_MOSI),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI2_MISO),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI2_SS0),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C1_SCL),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C1_SDA),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C2_SCL),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C2_SDA),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C3_SCL),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C3_SDA),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C4_SCL),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C4_SDA),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART1_RXD),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART1_TXD),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART2_RXD),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART2_TXD),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART3_RXD),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART3_TXD),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART4_RXD),
|
||||
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART4_TXD),
|
||||
};
|
||||
|
||||
static const struct imx_pinctrl_soc_info imxrt1050_pinctrl_info = {
|
||||
.pins = imxrt1050_pinctrl_pads,
|
||||
.npins = ARRAY_SIZE(imxrt1050_pinctrl_pads),
|
||||
.gpr_compatible = "fsl,imxrt1050-iomuxc-gpr",
|
||||
};
|
||||
|
||||
static const struct of_device_id imxrt1050_pinctrl_of_match[] = {
|
||||
{ .compatible = "fsl,imxrt1050-iomuxc", .data = &imxrt1050_pinctrl_info, },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static int imxrt1050_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
return imx_pinctrl_probe(pdev, &imxrt1050_pinctrl_info);
|
||||
}
|
||||
|
||||
static struct platform_driver imxrt1050_pinctrl_driver = {
|
||||
.driver = {
|
||||
.name = "imxrt1050-pinctrl",
|
||||
.of_match_table = of_match_ptr(imxrt1050_pinctrl_of_match),
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
.probe = imxrt1050_pinctrl_probe,
|
||||
};
|
||||
|
||||
static int __init imxrt1050_pinctrl_init(void)
|
||||
{
|
||||
return platform_driver_register(&imxrt1050_pinctrl_driver);
|
||||
}
|
||||
arch_initcall(imxrt1050_pinctrl_init);
|
||||
|
|
@ -1577,7 +1577,7 @@ static int byt_gpio_probe(struct intel_pinctrl *vg)
|
|||
vg->irqchip.irq_mask = byt_irq_mask,
|
||||
vg->irqchip.irq_unmask = byt_irq_unmask,
|
||||
vg->irqchip.irq_set_type = byt_irq_type,
|
||||
vg->irqchip.flags = IRQCHIP_SKIP_SET_WAKE,
|
||||
vg->irqchip.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED,
|
||||
|
||||
girq = &gc->irq;
|
||||
girq->chip = &vg->irqchip;
|
||||
|
|
|
|||
|
|
@ -73,6 +73,8 @@ struct intel_pad_context {
|
|||
u32 padctrl1;
|
||||
};
|
||||
|
||||
#define CHV_INVALID_HWIRQ ((unsigned int)INVALID_HWIRQ)
|
||||
|
||||
/**
|
||||
* struct intel_community_context - community context for Cherryview
|
||||
* @intr_lines: Mapping between 16 HW interrupt wires and GPIO offset (in GPIO number space)
|
||||
|
|
@ -709,6 +711,7 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
|
|||
unsigned int function, unsigned int group)
|
||||
{
|
||||
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
|
||||
struct device *dev = pctrl->dev;
|
||||
const struct intel_pingroup *grp;
|
||||
unsigned long flags;
|
||||
int i;
|
||||
|
|
@ -720,9 +723,8 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
|
|||
/* Check first that the pad is not locked */
|
||||
for (i = 0; i < grp->npins; i++) {
|
||||
if (chv_pad_locked(pctrl, grp->pins[i])) {
|
||||
dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n",
|
||||
grp->pins[i]);
|
||||
raw_spin_unlock_irqrestore(&chv_lock, flags);
|
||||
dev_warn(dev, "unable to set mode for locked pin %u\n", grp->pins[i]);
|
||||
return -EBUSY;
|
||||
}
|
||||
}
|
||||
|
|
@ -757,8 +759,8 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
|
|||
value |= CHV_PADCTRL1_INVRXTX_TXENABLE;
|
||||
chv_writel(pctrl, pin, CHV_PADCTRL1, value);
|
||||
|
||||
dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n",
|
||||
pin, mode, invert_oe ? "" : "not ");
|
||||
dev_dbg(dev, "configured pin %u mode %u OE %sinverted\n", pin, mode,
|
||||
invert_oe ? "" : "not ");
|
||||
}
|
||||
|
||||
raw_spin_unlock_irqrestore(&chv_lock, flags);
|
||||
|
|
@ -812,7 +814,7 @@ static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
|
|||
/* Reset the interrupt mapping */
|
||||
for (i = 0; i < ARRAY_SIZE(cctx->intr_lines); i++) {
|
||||
if (cctx->intr_lines[i] == offset) {
|
||||
cctx->intr_lines[i] = 0;
|
||||
cctx->intr_lines[i] = CHV_INVALID_HWIRQ;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -1058,6 +1060,7 @@ static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
|
|||
unsigned long *configs, unsigned int nconfigs)
|
||||
{
|
||||
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
|
||||
struct device *dev = pctrl->dev;
|
||||
enum pin_config_param param;
|
||||
int i, ret;
|
||||
u32 arg;
|
||||
|
|
@ -1094,8 +1097,7 @@ static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
|
|||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin,
|
||||
param, arg);
|
||||
dev_dbg(dev, "pin %d set config %d arg %u\n", pin, param, arg);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -1302,6 +1304,7 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
|
|||
if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
|
||||
struct device *dev = pctrl->dev;
|
||||
struct intel_community_context *cctx = &pctrl->context.communities[0];
|
||||
unsigned int pin = irqd_to_hwirq(d);
|
||||
irq_flow_handler_t handler;
|
||||
|
|
@ -1319,8 +1322,10 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
|
|||
else
|
||||
handler = handle_edge_irq;
|
||||
|
||||
if (!cctx->intr_lines[intsel]) {
|
||||
if (cctx->intr_lines[intsel] == CHV_INVALID_HWIRQ) {
|
||||
irq_set_handler_locked(d, handler);
|
||||
dev_dbg(dev, "using interrupt line %u for IRQ_TYPE_NONE on pin %u\n",
|
||||
intsel, pin);
|
||||
cctx->intr_lines[intsel] = pin;
|
||||
}
|
||||
raw_spin_unlock_irqrestore(&chv_lock, flags);
|
||||
|
|
@ -1330,17 +1335,74 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int chv_gpio_set_intr_line(struct intel_pinctrl *pctrl, unsigned int pin)
|
||||
{
|
||||
struct device *dev = pctrl->dev;
|
||||
struct intel_community_context *cctx = &pctrl->context.communities[0];
|
||||
const struct intel_community *community = &pctrl->communities[0];
|
||||
u32 value, intsel;
|
||||
int i;
|
||||
|
||||
value = chv_readl(pctrl, pin, CHV_PADCTRL0);
|
||||
intsel = (value & CHV_PADCTRL0_INTSEL_MASK) >> CHV_PADCTRL0_INTSEL_SHIFT;
|
||||
|
||||
if (cctx->intr_lines[intsel] == pin)
|
||||
return 0;
|
||||
|
||||
if (cctx->intr_lines[intsel] == CHV_INVALID_HWIRQ) {
|
||||
dev_dbg(dev, "using interrupt line %u for pin %u\n", intsel, pin);
|
||||
cctx->intr_lines[intsel] = pin;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* The interrupt line selected by the BIOS is already in use by
|
||||
* another pin, this is a known BIOS bug found on several models.
|
||||
* But this may also be caused by Linux deciding to use a pin as
|
||||
* IRQ which was not expected to be used as such by the BIOS authors,
|
||||
* so log this at info level only.
|
||||
*/
|
||||
dev_info(dev, "interrupt line %u is used by both pin %u and pin %u\n", intsel,
|
||||
cctx->intr_lines[intsel], pin);
|
||||
|
||||
if (chv_pad_locked(pctrl, pin))
|
||||
return -EBUSY;
|
||||
|
||||
/*
|
||||
* The BIOS fills the interrupt lines from 0 counting up, start at
|
||||
* the other end to find a free interrupt line to workaround this.
|
||||
*/
|
||||
for (i = community->nirqs - 1; i >= 0; i--) {
|
||||
if (cctx->intr_lines[i] == CHV_INVALID_HWIRQ)
|
||||
break;
|
||||
}
|
||||
if (i < 0)
|
||||
return -EBUSY;
|
||||
|
||||
dev_info(dev, "changing the interrupt line for pin %u to %d\n", pin, i);
|
||||
|
||||
value = (value & ~CHV_PADCTRL0_INTSEL_MASK) | (i << CHV_PADCTRL0_INTSEL_SHIFT);
|
||||
chv_writel(pctrl, pin, CHV_PADCTRL0, value);
|
||||
cctx->intr_lines[i] = pin;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
|
||||
struct intel_community_context *cctx = &pctrl->context.communities[0];
|
||||
unsigned int pin = irqd_to_hwirq(d);
|
||||
unsigned long flags;
|
||||
u32 value;
|
||||
int ret;
|
||||
|
||||
raw_spin_lock_irqsave(&chv_lock, flags);
|
||||
|
||||
ret = chv_gpio_set_intr_line(pctrl, pin);
|
||||
if (ret)
|
||||
goto out_unlock;
|
||||
|
||||
/*
|
||||
* Pins which can be used as shared interrupt are configured in
|
||||
* BIOS. Driver trusts BIOS configurations and assigns different
|
||||
|
|
@ -1375,26 +1437,22 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
|
|||
chv_writel(pctrl, pin, CHV_PADCTRL1, value);
|
||||
}
|
||||
|
||||
value = chv_readl(pctrl, pin, CHV_PADCTRL0);
|
||||
value &= CHV_PADCTRL0_INTSEL_MASK;
|
||||
value >>= CHV_PADCTRL0_INTSEL_SHIFT;
|
||||
|
||||
cctx->intr_lines[value] = pin;
|
||||
|
||||
if (type & IRQ_TYPE_EDGE_BOTH)
|
||||
irq_set_handler_locked(d, handle_edge_irq);
|
||||
else if (type & IRQ_TYPE_LEVEL_MASK)
|
||||
irq_set_handler_locked(d, handle_level_irq);
|
||||
|
||||
out_unlock:
|
||||
raw_spin_unlock_irqrestore(&chv_lock, flags);
|
||||
|
||||
return 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void chv_gpio_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
|
||||
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
|
||||
struct device *dev = pctrl->dev;
|
||||
const struct intel_community *community = &pctrl->communities[0];
|
||||
struct intel_community_context *cctx = &pctrl->context.communities[0];
|
||||
struct irq_chip *chip = irq_desc_get_chip(desc);
|
||||
|
|
@ -1412,6 +1470,11 @@ static void chv_gpio_irq_handler(struct irq_desc *desc)
|
|||
unsigned int offset;
|
||||
|
||||
offset = cctx->intr_lines[intr_line];
|
||||
if (offset == CHV_INVALID_HWIRQ) {
|
||||
dev_err(dev, "interrupt on unused interrupt line %u\n", intr_line);
|
||||
continue;
|
||||
}
|
||||
|
||||
generic_handle_domain_irq(gc->irq.domain, offset);
|
||||
}
|
||||
|
||||
|
|
@ -1512,17 +1575,16 @@ static int chv_gpio_irq_init_hw(struct gpio_chip *chip)
|
|||
static int chv_gpio_add_pin_ranges(struct gpio_chip *chip)
|
||||
{
|
||||
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
|
||||
struct device *dev = pctrl->dev;
|
||||
const struct intel_community *community = &pctrl->communities[0];
|
||||
const struct intel_padgroup *gpp;
|
||||
int ret, i;
|
||||
|
||||
for (i = 0; i < community->ngpps; i++) {
|
||||
gpp = &community->gpps[i];
|
||||
ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev),
|
||||
gpp->base, gpp->base,
|
||||
gpp->size);
|
||||
ret = gpiochip_add_pin_range(chip, dev_name(dev), gpp->base, gpp->base, gpp->size);
|
||||
if (ret) {
|
||||
dev_err(pctrl->dev, "failed to add GPIO pin range\n");
|
||||
dev_err(dev, "failed to add GPIO pin range\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
|
@ -1535,15 +1597,16 @@ static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq)
|
|||
const struct intel_community *community = &pctrl->communities[0];
|
||||
const struct intel_padgroup *gpp;
|
||||
struct gpio_chip *chip = &pctrl->chip;
|
||||
struct device *dev = pctrl->dev;
|
||||
bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
|
||||
int ret, i, irq_base;
|
||||
|
||||
*chip = chv_gpio_chip;
|
||||
|
||||
chip->ngpio = pctrl->soc->pins[pctrl->soc->npins - 1].number + 1;
|
||||
chip->label = dev_name(pctrl->dev);
|
||||
chip->label = dev_name(dev);
|
||||
chip->add_pin_ranges = chv_gpio_add_pin_ranges;
|
||||
chip->parent = pctrl->dev;
|
||||
chip->parent = dev;
|
||||
chip->base = -1;
|
||||
|
||||
pctrl->irq = irq;
|
||||
|
|
@ -1565,17 +1628,16 @@ static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq)
|
|||
if (need_valid_mask) {
|
||||
chip->irq.init_valid_mask = chv_init_irq_valid_mask;
|
||||
} else {
|
||||
irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0,
|
||||
pctrl->soc->npins, NUMA_NO_NODE);
|
||||
irq_base = devm_irq_alloc_descs(dev, -1, 0, pctrl->soc->npins, NUMA_NO_NODE);
|
||||
if (irq_base < 0) {
|
||||
dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n");
|
||||
dev_err(dev, "Failed to allocate IRQ numbers\n");
|
||||
return irq_base;
|
||||
}
|
||||
}
|
||||
|
||||
ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
|
||||
ret = devm_gpiochip_add_data(dev, chip, pctrl);
|
||||
if (ret) {
|
||||
dev_err(pctrl->dev, "Failed to register gpiochip\n");
|
||||
dev_err(dev, "Failed to register gpiochip\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -1617,11 +1679,13 @@ static acpi_status chv_pinctrl_mmio_access_handler(u32 function,
|
|||
static int chv_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct intel_pinctrl_soc_data *soc_data;
|
||||
struct intel_community_context *cctx;
|
||||
struct intel_community *community;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct acpi_device *adev = ACPI_COMPANION(dev);
|
||||
struct intel_pinctrl *pctrl;
|
||||
acpi_status status;
|
||||
unsigned int i;
|
||||
int ret, irq;
|
||||
|
||||
soc_data = intel_pinctrl_get_soc_data(pdev);
|
||||
|
|
@ -1663,6 +1727,10 @@ static int chv_pinctrl_probe(struct platform_device *pdev)
|
|||
if (!pctrl->context.communities)
|
||||
return -ENOMEM;
|
||||
|
||||
cctx = &pctrl->context.communities[0];
|
||||
for (i = 0; i < ARRAY_SIZE(cctx->intr_lines); i++)
|
||||
cctx->intr_lines[i] = CHV_INVALID_HWIRQ;
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0)
|
||||
return irq;
|
||||
|
|
@ -1767,15 +1835,15 @@ static int chv_pinctrl_resume_noirq(struct device *dev)
|
|||
val &= ~CHV_PADCTRL0_GPIORXSTATE;
|
||||
if (ctx->padctrl0 != val) {
|
||||
chv_writel(pctrl, desc->number, CHV_PADCTRL0, ctx->padctrl0);
|
||||
dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n",
|
||||
desc->number, chv_readl(pctrl, desc->number, CHV_PADCTRL0));
|
||||
dev_dbg(dev, "restored pin %2u ctrl0 0x%08x\n", desc->number,
|
||||
chv_readl(pctrl, desc->number, CHV_PADCTRL0));
|
||||
}
|
||||
|
||||
val = chv_readl(pctrl, desc->number, CHV_PADCTRL1);
|
||||
if (ctx->padctrl1 != val) {
|
||||
chv_writel(pctrl, desc->number, CHV_PADCTRL1, ctx->padctrl1);
|
||||
dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n",
|
||||
desc->number, chv_readl(pctrl, desc->number, CHV_PADCTRL1));
|
||||
dev_dbg(dev, "restored pin %2u ctrl1 0x%08x\n", desc->number,
|
||||
chv_readl(pctrl, desc->number, CHV_PADCTRL1));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -519,7 +519,7 @@ static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
|
|||
return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce);
|
||||
}
|
||||
|
||||
static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np)
|
||||
static int mtk_build_gpiochip(struct mtk_pinctrl *hw)
|
||||
{
|
||||
struct gpio_chip *chip = &hw->chip;
|
||||
int ret;
|
||||
|
|
@ -536,7 +536,6 @@ static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np)
|
|||
chip->set_config = mtk_gpio_set_config;
|
||||
chip->base = -1;
|
||||
chip->ngpio = hw->soc->npins;
|
||||
chip->of_node = np;
|
||||
chip->of_gpio_n_cells = 2;
|
||||
|
||||
ret = gpiochip_add_data(chip, hw);
|
||||
|
|
@ -550,7 +549,7 @@ static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np)
|
|||
* Documentation/devicetree/bindings/gpio/gpio.txt on how to
|
||||
* bind pinctrl and gpio drivers via the "gpio-ranges" property.
|
||||
*/
|
||||
if (!of_find_property(np, "gpio-ranges", NULL)) {
|
||||
if (!of_find_property(hw->dev->of_node, "gpio-ranges", NULL)) {
|
||||
ret = gpiochip_add_pin_range(chip, dev_name(hw->dev), 0, 0,
|
||||
chip->ngpio);
|
||||
if (ret < 0) {
|
||||
|
|
@ -691,7 +690,7 @@ int mtk_moore_pinctrl_probe(struct platform_device *pdev,
|
|||
"Failed to add EINT, but pinctrl still can work\n");
|
||||
|
||||
/* Build gpiochip should be after pinctrl_enable is done */
|
||||
err = mtk_build_gpiochip(hw, pdev->dev.of_node);
|
||||
err = mtk_build_gpiochip(hw);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "Failed to add gpio_chip\n");
|
||||
return err;
|
||||
|
|
|
|||
|
|
@ -815,6 +815,8 @@ static int mtk_pinconf_bias_get_rsel(struct mtk_pinctrl *hw,
|
|||
goto out;
|
||||
|
||||
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd);
|
||||
if (err)
|
||||
goto out;
|
||||
|
||||
if (pu == 0 && pd == 0) {
|
||||
*pullup = 0;
|
||||
|
|
|
|||
|
|
@ -581,7 +581,7 @@ ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw,
|
|||
{
|
||||
int pinmux, pullup, pullen, len = 0, r1 = -1, r0 = -1, rsel = -1;
|
||||
const struct mtk_pin_desc *desc;
|
||||
u32 try_all_type;
|
||||
u32 try_all_type = 0;
|
||||
|
||||
if (gpio >= hw->soc->npins)
|
||||
return -EINVAL;
|
||||
|
|
@ -895,7 +895,7 @@ static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
|
|||
return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce);
|
||||
}
|
||||
|
||||
static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np)
|
||||
static int mtk_build_gpiochip(struct mtk_pinctrl *hw)
|
||||
{
|
||||
struct gpio_chip *chip = &hw->chip;
|
||||
int ret;
|
||||
|
|
@ -913,7 +913,6 @@ static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np)
|
|||
chip->set_config = mtk_gpio_set_config;
|
||||
chip->base = -1;
|
||||
chip->ngpio = hw->soc->npins;
|
||||
chip->of_node = np;
|
||||
chip->of_gpio_n_cells = 2;
|
||||
|
||||
ret = gpiochip_add_data(chip, hw);
|
||||
|
|
@ -1037,7 +1036,7 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev,
|
|||
"Failed to add EINT, but pinctrl still can work\n");
|
||||
|
||||
/* Build gpiochip should be after pinctrl_enable is done */
|
||||
err = mtk_build_gpiochip(hw, pdev->dev.of_node);
|
||||
err = mtk_build_gpiochip(hw);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "Failed to add gpio_chip\n");
|
||||
return err;
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@
|
|||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/string_helpers.h>
|
||||
|
||||
#include "../pinctrl-utils.h"
|
||||
|
||||
|
|
@ -341,12 +342,12 @@ static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev,
|
|||
struct armada_37xx_pin_group *grp)
|
||||
{
|
||||
struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
|
||||
struct device *dev = info->dev;
|
||||
unsigned int reg = SELECTION;
|
||||
unsigned int mask = grp->reg_mask;
|
||||
int func, val;
|
||||
|
||||
dev_dbg(info->dev, "enable function %s group %s\n",
|
||||
name, grp->name);
|
||||
dev_dbg(dev, "enable function %s group %s\n", name, grp->name);
|
||||
|
||||
func = match_string(grp->funcs, NB_FUNCS, name);
|
||||
if (func < 0)
|
||||
|
|
@ -722,25 +723,22 @@ static unsigned int armada_37xx_irq_startup(struct irq_data *d)
|
|||
static int armada_37xx_irqchip_register(struct platform_device *pdev,
|
||||
struct armada_37xx_pinctrl *info)
|
||||
{
|
||||
struct device_node *np = info->dev->of_node;
|
||||
struct gpio_chip *gc = &info->gpio_chip;
|
||||
struct irq_chip *irqchip = &info->irq_chip;
|
||||
struct gpio_irq_chip *girq = &gc->irq;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct resource res;
|
||||
struct device_node *np;
|
||||
int ret = -ENODEV, i, nr_irq_parent;
|
||||
|
||||
/* Check if we have at least one gpio-controller child node */
|
||||
for_each_child_of_node(info->dev->of_node, np) {
|
||||
for_each_child_of_node(dev->of_node, np) {
|
||||
if (of_property_read_bool(np, "gpio-controller")) {
|
||||
ret = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (ret) {
|
||||
dev_err(dev, "no gpio-controller child node\n");
|
||||
return ret;
|
||||
}
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "no gpio-controller child node\n");
|
||||
|
||||
nr_irq_parent = of_irq_count(np);
|
||||
spin_lock_init(&info->irq_lock);
|
||||
|
|
@ -750,12 +748,7 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev,
|
|||
return 0;
|
||||
}
|
||||
|
||||
if (of_address_to_resource(info->dev->of_node, 1, &res)) {
|
||||
dev_err(dev, "cannot find IO resource\n");
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
info->base = devm_ioremap_resource(info->dev, &res);
|
||||
info->base = devm_platform_ioremap_resource(pdev, 1);
|
||||
if (IS_ERR(info->base))
|
||||
return PTR_ERR(info->base);
|
||||
|
||||
|
|
@ -774,8 +767,7 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev,
|
|||
* the chained irq with all of them.
|
||||
*/
|
||||
girq->num_parents = nr_irq_parent;
|
||||
girq->parents = devm_kcalloc(&pdev->dev, nr_irq_parent,
|
||||
sizeof(*girq->parents), GFP_KERNEL);
|
||||
girq->parents = devm_kcalloc(dev, nr_irq_parent, sizeof(*girq->parents), GFP_KERNEL);
|
||||
if (!girq->parents)
|
||||
return -ENOMEM;
|
||||
for (i = 0; i < nr_irq_parent; i++) {
|
||||
|
|
@ -794,11 +786,12 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev,
|
|||
static int armada_37xx_gpiochip_register(struct platform_device *pdev,
|
||||
struct armada_37xx_pinctrl *info)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np;
|
||||
struct gpio_chip *gc;
|
||||
int ret = -ENODEV;
|
||||
|
||||
for_each_child_of_node(info->dev->of_node, np) {
|
||||
for_each_child_of_node(dev->of_node, np) {
|
||||
if (of_find_property(np, "gpio-controller", NULL)) {
|
||||
ret = 0;
|
||||
break;
|
||||
|
|
@ -811,19 +804,16 @@ static int armada_37xx_gpiochip_register(struct platform_device *pdev,
|
|||
|
||||
gc = &info->gpio_chip;
|
||||
gc->ngpio = info->data->nr_pins;
|
||||
gc->parent = &pdev->dev;
|
||||
gc->parent = dev;
|
||||
gc->base = -1;
|
||||
gc->of_node = np;
|
||||
gc->label = info->data->name;
|
||||
|
||||
ret = armada_37xx_irqchip_register(pdev, info);
|
||||
if (ret)
|
||||
return ret;
|
||||
ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
return devm_gpiochip_add_data(dev, gc, info);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -874,13 +864,13 @@ static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs,
|
|||
static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
|
||||
{
|
||||
int n, num = 0, funcsize = info->data->nr_pins;
|
||||
struct device *dev = info->dev;
|
||||
|
||||
for (n = 0; n < info->ngroups; n++) {
|
||||
struct armada_37xx_pin_group *grp = &info->groups[n];
|
||||
int i, j, f;
|
||||
|
||||
grp->pins = devm_kcalloc(info->dev,
|
||||
grp->npins + grp->extra_npins,
|
||||
grp->pins = devm_kcalloc(dev, grp->npins + grp->extra_npins,
|
||||
sizeof(*grp->pins),
|
||||
GFP_KERNEL);
|
||||
if (!grp->pins)
|
||||
|
|
@ -898,8 +888,7 @@ static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
|
|||
ret = armada_37xx_add_function(info->funcs, &funcsize,
|
||||
grp->funcs[f]);
|
||||
if (ret == -EOVERFLOW)
|
||||
dev_err(info->dev,
|
||||
"More functions than pins(%d)\n",
|
||||
dev_err(dev, "More functions than pins(%d)\n",
|
||||
info->data->nr_pins);
|
||||
if (ret < 0)
|
||||
continue;
|
||||
|
|
@ -913,7 +902,7 @@ static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
|
|||
}
|
||||
|
||||
/**
|
||||
* armada_37xx_fill_funcs() - complete the funcs array
|
||||
* armada_37xx_fill_func() - complete the funcs array
|
||||
* @info: info driver instance
|
||||
*
|
||||
* Based on the data available from the armada_37xx_pin_group array
|
||||
|
|
@ -925,6 +914,7 @@ static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
|
|||
static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
|
||||
{
|
||||
struct armada_37xx_pmx_func *funcs = info->funcs;
|
||||
struct device *dev = info->dev;
|
||||
int n;
|
||||
|
||||
for (n = 0; n < info->nfuncs; n++) {
|
||||
|
|
@ -932,8 +922,7 @@ static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
|
|||
const char **groups;
|
||||
int g;
|
||||
|
||||
funcs[n].groups = devm_kcalloc(info->dev,
|
||||
funcs[n].ngroups,
|
||||
funcs[n].groups = devm_kcalloc(dev, funcs[n].ngroups,
|
||||
sizeof(*(funcs[n].groups)),
|
||||
GFP_KERNEL);
|
||||
if (!funcs[n].groups)
|
||||
|
|
@ -962,6 +951,8 @@ static int armada_37xx_pinctrl_register(struct platform_device *pdev,
|
|||
const struct armada_37xx_pin_data *pin_data = info->data;
|
||||
struct pinctrl_desc *ctrldesc = &info->pctl;
|
||||
struct pinctrl_pin_desc *pindesc, *pdesc;
|
||||
struct device *dev = &pdev->dev;
|
||||
char **pin_names;
|
||||
int pin, ret;
|
||||
|
||||
info->groups = pin_data->groups;
|
||||
|
|
@ -973,20 +964,21 @@ static int armada_37xx_pinctrl_register(struct platform_device *pdev,
|
|||
ctrldesc->pmxops = &armada_37xx_pmx_ops;
|
||||
ctrldesc->confops = &armada_37xx_pinconf_ops;
|
||||
|
||||
pindesc = devm_kcalloc(&pdev->dev,
|
||||
pin_data->nr_pins, sizeof(*pindesc),
|
||||
GFP_KERNEL);
|
||||
pindesc = devm_kcalloc(dev, pin_data->nr_pins, sizeof(*pindesc), GFP_KERNEL);
|
||||
if (!pindesc)
|
||||
return -ENOMEM;
|
||||
|
||||
ctrldesc->pins = pindesc;
|
||||
ctrldesc->npins = pin_data->nr_pins;
|
||||
|
||||
pin_names = devm_kasprintf_strarray(dev, pin_data->name, pin_data->nr_pins);
|
||||
if (IS_ERR(pin_names))
|
||||
return PTR_ERR(pin_names);
|
||||
|
||||
pdesc = pindesc;
|
||||
for (pin = 0; pin < pin_data->nr_pins; pin++) {
|
||||
pdesc->number = pin;
|
||||
pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
|
||||
pin_data->name, pin);
|
||||
pdesc->name = pin_names[pin];
|
||||
pdesc++;
|
||||
}
|
||||
|
||||
|
|
@ -994,14 +986,10 @@ static int armada_37xx_pinctrl_register(struct platform_device *pdev,
|
|||
* we allocate functions for number of pins and hope there are
|
||||
* fewer unique functions than pins available
|
||||
*/
|
||||
info->funcs = devm_kcalloc(&pdev->dev,
|
||||
pin_data->nr_pins,
|
||||
sizeof(struct armada_37xx_pmx_func),
|
||||
GFP_KERNEL);
|
||||
info->funcs = devm_kcalloc(dev, pin_data->nr_pins, sizeof(*info->funcs), GFP_KERNEL);
|
||||
if (!info->funcs)
|
||||
return -ENOMEM;
|
||||
|
||||
|
||||
ret = armada_37xx_fill_group(info);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
|
@ -1010,11 +998,9 @@ static int armada_37xx_pinctrl_register(struct platform_device *pdev,
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
|
||||
if (IS_ERR(info->pctl_dev)) {
|
||||
dev_err(&pdev->dev, "could not register pinctrl driver\n");
|
||||
return PTR_ERR(info->pctl_dev);
|
||||
}
|
||||
info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info);
|
||||
if (IS_ERR(info->pctl_dev))
|
||||
return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1143,18 +1129,15 @@ static int __init armada_37xx_pinctrl_probe(struct platform_device *pdev)
|
|||
struct regmap *regmap;
|
||||
int ret;
|
||||
|
||||
info = devm_kzalloc(dev, sizeof(struct armada_37xx_pinctrl),
|
||||
GFP_KERNEL);
|
||||
info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
|
||||
if (!info)
|
||||
return -ENOMEM;
|
||||
|
||||
info->dev = dev;
|
||||
|
||||
regmap = syscon_node_to_regmap(np);
|
||||
if (IS_ERR(regmap)) {
|
||||
dev_err(&pdev->dev, "cannot get regmap\n");
|
||||
return PTR_ERR(regmap);
|
||||
}
|
||||
if (IS_ERR(regmap))
|
||||
return dev_err_probe(dev, PTR_ERR(regmap), "cannot get regmap\n");
|
||||
info->regmap = regmap;
|
||||
|
||||
info->data = of_device_get_match_data(dev);
|
||||
|
|
|
|||
|
|
@ -46,6 +46,7 @@ static const struct pin_config_item conf_items[] = {
|
|||
PCONFDUMP(PIN_CONFIG_MODE_LOW_POWER, "pin low power", "mode", true),
|
||||
PCONFDUMP(PIN_CONFIG_OUTPUT_ENABLE, "output enabled", NULL, false),
|
||||
PCONFDUMP(PIN_CONFIG_OUTPUT, "pin output", "level", true),
|
||||
PCONFDUMP(PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS, "output impedance", "ohms", true),
|
||||
PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector", true),
|
||||
PCONFDUMP(PIN_CONFIG_SLEEP_HARDWARE_STATE, "sleep hardware state", NULL, false),
|
||||
PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL, true),
|
||||
|
|
@ -179,6 +180,7 @@ static const struct pinconf_generic_params dt_params[] = {
|
|||
{ "output-disable", PIN_CONFIG_OUTPUT_ENABLE, 0 },
|
||||
{ "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 },
|
||||
{ "output-high", PIN_CONFIG_OUTPUT, 1, },
|
||||
{ "output-impedance-ohms", PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS, 0 },
|
||||
{ "output-low", PIN_CONFIG_OUTPUT, 0, },
|
||||
{ "power-source", PIN_CONFIG_POWER_SOURCE, 0 },
|
||||
{ "sleep-hardware-state", PIN_CONFIG_SLEEP_HARDWARE_STATE, 0 },
|
||||
|
|
|
|||
|
|
@ -1009,9 +1009,6 @@ static int amd_gpio_probe(struct platform_device *pdev)
|
|||
gpio_dev->gc.owner = THIS_MODULE;
|
||||
gpio_dev->gc.parent = &pdev->dev;
|
||||
gpio_dev->gc.ngpio = resource_size(res) / 4;
|
||||
#if defined(CONFIG_OF_GPIO)
|
||||
gpio_dev->gc.of_node = pdev->dev.of_node;
|
||||
#endif
|
||||
|
||||
gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64;
|
||||
gpio_dev->groups = kerncz_groups;
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
*/
|
||||
|
||||
#include <dt-bindings/pinctrl/apple.h>
|
||||
#include <linux/bits.h>
|
||||
#include <linux/gpio/driver.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
|
|
@ -36,7 +37,7 @@ struct apple_gpio_pinctrl {
|
|||
struct pinctrl_desc pinctrl_desc;
|
||||
struct gpio_chip gpio_chip;
|
||||
struct irq_chip irq_chip;
|
||||
u8 irqgrps[0];
|
||||
u8 irqgrps[];
|
||||
};
|
||||
|
||||
#define REG_GPIO(x) (4 * (x))
|
||||
|
|
@ -70,31 +71,35 @@ struct regmap_config regmap_config = {
|
|||
.cache_type = REGCACHE_FLAT,
|
||||
.max_register = 512 * sizeof(u32),
|
||||
.num_reg_defaults_raw = 512,
|
||||
.use_relaxed_mmio = true
|
||||
.use_relaxed_mmio = true,
|
||||
};
|
||||
|
||||
// No locking needed to mask/unmask IRQs as the interrupt mode is per pin-register.
|
||||
/* No locking needed to mask/unmask IRQs as the interrupt mode is per pin-register. */
|
||||
static void apple_gpio_set_reg(struct apple_gpio_pinctrl *pctl,
|
||||
unsigned int pin, u32 mask, u32 value)
|
||||
unsigned int pin, u32 mask, u32 value)
|
||||
{
|
||||
regmap_update_bits(pctl->map, REG_GPIO(pin), mask, value);
|
||||
}
|
||||
|
||||
static uint32_t apple_gpio_get_reg(struct apple_gpio_pinctrl *pctl,
|
||||
unsigned int pin)
|
||||
static u32 apple_gpio_get_reg(struct apple_gpio_pinctrl *pctl,
|
||||
unsigned int pin)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
int ret;
|
||||
u32 val;
|
||||
|
||||
ret = regmap_read(pctl->map, REG_GPIO(pin), &val);
|
||||
if (ret)
|
||||
return 0;
|
||||
|
||||
regmap_read(pctl->map, REG_GPIO(pin), &val);
|
||||
return val;
|
||||
}
|
||||
|
||||
/* Pin controller functions */
|
||||
|
||||
static int apple_gpio_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
struct device_node *node,
|
||||
struct pinctrl_map **map,
|
||||
unsigned *num_maps)
|
||||
struct device_node *node,
|
||||
struct pinctrl_map **map,
|
||||
unsigned *num_maps)
|
||||
{
|
||||
unsigned reserved_maps;
|
||||
struct apple_gpio_pinctrl *pctl;
|
||||
|
|
@ -114,13 +119,12 @@ static int apple_gpio_dt_node_to_map(struct pinctrl_dev *pctldev,
|
|||
dev_err(pctl->dev,
|
||||
"missing or empty pinmux property in node %pOFn.\n",
|
||||
node);
|
||||
return ret;
|
||||
return ret ? ret : -EINVAL;
|
||||
}
|
||||
|
||||
num_pins = ret;
|
||||
|
||||
ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps, num_maps,
|
||||
num_pins);
|
||||
ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps, num_maps, num_pins);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
@ -138,11 +142,10 @@ static int apple_gpio_dt_node_to_map(struct pinctrl_dev *pctldev,
|
|||
}
|
||||
|
||||
group_name = pinctrl_generic_get_group_name(pctldev, pin);
|
||||
function_name =
|
||||
pinmux_generic_get_function_name(pctl->pctldev, func);
|
||||
function_name = pinmux_generic_get_function_name(pctl->pctldev, func);
|
||||
ret = pinctrl_utils_add_map_mux(pctl->pctldev, map,
|
||||
&reserved_maps, num_maps,
|
||||
group_name, function_name);
|
||||
&reserved_maps, num_maps,
|
||||
group_name, function_name);
|
||||
if (ret)
|
||||
goto free_map;
|
||||
}
|
||||
|
|
@ -165,7 +168,7 @@ static const struct pinctrl_ops apple_gpio_pinctrl_ops = {
|
|||
/* Pin multiplexer functions */
|
||||
|
||||
static int apple_gpio_pinmux_set(struct pinctrl_dev *pctldev, unsigned func,
|
||||
unsigned group)
|
||||
unsigned group)
|
||||
{
|
||||
struct apple_gpio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
|
|
@ -186,14 +189,14 @@ static const struct pinmux_ops apple_gpio_pinmux_ops = {
|
|||
|
||||
/* GPIO chip functions */
|
||||
|
||||
static int apple_gpio_get_direction(struct gpio_chip *chip,
|
||||
unsigned int offset)
|
||||
static int apple_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
|
||||
{
|
||||
struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
|
||||
unsigned int reg = apple_gpio_get_reg(pctl, offset);
|
||||
|
||||
return (FIELD_GET(REG_GPIOx_MODE, reg) == REG_GPIOx_OUT) ?
|
||||
GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
|
||||
if (FIELD_GET(REG_GPIOx_MODE, reg) == REG_GPIOx_OUT)
|
||||
return GPIO_LINE_DIRECTION_OUT;
|
||||
return GPIO_LINE_DIRECTION_IN;
|
||||
}
|
||||
|
||||
static int apple_gpio_get(struct gpio_chip *chip, unsigned offset)
|
||||
|
|
@ -211,17 +214,14 @@ static int apple_gpio_get(struct gpio_chip *chip, unsigned offset)
|
|||
return !!(reg & REG_GPIOx_DATA);
|
||||
}
|
||||
|
||||
static void apple_gpio_set(struct gpio_chip *chip, unsigned int offset,
|
||||
int value)
|
||||
static void apple_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
|
||||
{
|
||||
struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
|
||||
|
||||
apple_gpio_set_reg(pctl, offset, REG_GPIOx_DATA,
|
||||
value ? REG_GPIOx_DATA : 0);
|
||||
apple_gpio_set_reg(pctl, offset, REG_GPIOx_DATA, value ? REG_GPIOx_DATA : 0);
|
||||
}
|
||||
|
||||
static int apple_gpio_direction_input(struct gpio_chip *chip,
|
||||
unsigned int offset)
|
||||
static int apple_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
|
||||
{
|
||||
struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
|
||||
|
||||
|
|
@ -234,7 +234,7 @@ static int apple_gpio_direction_input(struct gpio_chip *chip,
|
|||
}
|
||||
|
||||
static int apple_gpio_direction_output(struct gpio_chip *chip,
|
||||
unsigned int offset, int value)
|
||||
unsigned int offset, int value)
|
||||
{
|
||||
struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
|
||||
|
||||
|
|
@ -249,13 +249,10 @@ static int apple_gpio_direction_output(struct gpio_chip *chip,
|
|||
|
||||
static void apple_gpio_irq_ack(struct irq_data *data)
|
||||
{
|
||||
struct apple_gpio_pinctrl *pctl =
|
||||
gpiochip_get_data(irq_data_get_irq_chip_data(data));
|
||||
unsigned int irqgrp =
|
||||
FIELD_GET(REG_GPIOx_GRP, apple_gpio_get_reg(pctl, data->hwirq));
|
||||
struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data));
|
||||
unsigned int irqgrp = FIELD_GET(REG_GPIOx_GRP, apple_gpio_get_reg(pctl, data->hwirq));
|
||||
|
||||
writel(BIT(data->hwirq & 31),
|
||||
pctl->base + REG_IRQ(irqgrp, data->hwirq));
|
||||
writel(BIT(data->hwirq % 32), pctl->base + REG_IRQ(irqgrp, data->hwirq));
|
||||
}
|
||||
|
||||
static unsigned int apple_gpio_irq_type(unsigned int type)
|
||||
|
|
@ -278,20 +275,19 @@ static unsigned int apple_gpio_irq_type(unsigned int type)
|
|||
|
||||
static void apple_gpio_irq_mask(struct irq_data *data)
|
||||
{
|
||||
struct apple_gpio_pinctrl *pctl =
|
||||
gpiochip_get_data(irq_data_get_irq_chip_data(data));
|
||||
struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data));
|
||||
|
||||
apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
|
||||
FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_IN_IRQ_OFF));
|
||||
FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_IN_IRQ_OFF));
|
||||
}
|
||||
|
||||
static void apple_gpio_irq_unmask(struct irq_data *data)
|
||||
{
|
||||
struct apple_gpio_pinctrl *pctl =
|
||||
gpiochip_get_data(irq_data_get_irq_chip_data(data));
|
||||
struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data));
|
||||
unsigned int irqtype = apple_gpio_irq_type(irqd_get_trigger_type(data));
|
||||
|
||||
apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
|
||||
FIELD_PREP(REG_GPIOx_MODE, irqtype));
|
||||
FIELD_PREP(REG_GPIOx_MODE, irqtype));
|
||||
}
|
||||
|
||||
static unsigned int apple_gpio_irq_startup(struct irq_data *data)
|
||||
|
|
@ -300,7 +296,7 @@ static unsigned int apple_gpio_irq_startup(struct irq_data *data)
|
|||
struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
|
||||
|
||||
apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_GRP,
|
||||
FIELD_PREP(REG_GPIOx_GRP, 0));
|
||||
FIELD_PREP(REG_GPIOx_GRP, 0));
|
||||
|
||||
apple_gpio_direction_input(chip, data->hwirq);
|
||||
apple_gpio_irq_unmask(data);
|
||||
|
|
@ -308,18 +304,16 @@ static unsigned int apple_gpio_irq_startup(struct irq_data *data)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int apple_gpio_irq_set_type(struct irq_data *data,
|
||||
unsigned int type)
|
||||
static int apple_gpio_irq_set_type(struct irq_data *data, unsigned int type)
|
||||
{
|
||||
struct apple_gpio_pinctrl *pctl =
|
||||
gpiochip_get_data(irq_data_get_irq_chip_data(data));
|
||||
struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data));
|
||||
unsigned int irqtype = apple_gpio_irq_type(type);
|
||||
|
||||
if (irqtype == REG_GPIOx_IN_IRQ_OFF)
|
||||
return -EINVAL;
|
||||
|
||||
apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
|
||||
FIELD_PREP(REG_GPIOx_MODE, irqtype));
|
||||
FIELD_PREP(REG_GPIOx_MODE, irqtype));
|
||||
|
||||
if (type & IRQ_TYPE_LEVEL_MASK)
|
||||
irq_set_handler_locked(data, handle_level_irq);
|
||||
|
|
@ -366,10 +360,6 @@ static int apple_gpio_register(struct apple_gpio_pinctrl *pctl)
|
|||
void **irq_data = NULL;
|
||||
int ret;
|
||||
|
||||
if (!of_property_read_bool(pctl->dev->of_node, "gpio-controller"))
|
||||
return dev_err_probe(pctl->dev, -ENODEV,
|
||||
"No gpio-controller property\n");
|
||||
|
||||
pctl->irq_chip = apple_gpio_irqchip;
|
||||
|
||||
pctl->gpio_chip.label = dev_name(pctl->dev);
|
||||
|
|
@ -383,7 +373,6 @@ static int apple_gpio_register(struct apple_gpio_pinctrl *pctl)
|
|||
pctl->gpio_chip.base = -1;
|
||||
pctl->gpio_chip.ngpio = pctl->pinctrl_desc.npins;
|
||||
pctl->gpio_chip.parent = pctl->dev;
|
||||
pctl->gpio_chip.of_node = pctl->dev->of_node;
|
||||
|
||||
if (girq->num_parents) {
|
||||
int i;
|
||||
|
|
@ -398,14 +387,13 @@ static int apple_gpio_register(struct apple_gpio_pinctrl *pctl)
|
|||
GFP_KERNEL);
|
||||
if (!girq->parents || !irq_data) {
|
||||
ret = -ENOMEM;
|
||||
goto out;
|
||||
goto out_free_irq_data;
|
||||
}
|
||||
|
||||
for (i = 0; i < girq->num_parents; i++) {
|
||||
ret = platform_get_irq(to_platform_device(pctl->dev),
|
||||
i);
|
||||
ret = platform_get_irq(to_platform_device(pctl->dev), i);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
goto out_free_irq_data;
|
||||
|
||||
girq->parents[i] = ret;
|
||||
pctl->irqgrps[i] = i;
|
||||
|
|
@ -419,7 +407,8 @@ static int apple_gpio_register(struct apple_gpio_pinctrl *pctl)
|
|||
}
|
||||
|
||||
ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl);
|
||||
out:
|
||||
|
||||
out_free_irq_data:
|
||||
kfree(girq->parents);
|
||||
kfree(irq_data);
|
||||
|
||||
|
|
|
|||
|
|
@ -23,19 +23,20 @@
|
|||
#include <linux/delay.h>
|
||||
#include <linux/gpio/driver.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/mfd/as3722.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm.h>
|
||||
#include <linux/property.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include <linux/pinctrl/pinconf-generic.h>
|
||||
#include <linux/pinctrl/pinconf.h>
|
||||
#include <linux/pinctrl/pinmux.h>
|
||||
#include <linux/pm.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include "core.h"
|
||||
#include "pinconf.h"
|
||||
|
|
@ -551,12 +552,13 @@ static int as3722_pinctrl_probe(struct platform_device *pdev)
|
|||
struct as3722_pctrl_info *as_pci;
|
||||
int ret;
|
||||
|
||||
device_set_node(&pdev->dev, dev_fwnode(pdev->dev.parent));
|
||||
|
||||
as_pci = devm_kzalloc(&pdev->dev, sizeof(*as_pci), GFP_KERNEL);
|
||||
if (!as_pci)
|
||||
return -ENOMEM;
|
||||
|
||||
as_pci->dev = &pdev->dev;
|
||||
as_pci->dev->of_node = pdev->dev.parent->of_node;
|
||||
as_pci->as3722 = dev_get_drvdata(pdev->dev.parent);
|
||||
platform_set_drvdata(pdev, as_pci);
|
||||
|
||||
|
|
@ -578,7 +580,6 @@ static int as3722_pinctrl_probe(struct platform_device *pdev)
|
|||
|
||||
as_pci->gpio_chip = as3722_gpio_chip;
|
||||
as_pci->gpio_chip.parent = &pdev->dev;
|
||||
as_pci->gpio_chip.of_node = pdev->dev.parent->of_node;
|
||||
ret = gpiochip_add_data(&as_pci->gpio_chip, as_pci);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "Couldn't register gpiochip, %d\n", ret);
|
||||
|
|
|
|||
|
|
@ -1136,7 +1136,6 @@ static int atmel_pinctrl_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
atmel_pioctrl->gpio_chip = &atmel_gpio_chip;
|
||||
atmel_pioctrl->gpio_chip->of_node = dev->of_node;
|
||||
atmel_pioctrl->gpio_chip->ngpio = atmel_pioctrl->npins;
|
||||
atmel_pioctrl->gpio_chip->label = dev_name(dev);
|
||||
atmel_pioctrl->gpio_chip->parent = dev;
|
||||
|
|
|
|||
|
|
@ -1868,7 +1868,6 @@ static int at91_gpio_probe(struct platform_device *pdev)
|
|||
at91_chip->chip = at91_gpio_template;
|
||||
|
||||
chip = &at91_chip->chip;
|
||||
chip->of_node = np;
|
||||
chip->label = dev_name(&pdev->dev);
|
||||
chip->parent = &pdev->dev;
|
||||
chip->owner = THIS_MODULE;
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@
|
|||
#include <linux/bits.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/property.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <linux/gpio/driver.h>
|
||||
|
|
@ -256,6 +257,8 @@ static int da9062_pctl_probe(struct platform_device *pdev)
|
|||
struct da9062_pctl *pctl;
|
||||
int i;
|
||||
|
||||
device_set_node(&pdev->dev, dev_fwnode(pdev->dev.parent));
|
||||
|
||||
pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
|
||||
if (!pctl)
|
||||
return -ENOMEM;
|
||||
|
|
@ -277,9 +280,6 @@ static int da9062_pctl_probe(struct platform_device *pdev)
|
|||
pctl->gc = reference_gc;
|
||||
pctl->gc.label = dev_name(&pdev->dev);
|
||||
pctl->gc.parent = &pdev->dev;
|
||||
#ifdef CONFIG_OF_GPIO
|
||||
pctl->gc.of_node = parent->of_node;
|
||||
#endif
|
||||
|
||||
platform_set_drvdata(pdev, pctl);
|
||||
|
||||
|
|
|
|||
|
|
@ -233,7 +233,7 @@ static void dc_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
|
|||
spin_unlock_irqrestore(&pmap->lock, flags);
|
||||
}
|
||||
|
||||
static int dc_gpiochip_add(struct dc_pinmap *pmap, struct device_node *np)
|
||||
static int dc_gpiochip_add(struct dc_pinmap *pmap)
|
||||
{
|
||||
struct gpio_chip *chip = &pmap->chip;
|
||||
int ret;
|
||||
|
|
@ -248,7 +248,6 @@ static int dc_gpiochip_add(struct dc_pinmap *pmap, struct device_node *np)
|
|||
chip->set = dc_gpio_set;
|
||||
chip->base = -1;
|
||||
chip->ngpio = PINS_COUNT;
|
||||
chip->of_node = np;
|
||||
chip->of_gpio_n_cells = 2;
|
||||
|
||||
spin_lock_init(&pmap->lock);
|
||||
|
|
@ -326,7 +325,7 @@ static int dc_pinctrl_probe(struct platform_device *pdev)
|
|||
return PTR_ERR(pmap->pctl);
|
||||
}
|
||||
|
||||
return dc_gpiochip_add(pmap, pdev->dev.of_node);
|
||||
return dc_gpiochip_add(pmap);
|
||||
}
|
||||
|
||||
static const struct of_device_id dc_pinctrl_ids[] = {
|
||||
|
|
|
|||
|
|
@ -1555,58 +1555,42 @@ static int keembay_pinctrl_reg(struct keembay_pinctrl *kpc, struct device *dev)
|
|||
}
|
||||
|
||||
static int keembay_add_functions(struct keembay_pinctrl *kpc,
|
||||
struct function_desc *function)
|
||||
struct function_desc *functions)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
/* Assign the groups for each function */
|
||||
for (i = 0; i < kpc->npins; i++) {
|
||||
const struct pinctrl_pin_desc *pdesc = keembay_pins + i;
|
||||
struct keembay_mux_desc *mux = pdesc->drv_data;
|
||||
for (i = 0; i < kpc->nfuncs; i++) {
|
||||
struct function_desc *func = &functions[i];
|
||||
const char **group_names;
|
||||
unsigned int grp_idx = 0;
|
||||
int j;
|
||||
|
||||
while (mux->name) {
|
||||
struct function_desc *func;
|
||||
const char **grp;
|
||||
size_t grp_size;
|
||||
u32 j, grp_num;
|
||||
group_names = devm_kcalloc(kpc->dev, func->num_group_names,
|
||||
sizeof(*group_names), GFP_KERNEL);
|
||||
if (!group_names)
|
||||
return -ENOMEM;
|
||||
|
||||
for (j = 0; j < kpc->nfuncs; j++) {
|
||||
if (!strcmp(mux->name, function[j].name))
|
||||
break;
|
||||
for (j = 0; j < kpc->npins; j++) {
|
||||
const struct pinctrl_pin_desc *pdesc = &keembay_pins[j];
|
||||
struct keembay_mux_desc *mux;
|
||||
|
||||
for (mux = pdesc->drv_data; mux->name; mux++) {
|
||||
if (!strcmp(mux->name, func->name))
|
||||
group_names[grp_idx++] = pdesc->name;
|
||||
}
|
||||
|
||||
if (j == kpc->nfuncs)
|
||||
return -EINVAL;
|
||||
|
||||
func = function + j;
|
||||
grp_num = func->num_group_names;
|
||||
grp_size = sizeof(*func->group_names);
|
||||
|
||||
if (!func->group_names) {
|
||||
func->group_names = devm_kcalloc(kpc->dev,
|
||||
grp_num,
|
||||
grp_size,
|
||||
GFP_KERNEL);
|
||||
if (!func->group_names)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
grp = func->group_names;
|
||||
while (*grp)
|
||||
grp++;
|
||||
|
||||
*grp = pdesc->name;
|
||||
mux++;
|
||||
}
|
||||
|
||||
func->group_names = group_names;
|
||||
}
|
||||
|
||||
/* Add all functions */
|
||||
for (i = 0; i < kpc->nfuncs; i++) {
|
||||
pinmux_generic_add_function(kpc->pctrl,
|
||||
function[i].name,
|
||||
function[i].group_names,
|
||||
function[i].num_group_names,
|
||||
function[i].data);
|
||||
functions[i].name,
|
||||
functions[i].group_names,
|
||||
functions[i].num_group_names,
|
||||
functions[i].data);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -1617,37 +1601,38 @@ static int keembay_build_functions(struct keembay_pinctrl *kpc)
|
|||
struct function_desc *keembay_funcs, *new_funcs;
|
||||
int i;
|
||||
|
||||
/* Allocate total number of functions */
|
||||
/*
|
||||
* Allocate maximum possible number of functions. Assume every pin
|
||||
* being part of 8 (hw maximum) globally unique muxes.
|
||||
*/
|
||||
kpc->nfuncs = 0;
|
||||
keembay_funcs = kcalloc(kpc->npins * 8, sizeof(*keembay_funcs), GFP_KERNEL);
|
||||
if (!keembay_funcs)
|
||||
return -ENOMEM;
|
||||
|
||||
/* Find total number of functions and each's properties */
|
||||
/* Setup 1 function for each unique mux */
|
||||
for (i = 0; i < kpc->npins; i++) {
|
||||
const struct pinctrl_pin_desc *pdesc = keembay_pins + i;
|
||||
struct keembay_mux_desc *mux = pdesc->drv_data;
|
||||
struct keembay_mux_desc *mux;
|
||||
|
||||
while (mux->name) {
|
||||
struct function_desc *fdesc = keembay_funcs;
|
||||
for (mux = pdesc->drv_data; mux->name; mux++) {
|
||||
struct function_desc *fdesc;
|
||||
|
||||
while (fdesc->name) {
|
||||
/* Check if we already have function for this mux */
|
||||
for (fdesc = keembay_funcs; fdesc->name; fdesc++) {
|
||||
if (!strcmp(mux->name, fdesc->name)) {
|
||||
fdesc->num_group_names++;
|
||||
break;
|
||||
}
|
||||
|
||||
fdesc++;
|
||||
}
|
||||
|
||||
/* Setup new function for this mux we didn't see before */
|
||||
if (!fdesc->name) {
|
||||
fdesc->name = mux->name;
|
||||
fdesc->num_group_names = 1;
|
||||
fdesc->data = &mux->mode;
|
||||
kpc->nfuncs++;
|
||||
}
|
||||
|
||||
mux++;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
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