watchdog: f71808e_wdt: fix F81866 bit operation
Fix error bit operation in watchdog_start()
Fixes: 14b24a88a3
("watchdog: f71808e_wdt: Add F81866 support")
Signed-off-by: Ji-Ze Hong (Peter Hong) <hpeter+linux_kernel@gmail.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
This commit is contained in:
Родитель
a3f764d2ee
Коммит
e347afa5fb
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@ -339,6 +339,7 @@ static int f71862fg_pin_configure(unsigned short ioaddr)
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static int watchdog_start(void)
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{
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int err;
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u8 tmp;
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/* Make sure we don't die as soon as the watchdog is enabled below */
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err = watchdog_keepalive();
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@ -388,19 +389,18 @@ static int watchdog_start(void)
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break;
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case f81866:
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/* Set pin 70 to WDTRST# */
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superio_clear_bit(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL,
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BIT(3) | BIT(0));
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superio_set_bit(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL,
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BIT(2));
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/*
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* GPIO1 Control Register when 27h BIT3:2 = 01 & BIT0 = 0.
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* The PIN 70(GPIO15/WDTRST) is controlled by 2Ch:
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* BIT5: 0 -> WDTRST#
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* 1 -> GPIO15
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*/
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superio_clear_bit(watchdog.sioaddr, SIO_F81866_REG_GPIO1,
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BIT(5));
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tmp = superio_inb(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL);
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tmp &= ~(BIT(3) | BIT(0));
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tmp |= BIT(2);
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superio_outb(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL, tmp);
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superio_clear_bit(watchdog.sioaddr, SIO_F81866_REG_GPIO1, 5);
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break;
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default:
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