ARM: Realview/Versatile: separate out common SP804 timer code
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
Родитель
f4b8b319bf
Коммит
e388771458
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@ -257,6 +257,7 @@ config ARCH_REALVIEW
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select GENERIC_CLOCKEVENTS
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select ARCH_WANT_OPTIONAL_GPIOLIB
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select PLAT_VERSATILE
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select ARM_TIMER_SP804
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help
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This enables support for ARM Ltd RealView boards.
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@ -271,6 +272,7 @@ config ARCH_VERSATILE
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select GENERIC_CLOCKEVENTS
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select ARCH_WANT_OPTIONAL_GPIOLIB
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select PLAT_VERSATILE
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select ARM_TIMER_SP804
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help
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This enables support for ARM Ltd Versatile board.
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@ -944,6 +946,9 @@ config PLAT_PXA
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config PLAT_VERSATILE
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bool
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config ARM_TIMER_SP804
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bool
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source arch/arm/mm/Kconfig
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config IWMMXT
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@ -25,8 +25,6 @@
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#include <linux/interrupt.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/clcd.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/io.h>
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#include <linux/smsc911x.h>
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#include <linux/ata_platform.h>
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@ -51,6 +49,7 @@
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#include <mach/clkdev.h>
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#include <mach/platform.h>
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#include <mach/irqs.h>
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#include <plat/timer-sp.h>
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#include "core.h"
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@ -645,133 +644,6 @@ void __iomem *timer1_va_base;
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void __iomem *timer2_va_base;
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void __iomem *timer3_va_base;
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/*
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* How long is the timer interval?
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*/
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#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
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#if TIMER_INTERVAL >= 0x100000
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#define TIMER_RELOAD (TIMER_INTERVAL >> 8)
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#define TIMER_DIVISOR (TIMER_CTRL_DIV256)
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#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
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#elif TIMER_INTERVAL >= 0x10000
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#define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
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#define TIMER_DIVISOR (TIMER_CTRL_DIV16)
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#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
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#else
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#define TIMER_RELOAD (TIMER_INTERVAL)
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#define TIMER_DIVISOR (TIMER_CTRL_DIV1)
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#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
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#endif
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static void timer_set_mode(enum clock_event_mode mode,
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struct clock_event_device *clk)
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{
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unsigned long ctrl;
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switch(mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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writel(TIMER_RELOAD, timer0_va_base + TIMER_LOAD);
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ctrl = TIMER_CTRL_PERIODIC;
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ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/* period set, and timer enabled in 'next_event' hook */
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ctrl = TIMER_CTRL_ONESHOT;
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ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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default:
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ctrl = 0;
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}
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writel(ctrl, timer0_va_base + TIMER_CTRL);
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}
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static int timer_set_next_event(unsigned long evt,
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struct clock_event_device *unused)
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{
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unsigned long ctrl = readl(timer0_va_base + TIMER_CTRL);
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writel(evt, timer0_va_base + TIMER_LOAD);
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writel(ctrl | TIMER_CTRL_ENABLE, timer0_va_base + TIMER_CTRL);
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return 0;
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}
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static struct clock_event_device timer0_clockevent = {
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.name = "timer0",
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.shift = 32,
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = timer_set_mode,
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.set_next_event = timer_set_next_event,
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.rating = 300,
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.cpumask = cpu_all_mask,
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};
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static void __init realview_clockevents_init(unsigned int timer_irq)
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{
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timer0_clockevent.irq = timer_irq;
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timer0_clockevent.mult =
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div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
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timer0_clockevent.max_delta_ns =
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clockevent_delta2ns(0xffffffff, &timer0_clockevent);
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timer0_clockevent.min_delta_ns =
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clockevent_delta2ns(0xf, &timer0_clockevent);
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clockevents_register_device(&timer0_clockevent);
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}
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/*
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* IRQ handler for the timer
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*/
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static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = &timer0_clockevent;
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/* clear the interrupt */
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writel(1, timer0_va_base + TIMER_INTCLR);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction realview_timer_irq = {
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.name = "RealView Timer Tick",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = realview_timer_interrupt,
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};
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static cycle_t realview_get_cycles(struct clocksource *cs)
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{
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return ~readl(timer3_va_base + TIMER_VALUE);
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}
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static struct clocksource clocksource_realview = {
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.name = "timer3",
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.rating = 200,
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.read = realview_get_cycles,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = 20,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static void __init realview_clocksource_init(void)
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{
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/* setup timer 0 as free-running clocksource */
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writel(0, timer3_va_base + TIMER_CTRL);
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writel(0xffffffff, timer3_va_base + TIMER_LOAD);
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writel(0xffffffff, timer3_va_base + TIMER_VALUE);
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writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
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timer3_va_base + TIMER_CTRL);
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clocksource_realview.mult =
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clocksource_khz2mult(1000, clocksource_realview.shift);
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clocksource_register(&clocksource_realview);
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}
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/*
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* Set up the clock source and clock events devices
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*/
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@ -799,13 +671,8 @@ void __init realview_timer_init(unsigned int timer_irq)
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writel(0, timer2_va_base + TIMER_CTRL);
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writel(0, timer3_va_base + TIMER_CTRL);
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/*
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* Make irqs happen for the system timer
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*/
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setup_irq(timer_irq, &realview_timer_irq);
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realview_clocksource_init();
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realview_clockevents_init(timer_irq);
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sp804_clocksource_init(timer3_va_base);
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sp804_clockevents_init(timer0_va_base, timer_irq);
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}
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/*
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@ -28,8 +28,6 @@
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#include <linux/amba/clcd.h>
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#include <linux/amba/pl061.h>
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#include <linux/amba/mmci.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/cnt32_to_63.h>
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#include <linux/io.h>
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@ -50,6 +48,7 @@
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#include <mach/clkdev.h>
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#include <mach/hardware.h>
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#include <mach/platform.h>
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#include <plat/timer-sp.h>
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#include "core.h"
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@ -877,120 +876,6 @@ void __init versatile_init(void)
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#define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
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#define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
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#define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
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#define VA_IC_BASE __io_address(VERSATILE_VIC_BASE)
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/*
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* How long is the timer interval?
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*/
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#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
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#if TIMER_INTERVAL >= 0x100000
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#define TIMER_RELOAD (TIMER_INTERVAL >> 8)
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#define TIMER_DIVISOR (TIMER_CTRL_DIV256)
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#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
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#elif TIMER_INTERVAL >= 0x10000
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#define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
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#define TIMER_DIVISOR (TIMER_CTRL_DIV16)
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#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
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#else
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#define TIMER_RELOAD (TIMER_INTERVAL)
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#define TIMER_DIVISOR (TIMER_CTRL_DIV1)
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#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
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#endif
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static void timer_set_mode(enum clock_event_mode mode,
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struct clock_event_device *clk)
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{
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unsigned long ctrl;
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switch(mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
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ctrl = TIMER_CTRL_PERIODIC;
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ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/* period set, and timer enabled in 'next_event' hook */
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ctrl = TIMER_CTRL_ONESHOT;
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ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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default:
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ctrl = 0;
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}
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writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
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}
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static int timer_set_next_event(unsigned long evt,
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struct clock_event_device *unused)
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{
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unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
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writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
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writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
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return 0;
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}
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static struct clock_event_device timer0_clockevent = {
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.name = "timer0",
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.shift = 32,
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = timer_set_mode,
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.set_next_event = timer_set_next_event,
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};
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/*
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* IRQ handler for the timer
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*/
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static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = &timer0_clockevent;
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writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction versatile_timer_irq = {
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.name = "Versatile Timer Tick",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = versatile_timer_interrupt,
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};
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static cycle_t versatile_get_cycles(struct clocksource *cs)
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{
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return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
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}
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static struct clocksource clocksource_versatile = {
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.name = "timer3",
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.rating = 200,
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.read = versatile_get_cycles,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = 20,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static int __init versatile_clocksource_init(void)
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{
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/* setup timer3 as free-running clocksource */
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writel(0, TIMER3_VA_BASE + TIMER_CTRL);
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writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
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writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
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writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
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TIMER3_VA_BASE + TIMER_CTRL);
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clocksource_versatile.mult =
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clocksource_khz2mult(1000, clocksource_versatile.shift);
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clocksource_register(&clocksource_versatile);
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return 0;
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}
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/*
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* Set up timer interrupt, and return the current time in seconds.
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@ -1019,22 +904,8 @@ static void __init versatile_timer_init(void)
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writel(0, TIMER2_VA_BASE + TIMER_CTRL);
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writel(0, TIMER3_VA_BASE + TIMER_CTRL);
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/*
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* Make irqs happen for the system timer
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*/
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setup_irq(IRQ_TIMERINT0_1, &versatile_timer_irq);
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versatile_clocksource_init();
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timer0_clockevent.mult =
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div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
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timer0_clockevent.max_delta_ns =
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clockevent_delta2ns(0xffffffff, &timer0_clockevent);
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timer0_clockevent.min_delta_ns =
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clockevent_delta2ns(0xf, &timer0_clockevent);
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timer0_clockevent.cpumask = cpumask_of(0);
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clockevents_register_device(&timer0_clockevent);
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sp804_clocksource_init(TIMER3_VA_BASE);
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sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1);
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}
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struct sys_timer versatile_timer = {
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@ -1 +1,2 @@
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obj-y := clock.o
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obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o
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@ -0,0 +1,2 @@
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void sp804_clocksource_init(void __iomem *);
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void sp804_clockevents_init(void __iomem *, unsigned int);
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@ -0,0 +1,168 @@
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/*
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* linux/arch/arm/plat-versatile/timer-sp.c
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*
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* Copyright (C) 1999 - 2003 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; either version 2 of the License, or
|
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/hardware/arm_timer.h>
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#include <mach/platform.h>
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#include <plat/timer-sp.h>
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/*
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* How long is the timer interval?
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*/
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#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
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#if TIMER_INTERVAL >= 0x100000
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#define TIMER_RELOAD (TIMER_INTERVAL >> 8)
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#define TIMER_DIVISOR (TIMER_CTRL_DIV256)
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#elif TIMER_INTERVAL >= 0x10000
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#define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
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#define TIMER_DIVISOR (TIMER_CTRL_DIV16)
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#else
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#define TIMER_RELOAD (TIMER_INTERVAL)
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#define TIMER_DIVISOR (TIMER_CTRL_DIV1)
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#endif
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static void __iomem *clksrc_base;
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static cycle_t sp804_read(struct clocksource *cs)
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{
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return ~readl(clksrc_base + TIMER_VALUE);
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}
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static struct clocksource clocksource_sp804 = {
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.name = "timer3",
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.rating = 200,
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.read = sp804_read,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = 20,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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void __init sp804_clocksource_init(void __iomem *base)
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{
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struct clocksource *cs = &clocksource_sp804;
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||||
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||||
clksrc_base = base;
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||||
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||||
/* setup timer 0 as free-running clocksource */
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writel(0, clksrc_base + TIMER_CTRL);
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||||
writel(0xffffffff, clksrc_base + TIMER_LOAD);
|
||||
writel(0xffffffff, clksrc_base + TIMER_VALUE);
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||||
writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
|
||||
clksrc_base + TIMER_CTRL);
|
||||
|
||||
cs->mult = clocksource_khz2mult(1000, cs->shift);
|
||||
clocksource_register(cs);
|
||||
}
|
||||
|
||||
|
||||
static void __iomem *clkevt_base;
|
||||
|
||||
/*
|
||||
* IRQ handler for the timer
|
||||
*/
|
||||
static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
struct clock_event_device *evt = dev_id;
|
||||
|
||||
/* clear the interrupt */
|
||||
writel(1, clkevt_base + TIMER_INTCLR);
|
||||
|
||||
evt->event_handler(evt);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void sp804_set_mode(enum clock_event_mode mode,
|
||||
struct clock_event_device *evt)
|
||||
{
|
||||
unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE;
|
||||
|
||||
writel(ctrl, clkevt_base + TIMER_CTRL);
|
||||
|
||||
switch (mode) {
|
||||
case CLOCK_EVT_MODE_PERIODIC:
|
||||
writel(TIMER_RELOAD, clkevt_base + TIMER_LOAD);
|
||||
ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
|
||||
break;
|
||||
|
||||
case CLOCK_EVT_MODE_ONESHOT:
|
||||
/* period set, and timer enabled in 'next_event' hook */
|
||||
ctrl |= TIMER_CTRL_ONESHOT;
|
||||
break;
|
||||
|
||||
case CLOCK_EVT_MODE_UNUSED:
|
||||
case CLOCK_EVT_MODE_SHUTDOWN:
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
writel(ctrl, clkevt_base + TIMER_CTRL);
|
||||
}
|
||||
|
||||
static int sp804_set_next_event(unsigned long next,
|
||||
struct clock_event_device *evt)
|
||||
{
|
||||
unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
|
||||
|
||||
writel(next, clkevt_base + TIMER_LOAD);
|
||||
writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct clock_event_device sp804_clockevent = {
|
||||
.name = "timer0",
|
||||
.shift = 32,
|
||||
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
|
||||
.set_mode = sp804_set_mode,
|
||||
.set_next_event = sp804_set_next_event,
|
||||
.rating = 300,
|
||||
.cpumask = cpu_all_mask,
|
||||
};
|
||||
|
||||
static struct irqaction sp804_timer_irq = {
|
||||
.name = "timer",
|
||||
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
|
||||
.handler = sp804_timer_interrupt,
|
||||
.dev_id = &sp804_clockevent,
|
||||
};
|
||||
|
||||
void __init sp804_clockevents_init(void __iomem *base, unsigned int timer_irq)
|
||||
{
|
||||
struct clock_event_device *evt = &sp804_clockevent;
|
||||
|
||||
clkevt_base = base;
|
||||
|
||||
evt->irq = timer_irq;
|
||||
evt->mult = div_sc(1000000, NSEC_PER_SEC, evt->shift);
|
||||
evt->max_delta_ns = clockevent_delta2ns(0xffffffff, evt);
|
||||
evt->min_delta_ns = clockevent_delta2ns(0xf, evt);
|
||||
|
||||
setup_irq(timer_irq, &sp804_timer_irq);
|
||||
clockevents_register_device(evt);
|
||||
}
|
||||
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