i3c: dw: Add support for in-band interrupts
This change adds support for receiving and dequeueing i3c IBIs. By setting struct dw_i3c_master->ibi_capable before probe, a platform implementation can select the IBI-enabled version of the i3c_master_ops, enabling the global IBI infrastrcture for that controller. Signed-off-by: Jeremy Kerr <jk@codeconstruct.com.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/79daeefd7ccb7c935d0c159149df21a6c9a73ffa.1680161823.git.jk@codeconstruct.com.au Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
This commit is contained in:
Jeremy Kerr
Alexandre Belloni
Родитель
e2d43101f6
Коммит
e389b1d72a
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@ -76,7 +76,22 @@
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#define RX_TX_DATA_PORT 0x14
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#define IBI_QUEUE_STATUS 0x18
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#define IBI_QUEUE_STATUS_IBI_ID(x) (((x) & GENMASK(15, 8)) >> 8)
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#define IBI_QUEUE_STATUS_DATA_LEN(x) ((x) & GENMASK(7, 0))
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#define IBI_QUEUE_IBI_ADDR(x) (IBI_QUEUE_STATUS_IBI_ID(x) >> 1)
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#define IBI_QUEUE_IBI_RNW(x) (IBI_QUEUE_STATUS_IBI_ID(x) & BIT(0))
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#define IBI_TYPE_MR(x) \
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((IBI_QUEUE_IBI_ADDR(x) != I3C_HOT_JOIN_ADDR) && !IBI_QUEUE_IBI_RNW(x))
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#define IBI_TYPE_HJ(x) \
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((IBI_QUEUE_IBI_ADDR(x) == I3C_HOT_JOIN_ADDR) && !IBI_QUEUE_IBI_RNW(x))
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#define IBI_TYPE_SIRQ(x) \
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((IBI_QUEUE_IBI_ADDR(x) != I3C_HOT_JOIN_ADDR) && IBI_QUEUE_IBI_RNW(x))
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#define QUEUE_THLD_CTRL 0x1c
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#define QUEUE_THLD_CTRL_IBI_STAT_MASK GENMASK(31, 24)
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#define QUEUE_THLD_CTRL_IBI_STAT(x) (((x) - 1) << 24)
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#define QUEUE_THLD_CTRL_IBI_DATA_MASK GENMASK(20, 16)
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#define QUEUE_THLD_CTRL_IBI_DATA(x) ((x) << 16)
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#define QUEUE_THLD_CTRL_RESP_BUF_MASK GENMASK(15, 8)
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#define QUEUE_THLD_CTRL_RESP_BUF(x) (((x) - 1) << 8)
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@ -186,6 +201,8 @@
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#define EXTENDED_CAPABILITY 0xe8
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#define SLAVE_CONFIG 0xec
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#define DEV_ADDR_TABLE_IBI_MDB BIT(12)
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#define DEV_ADDR_TABLE_SIR_REJECT BIT(13)
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#define DEV_ADDR_TABLE_LEGACY_I2C_DEV BIT(31)
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#define DEV_ADDR_TABLE_DYNAMIC_ADDR(x) (((x) << 16) & GENMASK(23, 16))
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#define DEV_ADDR_TABLE_STATIC_ADDR(x) ((x) & GENMASK(6, 0))
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@ -221,6 +238,7 @@ struct dw_i3c_xfer {
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struct dw_i3c_i2c_dev_data {
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u8 index;
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struct i3c_generic_ibi_pool *ibi_pool;
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};
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static u8 even_parity(u8 p)
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@ -336,6 +354,12 @@ static void dw_i3c_master_read_rx_fifo(struct dw_i3c_master *master,
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return dw_i3c_master_read_fifo(master, RX_TX_DATA_PORT, bytes, nbytes);
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}
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static void dw_i3c_master_read_ibi_fifo(struct dw_i3c_master *master,
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u8 *bytes, int nbytes)
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{
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return dw_i3c_master_read_fifo(master, IBI_QUEUE_STATUS, bytes, nbytes);
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}
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static struct dw_i3c_xfer *
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dw_i3c_master_alloc_xfer(struct dw_i3c_master *master, unsigned int ncmds)
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{
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@ -605,7 +629,11 @@ static int dw_i3c_master_bus_init(struct i3c_master_controller *m)
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}
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thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL);
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thld_ctrl &= ~QUEUE_THLD_CTRL_RESP_BUF_MASK;
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thld_ctrl &= ~(QUEUE_THLD_CTRL_RESP_BUF_MASK |
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QUEUE_THLD_CTRL_IBI_STAT_MASK |
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QUEUE_THLD_CTRL_IBI_STAT_MASK);
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thld_ctrl |= QUEUE_THLD_CTRL_IBI_STAT(1) |
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QUEUE_THLD_CTRL_IBI_DATA(31);
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writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL);
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thld_ctrl = readl(master->regs + DATA_BUFFER_THLD_CTRL);
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@ -1074,6 +1102,226 @@ static void dw_i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev)
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kfree(data);
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}
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static int dw_i3c_master_request_ibi(struct i3c_dev_desc *dev,
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const struct i3c_ibi_setup *req)
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{
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struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
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struct i3c_master_controller *m = i3c_dev_get_master(dev);
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struct dw_i3c_master *master = to_dw_i3c_master(m);
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unsigned long flags;
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data->ibi_pool = i3c_generic_ibi_alloc_pool(dev, req);
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if (IS_ERR(data->ibi_pool))
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return PTR_ERR(data->ibi_pool);
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spin_lock_irqsave(&master->devs_lock, flags);
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master->devs[data->index].ibi_dev = dev;
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spin_unlock_irqrestore(&master->devs_lock, flags);
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return 0;
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}
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static void dw_i3c_master_free_ibi(struct i3c_dev_desc *dev)
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{
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struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
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struct i3c_master_controller *m = i3c_dev_get_master(dev);
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struct dw_i3c_master *master = to_dw_i3c_master(m);
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unsigned long flags;
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spin_lock_irqsave(&master->devs_lock, flags);
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master->devs[data->index].ibi_dev = NULL;
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spin_unlock_irqrestore(&master->devs_lock, flags);
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i3c_generic_ibi_free_pool(data->ibi_pool);
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data->ibi_pool = NULL;
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}
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static void dw_i3c_master_set_sir_enabled(struct dw_i3c_master *master,
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struct i3c_dev_desc *dev,
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u8 idx, bool enable)
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{
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unsigned long flags;
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u32 dat_entry, reg;
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bool global;
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dat_entry = DEV_ADDR_TABLE_LOC(master->datstartaddr, idx);
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spin_lock_irqsave(&master->devs_lock, flags);
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reg = readl(master->regs + dat_entry);
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if (enable) {
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reg &= ~DEV_ADDR_TABLE_SIR_REJECT;
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if (dev->info.bcr & I3C_BCR_IBI_PAYLOAD)
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reg |= DEV_ADDR_TABLE_IBI_MDB;
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} else {
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reg |= DEV_ADDR_TABLE_SIR_REJECT;
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}
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writel(reg, master->regs + dat_entry);
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reg = readl(master->regs + IBI_SIR_REQ_REJECT);
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if (enable) {
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global = reg == 0xffffffff;
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reg &= ~BIT(idx);
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} else {
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global = reg == 0;
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reg |= BIT(idx);
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}
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writel(reg, master->regs + IBI_SIR_REQ_REJECT);
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if (global) {
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reg = readl(master->regs + INTR_STATUS_EN);
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reg &= ~INTR_IBI_THLD_STAT;
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if (enable)
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reg |= INTR_IBI_THLD_STAT;
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writel(reg, master->regs + INTR_STATUS_EN);
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reg = readl(master->regs + INTR_SIGNAL_EN);
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reg &= ~INTR_IBI_THLD_STAT;
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if (enable)
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reg |= INTR_IBI_THLD_STAT;
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writel(reg, master->regs + INTR_SIGNAL_EN);
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}
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spin_unlock_irqrestore(&master->devs_lock, flags);
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}
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static int dw_i3c_master_enable_ibi(struct i3c_dev_desc *dev)
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{
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struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
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struct i3c_master_controller *m = i3c_dev_get_master(dev);
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struct dw_i3c_master *master = to_dw_i3c_master(m);
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int rc;
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dw_i3c_master_set_sir_enabled(master, dev, data->index, true);
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rc = i3c_master_enec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR);
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if (rc)
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dw_i3c_master_set_sir_enabled(master, dev, data->index, false);
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return rc;
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}
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static int dw_i3c_master_disable_ibi(struct i3c_dev_desc *dev)
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{
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struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
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struct i3c_master_controller *m = i3c_dev_get_master(dev);
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struct dw_i3c_master *master = to_dw_i3c_master(m);
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int rc;
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rc = i3c_master_disec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR);
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if (rc)
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return rc;
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dw_i3c_master_set_sir_enabled(master, dev, data->index, false);
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return 0;
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}
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static void dw_i3c_master_recycle_ibi_slot(struct i3c_dev_desc *dev,
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struct i3c_ibi_slot *slot)
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{
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struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
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i3c_generic_ibi_recycle_slot(data->ibi_pool, slot);
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}
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static void dw_i3c_master_drain_ibi_queue(struct dw_i3c_master *master,
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int len)
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{
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int i;
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for (i = 0; i < DIV_ROUND_UP(len, 4); i++)
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readl(master->regs + IBI_QUEUE_STATUS);
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}
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static void dw_i3c_master_handle_ibi_sir(struct dw_i3c_master *master,
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u32 status)
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{
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struct dw_i3c_i2c_dev_data *data;
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struct i3c_ibi_slot *slot;
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struct i3c_dev_desc *dev;
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unsigned long flags;
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u8 addr, len;
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int idx;
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addr = IBI_QUEUE_IBI_ADDR(status);
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len = IBI_QUEUE_STATUS_DATA_LEN(status);
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spin_lock_irqsave(&master->devs_lock, flags);
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idx = dw_i3c_master_get_addr_pos(master, addr);
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if (idx < 0) {
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dev_dbg_ratelimited(&master->base.dev,
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"IBI from unknown addr 0x%x\n", addr);
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goto err_drain;
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}
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dev = master->devs[idx].ibi_dev;
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if (!dev || !dev->ibi) {
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dev_dbg_ratelimited(&master->base.dev,
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"IBI from non-requested dev idx %d\n", idx);
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goto err_drain;
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}
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data = i3c_dev_get_master_data(dev);
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slot = i3c_generic_ibi_get_free_slot(data->ibi_pool);
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if (!slot) {
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dev_dbg_ratelimited(&master->base.dev,
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"No IBI slots available\n");
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goto err_drain;
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}
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if (dev->ibi->max_payload_len < len) {
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dev_dbg_ratelimited(&master->base.dev,
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"IBI payload len %d greater than max %d\n",
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len, dev->ibi->max_payload_len);
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goto err_drain;
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}
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if (len) {
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dw_i3c_master_read_ibi_fifo(master, slot->data, len);
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slot->len = len;
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}
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i3c_master_queue_ibi(dev, slot);
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spin_unlock_irqrestore(&master->devs_lock, flags);
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return;
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err_drain:
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dw_i3c_master_drain_ibi_queue(master, len);
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spin_unlock_irqrestore(&master->devs_lock, flags);
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}
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/* "ibis": referring to In-Band Interrupts, and not
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* https://en.wikipedia.org/wiki/Australian_white_ibis. The latter should
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* not be handled.
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*/
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static void dw_i3c_master_irq_handle_ibis(struct dw_i3c_master *master)
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{
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unsigned int i, len, n_ibis;
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u32 reg;
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reg = readl(master->regs + QUEUE_STATUS_LEVEL);
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n_ibis = QUEUE_STATUS_IBI_STATUS_CNT(reg);
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if (!n_ibis)
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return;
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for (i = 0; i < n_ibis; i++) {
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reg = readl(master->regs + IBI_QUEUE_STATUS);
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if (IBI_TYPE_SIRQ(reg)) {
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dw_i3c_master_handle_ibi_sir(master, reg);
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} else {
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len = IBI_QUEUE_STATUS_DATA_LEN(reg);
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dev_info(&master->base.dev,
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"unsupported IBI type 0x%lx len %d\n",
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IBI_QUEUE_STATUS_IBI_ID(reg), len);
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dw_i3c_master_drain_ibi_queue(master, len);
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}
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}
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}
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static irqreturn_t dw_i3c_master_irq_handler(int irq, void *dev_id)
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{
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struct dw_i3c_master *master = dev_id;
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@ -1092,6 +1340,9 @@ static irqreturn_t dw_i3c_master_irq_handler(int irq, void *dev_id)
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writel(INTR_TRANSFER_ERR_STAT, master->regs + INTR_STATUS);
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spin_unlock(&master->xferqueue.lock);
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if (status & INTR_IBI_THLD_STAT)
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dw_i3c_master_irq_handle_ibis(master);
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return IRQ_HANDLED;
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}
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@ -1110,6 +1361,26 @@ static const struct i3c_master_controller_ops dw_mipi_i3c_ops = {
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.i2c_xfers = dw_i3c_master_i2c_xfers,
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};
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static const struct i3c_master_controller_ops dw_mipi_i3c_ibi_ops = {
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.bus_init = dw_i3c_master_bus_init,
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.bus_cleanup = dw_i3c_master_bus_cleanup,
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.attach_i3c_dev = dw_i3c_master_attach_i3c_dev,
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.reattach_i3c_dev = dw_i3c_master_reattach_i3c_dev,
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.detach_i3c_dev = dw_i3c_master_detach_i3c_dev,
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.do_daa = dw_i3c_master_daa,
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.supports_ccc_cmd = dw_i3c_master_supports_ccc_cmd,
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.send_ccc_cmd = dw_i3c_master_send_ccc_cmd,
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.priv_xfers = dw_i3c_master_priv_xfers,
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.attach_i2c_dev = dw_i3c_master_attach_i2c_dev,
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.detach_i2c_dev = dw_i3c_master_detach_i2c_dev,
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.i2c_xfers = dw_i3c_master_i2c_xfers,
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.request_ibi = dw_i3c_master_request_ibi,
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.free_ibi = dw_i3c_master_free_ibi,
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.enable_ibi = dw_i3c_master_enable_ibi,
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.disable_ibi = dw_i3c_master_disable_ibi,
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.recycle_ibi_slot = dw_i3c_master_recycle_ibi_slot,
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};
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/* default platform ops implementations */
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static int dw_i3c_platform_init_nop(struct dw_i3c_master *i3c)
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{
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@ -1123,6 +1394,7 @@ static const struct dw_i3c_platform_ops dw_i3c_platform_ops_default = {
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int dw_i3c_common_probe(struct dw_i3c_master *master,
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struct platform_device *pdev)
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{
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const struct i3c_master_controller_ops *ops;
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int ret, irq;
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if (!master->platform_ops)
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@ -1172,8 +1444,11 @@ int dw_i3c_common_probe(struct dw_i3c_master *master,
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master->maxdevs = ret >> 16;
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master->free_pos = GENMASK(master->maxdevs - 1, 0);
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ret = i3c_master_register(&master->base, &pdev->dev,
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&dw_mipi_i3c_ops, false);
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ops = &dw_mipi_i3c_ops;
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if (master->ibi_capable)
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ops = &dw_mipi_i3c_ibi_ops;
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ret = i3c_master_register(&master->base, &pdev->dev, ops, false);
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if (ret)
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goto err_assert_rst;
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@ -19,6 +19,7 @@ struct dw_i3c_master_caps {
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struct dw_i3c_dat_entry {
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u8 addr;
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struct i3c_dev_desc *ibi_dev;
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};
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struct dw_i3c_master {
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@ -37,12 +38,22 @@ struct dw_i3c_master {
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struct clk *core_clk;
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char version[5];
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char type[5];
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bool ibi_capable;
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/*
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* Per-device hardware data, used to manage the device address table
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* (DAT)
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*
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* Locking: the devs array may be referenced in IRQ context while
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* processing an IBI. However, IBIs (for a specific device, which
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* implies a specific DAT entry) can only happen while interrupts are
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* requested for that device, which is serialised against other
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* insertions/removals from the array by the global i3c infrastructure.
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* So, devs_lock protects against concurrent updates to devs->ibi_dev
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* between request_ibi/free_ibi and the IBI irq event.
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*/
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struct dw_i3c_dat_entry devs[DW_I3C_MAX_DEVS];
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spinlock_t devs_lock;
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/* platform-specific data */
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const struct dw_i3c_platform_ops *platform_ops;
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