Merge remote-tracking branch 'asoc/topic/tas2552' into asoc-next
This commit is contained in:
Mark Brown
Коммит
e39f6bc7de
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@ -14,6 +14,12 @@ Required properties:
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Optional properties:
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- enable-gpio - gpio pin to enable/disable the device
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tas2552 can receive it's reference clock via MCLK, BCLK, IVCLKIN pin or use the
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internal 1.8MHz. This CLKIN is used by the PLL. In addition to PLL, the PDM
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reference clock is also selectable: PLL, IVCLKIN, BCLK or MCLK.
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For system integration the dt-bindings/sound/tas2552.h header file provides
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defined values to selct and configure the PLL and PDM reference clocks.
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Example:
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tas2552: tas2552@41 {
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@ -45,7 +45,7 @@ static struct reg_default tas2552_reg_defs[] = {
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{TAS2552_OUTPUT_DATA, 0xc0},
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{TAS2552_PDM_CFG, 0x01},
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{TAS2552_PGA_GAIN, 0x00},
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{TAS2552_BOOST_PT_CTRL, 0x0f},
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{TAS2552_BOOST_APT_CTRL, 0x0f},
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{TAS2552_RESERVED_0D, 0xbe},
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{TAS2552_LIMIT_RATE_HYS, 0x08},
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{TAS2552_CFG_2, 0xef},
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@ -77,7 +77,9 @@ struct tas2552_data {
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struct gpio_desc *enable_gpio;
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unsigned char regs[TAS2552_VBAT_DATA];
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unsigned int pll_clkin;
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int pll_clk_id;
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unsigned int pdm_clk;
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int pdm_clk_id;
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unsigned int dai_fmt;
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unsigned int tdm_delay;
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@ -143,31 +145,105 @@ static const struct snd_soc_dapm_route tas2552_audio_map[] = {
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};
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#ifdef CONFIG_PM
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static void tas2552_sw_shutdown(struct tas2552_data *tas_data, int sw_shutdown)
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static void tas2552_sw_shutdown(struct tas2552_data *tas2552, int sw_shutdown)
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{
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u8 cfg1_reg = 0;
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if (!tas_data->codec)
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if (!tas2552->codec)
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return;
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if (sw_shutdown)
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cfg1_reg = TAS2552_SWS;
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snd_soc_update_bits(tas_data->codec, TAS2552_CFG_1, TAS2552_SWS,
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snd_soc_update_bits(tas2552->codec, TAS2552_CFG_1, TAS2552_SWS,
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cfg1_reg);
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}
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#endif
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static int tas2552_setup_pll(struct snd_soc_codec *codec,
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struct snd_pcm_hw_params *params)
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{
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struct tas2552_data *tas2552 = dev_get_drvdata(codec->dev);
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bool bypass_pll = false;
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unsigned int pll_clk = params_rate(params) * 512;
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unsigned int pll_clkin = tas2552->pll_clkin;
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u8 pll_enable;
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if (!pll_clkin) {
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if (tas2552->pll_clk_id != TAS2552_PLL_CLKIN_BCLK)
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return -EINVAL;
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pll_clkin = snd_soc_params_to_bclk(params);
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pll_clkin += tas2552->tdm_delay;
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}
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pll_enable = snd_soc_read(codec, TAS2552_CFG_2) & TAS2552_PLL_ENABLE;
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snd_soc_update_bits(codec, TAS2552_CFG_2, TAS2552_PLL_ENABLE, 0);
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if (pll_clkin == pll_clk)
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bypass_pll = true;
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if (bypass_pll) {
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/* By pass the PLL configuration */
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snd_soc_update_bits(codec, TAS2552_PLL_CTRL_2,
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TAS2552_PLL_BYPASS, TAS2552_PLL_BYPASS);
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} else {
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/* Fill in the PLL control registers for J & D
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* pll_clk = (.5 * pll_clkin * J.D) / 2^p
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* Need to fill in J and D here based on incoming freq
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*/
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unsigned int d;
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u8 j;
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u8 pll_sel = (tas2552->pll_clk_id << 3) & TAS2552_PLL_SRC_MASK;
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u8 p = snd_soc_read(codec, TAS2552_PLL_CTRL_1);
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p = (p >> 7);
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recalc:
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j = (pll_clk * 2 * (1 << p)) / pll_clkin;
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d = (pll_clk * 2 * (1 << p)) % pll_clkin;
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d /= (pll_clkin / 10000);
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if (d && (pll_clkin < 512000 || pll_clkin > 9200000)) {
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if (tas2552->pll_clk_id == TAS2552_PLL_CLKIN_BCLK) {
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pll_clkin = 1800000;
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pll_sel = (TAS2552_PLL_CLKIN_1_8_FIXED << 3) &
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TAS2552_PLL_SRC_MASK;
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} else {
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pll_clkin = snd_soc_params_to_bclk(params);
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pll_clkin += tas2552->tdm_delay;
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pll_sel = (TAS2552_PLL_CLKIN_BCLK << 3) &
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TAS2552_PLL_SRC_MASK;
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}
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goto recalc;
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}
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snd_soc_update_bits(codec, TAS2552_CFG_1, TAS2552_PLL_SRC_MASK,
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pll_sel);
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snd_soc_update_bits(codec, TAS2552_PLL_CTRL_1,
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TAS2552_PLL_J_MASK, j);
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/* Will clear the PLL_BYPASS bit */
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snd_soc_write(codec, TAS2552_PLL_CTRL_2,
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TAS2552_PLL_D_UPPER(d));
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snd_soc_write(codec, TAS2552_PLL_CTRL_3,
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TAS2552_PLL_D_LOWER(d));
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}
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/* Restore PLL status */
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snd_soc_update_bits(codec, TAS2552_CFG_2, TAS2552_PLL_ENABLE,
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pll_enable);
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return 0;
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}
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static int tas2552_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_codec *codec = dai->codec;
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struct tas2552_data *tas2552 = dev_get_drvdata(codec->dev);
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int sample_rate, pll_clk;
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int d;
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int cpf;
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u8 p, j;
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u8 ser_ctrl1_reg, wclk_rate;
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switch (params_width(params)) {
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@ -245,49 +321,7 @@ static int tas2552_hw_params(struct snd_pcm_substream *substream,
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snd_soc_update_bits(codec, TAS2552_CFG_3, TAS2552_WCLK_FREQ_MASK,
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wclk_rate);
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if (!tas2552->pll_clkin)
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return -EINVAL;
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snd_soc_update_bits(codec, TAS2552_CFG_2, TAS2552_PLL_ENABLE, 0);
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if (tas2552->pll_clkin == TAS2552_245MHZ_CLK ||
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tas2552->pll_clkin == TAS2552_225MHZ_CLK) {
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/* By pass the PLL configuration */
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snd_soc_update_bits(codec, TAS2552_PLL_CTRL_2,
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TAS2552_PLL_BYPASS_MASK,
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TAS2552_PLL_BYPASS);
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} else {
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/* Fill in the PLL control registers for J & D
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* PLL_CLK = (.5 * freq * J.D) / 2^p
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* Need to fill in J and D here based on incoming freq
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*/
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p = snd_soc_read(codec, TAS2552_PLL_CTRL_1);
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p = (p >> 7);
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sample_rate = params_rate(params);
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if (sample_rate == 48000)
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pll_clk = TAS2552_245MHZ_CLK;
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else if (sample_rate == 44100)
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pll_clk = TAS2552_225MHZ_CLK;
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else {
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dev_vdbg(codec->dev, "Substream sample rate is not found %i\n",
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params_rate(params));
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return -EINVAL;
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}
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j = (pll_clk * 2 * (1 << p)) / tas2552->pll_clkin;
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d = (pll_clk * 2 * (1 << p)) % tas2552->pll_clkin;
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snd_soc_update_bits(codec, TAS2552_PLL_CTRL_1,
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TAS2552_PLL_J_MASK, j);
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snd_soc_write(codec, TAS2552_PLL_CTRL_2,
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(d >> 7) & TAS2552_PLL_D_UPPER_MASK);
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snd_soc_write(codec, TAS2552_PLL_CTRL_3,
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d & TAS2552_PLL_D_LOWER_MASK);
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}
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return 0;
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return tas2552_setup_pll(codec, params);
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}
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#define TAS2552_DAI_FMT_MASK (TAS2552_BCLKDIR | \
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@ -370,12 +404,21 @@ static int tas2552_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
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switch (clk_id) {
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case TAS2552_PLL_CLKIN_MCLK:
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case TAS2552_PLL_CLKIN_BCLK:
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case TAS2552_PLL_CLKIN_IVCLKIN:
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if (freq < 512000 || freq > 24576000) {
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/* out of range PLL_CLKIN, fall back to use BCLK */
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dev_warn(codec->dev, "Out of range PLL_CLKIN: %u\n",
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freq);
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clk_id = TAS2552_PLL_CLKIN_BCLK;
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freq = 0;
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}
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/* fall through */
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case TAS2552_PLL_CLKIN_BCLK:
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case TAS2552_PLL_CLKIN_1_8_FIXED:
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mask = TAS2552_PLL_SRC_MASK;
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val = (clk_id << 3) & mask; /* bit 4:5 in the register */
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reg = TAS2552_CFG_1;
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tas2552->pll_clk_id = clk_id;
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tas2552->pll_clkin = freq;
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break;
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case TAS2552_PDM_CLK_PLL:
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@ -385,6 +428,7 @@ static int tas2552_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
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mask = TAS2552_PDM_CLK_SEL_MASK;
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val = (clk_id >> 1) & mask; /* bit 0:1 in the register */
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reg = TAS2552_PDM_CFG;
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tas2552->pdm_clk_id = clk_id;
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tas2552->pdm_clk = freq;
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break;
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default:
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@ -509,9 +553,20 @@ static struct snd_soc_dai_driver tas2552_dai[] = {
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*/
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static DECLARE_TLV_DB_SCALE(dac_tlv, -7, 100, 0);
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static const char * const tas2552_din_source_select[] = {
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"Muted",
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"Left",
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"Right",
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"Left + Right average",
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};
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static SOC_ENUM_SINGLE_DECL(tas2552_din_source_enum,
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TAS2552_CFG_3, 3,
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tas2552_din_source_select);
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static const struct snd_kcontrol_new tas2552_snd_controls[] = {
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SOC_SINGLE_TLV("Speaker Driver Playback Volume",
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TAS2552_PGA_GAIN, 0, 0x1f, 0, dac_tlv),
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SOC_ENUM("DIN source", tas2552_din_source_enum),
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};
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static int tas2552_codec_probe(struct snd_soc_codec *codec)
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@ -543,13 +598,14 @@ static int tas2552_codec_probe(struct snd_soc_codec *codec)
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snd_soc_update_bits(codec, TAS2552_CFG_1, TAS2552_MUTE, TAS2552_MUTE);
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snd_soc_write(codec, TAS2552_CFG_3, TAS2552_I2S_OUT_SEL |
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TAS2552_DIN_SRC_SEL_AVG_L_R);
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snd_soc_write(codec, TAS2552_DOUT, TAS2552_PDM_DATA_I);
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snd_soc_write(codec, TAS2552_OUTPUT_DATA, TAS2552_PDM_DATA_V_I | 0x8);
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snd_soc_write(codec, TAS2552_BOOST_PT_CTRL, TAS2552_APT_DELAY_200 |
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TAS2552_APT_THRESH_2_1_7);
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snd_soc_write(codec, TAS2552_OUTPUT_DATA,
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TAS2552_PDM_DATA_SEL_V_I |
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TAS2552_R_DATA_OUT(TAS2552_DATA_OUT_V_DATA));
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snd_soc_write(codec, TAS2552_BOOST_APT_CTRL, TAS2552_APT_DELAY_200 |
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TAS2552_APT_THRESH_20_17);
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snd_soc_write(codec, TAS2552_CFG_2, TAS2552_BOOST_EN |
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TAS2552_APT_EN | TAS2552_LIM_EN);
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snd_soc_write(codec, TAS2552_CFG_2, TAS2552_BOOST_EN | TAS2552_APT_EN |
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TAS2552_LIM_EN);
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return 0;
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@ -647,13 +703,10 @@ static int tas2552_probe(struct i2c_client *client,
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if (data == NULL)
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return -ENOMEM;
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data->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
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if (IS_ERR(data->enable_gpio)) {
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if (PTR_ERR(data->enable_gpio) == -EPROBE_DEFER)
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return -EPROBE_DEFER;
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data->enable_gpio = NULL;;
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}
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data->enable_gpio = devm_gpiod_get_optional(dev, "enable",
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GPIOD_OUT_LOW);
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if (IS_ERR(data->enable_gpio))
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return PTR_ERR(data->enable_gpio);
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data->tas2552_client = client;
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data->regmap = devm_regmap_init_i2c(client, &tas2552_regmap_config);
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@ -695,6 +748,7 @@ static int tas2552_probe(struct i2c_client *client,
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static int tas2552_i2c_remove(struct i2c_client *client)
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{
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snd_soc_unregister_codec(&client->dev);
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pm_runtime_disable(&client->dev);
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return 0;
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}
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|
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@ -19,7 +19,7 @@
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#define __TAS2552_H__
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/* Register Address Map */
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#define TAS2552_DEVICE_STATUS 0x00
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#define TAS2552_DEVICE_STATUS 0x00
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#define TAS2552_CFG_1 0x01
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#define TAS2552_CFG_2 0x02
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#define TAS2552_CFG_3 0x03
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@ -33,13 +33,13 @@
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#define TAS2552_BTIP 0x0b
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#define TAS2552_BTS_CTRL 0x0c
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#define TAS2552_RESERVED_0D 0x0d
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#define TAS2552_LIMIT_RATE_HYS 0x0e
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#define TAS2552_LIMIT_RELEASE 0x0f
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#define TAS2552_LIMIT_INT_COUNT 0x10
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#define TAS2552_LIMIT_RATE_HYS 0x0e
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#define TAS2552_LIMIT_RELEASE 0x0f
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#define TAS2552_LIMIT_INT_COUNT 0x10
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#define TAS2552_PDM_CFG 0x11
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#define TAS2552_PGA_GAIN 0x12
|
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#define TAS2552_EDGE_RATE_CTRL 0x13
|
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#define TAS2552_BOOST_PT_CTRL 0x14
|
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#define TAS2552_EDGE_RATE_CTRL 0x13
|
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#define TAS2552_BOOST_APT_CTRL 0x14
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#define TAS2552_VER_NUM 0x16
|
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#define TAS2552_VBAT_DATA 0x19
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#define TAS2552_MAX_REG 0x20
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|
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@ -103,10 +103,21 @@
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#define TAS2552_WCLKDIR (1 << 7)
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||||
|
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/* OUTPUT_DATA register */
|
||||
#define TAS2552_PDM_DATA_I 0x00
|
||||
#define TAS2552_PDM_DATA_V (1 << 6)
|
||||
#define TAS2552_PDM_DATA_I_V (1 << 7)
|
||||
#define TAS2552_PDM_DATA_V_I (0x11 << 6)
|
||||
#define TAS2552_DATA_OUT_I_DATA (0x0)
|
||||
#define TAS2552_DATA_OUT_V_DATA (0x1)
|
||||
#define TAS2552_DATA_OUT_VBAT_DATA (0x2)
|
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#define TAS2552_DATA_OUT_VBOOST_DATA (0x3)
|
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#define TAS2552_DATA_OUT_PGA_GAIN (0x4)
|
||||
#define TAS2552_DATA_OUT_IV_DATA (0x5)
|
||||
#define TAS2552_DATA_OUT_VBAT_VBOOST_GAIN (0x6)
|
||||
#define TAS2552_DATA_OUT_DISABLED (0x7)
|
||||
#define TAS2552_L_DATA_OUT(x) ((x) << 0)
|
||||
#define TAS2552_R_DATA_OUT(x) ((x) << 3)
|
||||
#define TAS2552_PDM_DATA_SEL_I (0x0 << 6)
|
||||
#define TAS2552_PDM_DATA_SEL_V (0x1 << 6)
|
||||
#define TAS2552_PDM_DATA_SEL_I_V (0x2 << 6)
|
||||
#define TAS2552_PDM_DATA_SEL_V_I (0x3 << 6)
|
||||
#define TAS2552_PDM_DATA_SEL_MASK TAS2552_PDM_DATA_SEL_V_I
|
||||
|
||||
/* PDM CFG Register */
|
||||
#define TAS2552_PDM_CLK_SEL_PLL (0x0 << 0)
|
||||
|
|
@ -116,24 +127,20 @@
|
|||
#define TAS2552_PDM_CLK_SEL_MASK TAS2552_PDM_CLK_SEL_MCLK
|
||||
#define TAS2552_PDM_DATA_ES (1 << 2)
|
||||
|
||||
/* Boost pass-through register */
|
||||
#define TAS2552_APT_DELAY_50 0x00
|
||||
#define TAS2552_APT_DELAY_75 (1 << 1)
|
||||
#define TAS2552_APT_DELAY_125 (1 << 2)
|
||||
#define TAS2552_APT_DELAY_200 (1 << 3)
|
||||
|
||||
#define TAS2552_APT_THRESH_2_5 0x00
|
||||
#define TAS2552_APT_THRESH_1_7 (1 << 3)
|
||||
#define TAS2552_APT_THRESH_1_4_1_1 (1 << 4)
|
||||
#define TAS2552_APT_THRESH_2_1_7 (0x11 << 2)
|
||||
/* Boost Auto-pass through register */
|
||||
#define TAS2552_APT_DELAY_50 (0x0 << 0)
|
||||
#define TAS2552_APT_DELAY_75 (0x1 << 0)
|
||||
#define TAS2552_APT_DELAY_125 (0x2 << 0)
|
||||
#define TAS2552_APT_DELAY_200 (0x3 << 0)
|
||||
#define TAS2552_APT_THRESH_05_02 (0x0 << 2)
|
||||
#define TAS2552_APT_THRESH_10_07 (0x1 << 2)
|
||||
#define TAS2552_APT_THRESH_14_11 (0x2 << 2)
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||||
#define TAS2552_APT_THRESH_20_17 (0x3 << 2)
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/* PLL Control Register */
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#define TAS2552_245MHZ_CLK 24576000
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#define TAS2552_225MHZ_CLK 22579200
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#define TAS2552_PLL_J_MASK 0x7f
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#define TAS2552_PLL_D_UPPER_MASK 0x3f
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#define TAS2552_PLL_D_LOWER_MASK 0xff
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#define TAS2552_PLL_BYPASS_MASK 0x80
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#define TAS2552_PLL_BYPASS 0x80
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#define TAS2552_PLL_J_MASK 0x7f
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#define TAS2552_PLL_D_UPPER(x) (((x) >> 8) & 0x3f)
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#define TAS2552_PLL_D_LOWER(x) ((x) & 0xff)
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#define TAS2552_PLL_BYPASS (1 << 7)
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#endif
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