PCI updates for v4.5:
Freescale Layerscape host bridge driver Fix MSG TLP drop setting (Minghuan Lian) TI Keystone host bridge driver Fix MSI code that retrieves struct pcie_port pointer (Murali Karicheri) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJW2Ha2AAoJEFmIoMA60/r8Fg0P/2MAV3FUJfTdG+FdmSQu5TOh EncQbwTR8SDnMtPa1H8+eIE7n6CXA56OeGMfRMhEDhbGWyJEMnPM1h/NKYLkcNPS lNPwboMfxlmPClulMg012e7/clzwVbBlSndxkjkZVzmcstuTrzXKFcN8pmFMzaN1 tOnuEPIQZuvyqCU2R+6krT/aUG7+xUjULk4m349lVqbr3z1635YgnrIe57gCYBY6 meAfgEEewU/XgjFKviy7wC30gViUaZA+CdvwxZpROH+RIhX3kUYKep31KPXiyIVn 3SPDF9gkW5s5RullIQQiNygMRs4e7rrdAT3LF1kEQWDyfZ6AJfHduMC6CdXUzkzB WHvi7rtKtubo+pTGq+fSXTXlESQp8C1fTzeUJLlUrEj/5j1VL0J9uOOk3QtDQVGP QMD4YzKYjfJbmtSzE/mL9GIpYIb9fXeOCGfdsdndynU6QDIZ2RN+9jSR82gLMZZj PUUDixtH9+jUMxSARp3ftX9/8VbINbJFT2NtMCSRRXLGrIohekhgpFhpQw8wdaiX TuJdSOVaWYIJS+mT2T7/8ZAuB48a4sd6vW+1/31itEGPkhh1XdPp6Fa46eBeGTCq /hs5xlgohmW89HOLj0u7W0feTRwQe5tcph+GgfH4/SrFOlVtbL7kGtzkjc4dCJmw 8TySu5pOthybKAp+dDVn =ASQ6 -----END PGP SIGNATURE----- Merge tag 'pci-v4.5-fixes-4' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI fixes from Bjorn Helgaas: "Freescale Layerscape host bridge driver: Fix MSG TLP drop setting (Minghuan Lian) TI Keystone host bridge driver: Fix MSI code that retrieves struct pcie_port pointer (Murali Karicheri)" * tag 'pci-v4.5-fixes-4' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: PCI: layerscape: Fix MSG TLP drop setting PCI: keystone: Fix MSI code that retrieves struct pcie_port pointer
This commit is contained in:
Коммит
e3c2ef41f8
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@ -58,11 +58,6 @@
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#define to_keystone_pcie(x) container_of(x, struct keystone_pcie, pp)
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static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
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{
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return sys->private_data;
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}
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static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset,
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u32 *bit_pos)
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{
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@ -108,7 +103,7 @@ static void ks_dw_pcie_msi_irq_ack(struct irq_data *d)
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struct pcie_port *pp;
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msi = irq_data_get_msi_desc(d);
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pp = sys_to_pcie(msi_desc_to_pci_sysdata(msi));
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pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
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ks_pcie = to_keystone_pcie(pp);
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offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
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update_reg_offset_bit_pos(offset, ®_offset, &bit_pos);
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@ -146,7 +141,7 @@ static void ks_dw_pcie_msi_irq_mask(struct irq_data *d)
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u32 offset;
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msi = irq_data_get_msi_desc(d);
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pp = sys_to_pcie(msi_desc_to_pci_sysdata(msi));
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pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
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ks_pcie = to_keystone_pcie(pp);
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offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
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@ -167,7 +162,7 @@ static void ks_dw_pcie_msi_irq_unmask(struct irq_data *d)
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u32 offset;
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msi = irq_data_get_msi_desc(d);
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pp = sys_to_pcie(msi_desc_to_pci_sysdata(msi));
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pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
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ks_pcie = to_keystone_pcie(pp);
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offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
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@ -77,6 +77,16 @@ static void ls_pcie_fix_class(struct ls_pcie *pcie)
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iowrite16(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE);
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}
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/* Drop MSG TLP except for Vendor MSG */
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static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
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{
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u32 val;
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val = ioread32(pcie->dbi + PCIE_STRFMR1);
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val &= 0xDFFFFFFF;
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iowrite32(val, pcie->dbi + PCIE_STRFMR1);
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}
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static int ls1021_pcie_link_up(struct pcie_port *pp)
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{
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u32 state;
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@ -97,7 +107,7 @@ static int ls1021_pcie_link_up(struct pcie_port *pp)
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static void ls1021_pcie_host_init(struct pcie_port *pp)
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{
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struct ls_pcie *pcie = to_ls_pcie(pp);
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u32 val, index[2];
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u32 index[2];
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pcie->scfg = syscon_regmap_lookup_by_phandle(pp->dev->of_node,
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"fsl,pcie-scfg");
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@ -116,13 +126,7 @@ static void ls1021_pcie_host_init(struct pcie_port *pp)
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dw_pcie_setup_rc(pp);
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/*
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* LS1021A Workaround for internal TKT228622
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* to fix the INTx hang issue
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*/
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val = ioread32(pcie->dbi + PCIE_STRFMR1);
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val &= 0xffff;
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iowrite32(val, pcie->dbi + PCIE_STRFMR1);
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ls_pcie_drop_msg_tlp(pcie);
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}
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static int ls_pcie_link_up(struct pcie_port *pp)
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@ -147,6 +151,7 @@ static void ls_pcie_host_init(struct pcie_port *pp)
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iowrite32(1, pcie->dbi + PCIE_DBI_RO_WR_EN);
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ls_pcie_fix_class(pcie);
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ls_pcie_clear_multifunction(pcie);
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ls_pcie_drop_msg_tlp(pcie);
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iowrite32(0, pcie->dbi + PCIE_DBI_RO_WR_EN);
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}
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