Move all the EDAC core functionality behind CONFIG_EDAC and get rid of
that indirection. Update defconfigs which had it.

While at it, fix dependencies such that EDAC depends on RAS for the
tracepoints.

Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: Chris Metcalf <cmetcalf@mellanox.com>
Cc: linux-edac@vger.kernel.org
This commit is contained in:
Borislav Petkov 2017-02-03 18:18:05 +01:00
Родитель be1d162948
Коммит e3c4ff6d8c
16 изменённых файлов: 48 добавлений и 77 удалений

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@ -748,7 +748,6 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
CONFIG_LEDS_TRIGGER_TRANSIENT=y CONFIG_LEDS_TRIGGER_TRANSIENT=y
CONFIG_LEDS_TRIGGER_CAMERA=y CONFIG_LEDS_TRIGGER_CAMERA=y
CONFIG_EDAC=y CONFIG_EDAC=y
CONFIG_EDAC_MM_EDAC=y
CONFIG_EDAC_HIGHBANK_MC=y CONFIG_EDAC_HIGHBANK_MC=y
CONFIG_EDAC_HIGHBANK_L2=y CONFIG_EDAC_HIGHBANK_L2=y
CONFIG_RTC_CLASS=y CONFIG_RTC_CLASS=y

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@ -635,8 +635,7 @@ CONFIG_LEDS_TRIGGER_GPIO=m
CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
CONFIG_LEDS_TRIGGER_TRANSIENT=m CONFIG_LEDS_TRIGGER_TRANSIENT=m
CONFIG_LEDS_TRIGGER_CAMERA=m CONFIG_LEDS_TRIGGER_CAMERA=m
CONFIG_EDAC=y CONFIG_EDAC=m
CONFIG_EDAC_MM_EDAC=m
CONFIG_RTC_CLASS=y CONFIG_RTC_CLASS=y
CONFIG_RTC_DEBUG=y CONFIG_RTC_DEBUG=y
CONFIG_RTC_DRV_DS1307=m CONFIG_RTC_DRV_DS1307=m

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@ -16,9 +16,8 @@ CONFIG_DAVICOM_PHY=y
CONFIG_DMADEVICES=y CONFIG_DMADEVICES=y
CONFIG_E1000E=y CONFIG_E1000E=y
CONFIG_E1000=y CONFIG_E1000=y
CONFIG_EDAC_MM_EDAC=y
CONFIG_EDAC_MPC85XX=y
CONFIG_EDAC=y CONFIG_EDAC=y
CONFIG_EDAC_MPC85XX=y
CONFIG_EEPROM_AT24=y CONFIG_EEPROM_AT24=y
CONFIG_EEPROM_LEGACY=y CONFIG_EEPROM_LEGACY=y
CONFIG_FB_FSL_DIU=y CONFIG_FB_FSL_DIU=y

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@ -155,7 +155,6 @@ CONFIG_USB_OHCI_HCD_PPC_OF_BE=y
CONFIG_USB_OHCI_HCD_PPC_OF_LE=y CONFIG_USB_OHCI_HCD_PPC_OF_LE=y
CONFIG_USB_STORAGE=y CONFIG_USB_STORAGE=y
CONFIG_EDAC=y CONFIG_EDAC=y
CONFIG_EDAC_MM_EDAC=y
CONFIG_EDAC_MPC85XX=y CONFIG_EDAC_MPC85XX=y
CONFIG_RTC_CLASS=y CONFIG_RTC_CLASS=y
# CONFIG_RTC_INTF_PROC is not set # CONFIG_RTC_INTF_PROC is not set

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@ -116,7 +116,6 @@ CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_EDAC=y CONFIG_EDAC=y
CONFIG_EDAC_MM_EDAC=y
CONFIG_RTC_CLASS=y CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_DS1307=y
CONFIG_RTC_DRV_CMOS=y CONFIG_RTC_DRV_CMOS=y

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@ -179,7 +179,6 @@ CONFIG_INFINIBAND_MTHCA=m
CONFIG_INFINIBAND_IPOIB=m CONFIG_INFINIBAND_IPOIB=m
CONFIG_INFINIBAND_IPOIB_DEBUG_DATA=y CONFIG_INFINIBAND_IPOIB_DEBUG_DATA=y
CONFIG_EDAC=y CONFIG_EDAC=y
CONFIG_EDAC_MM_EDAC=y
CONFIG_EDAC_CELL=y CONFIG_EDAC_CELL=y
CONFIG_UIO=m CONFIG_UIO=m
CONFIG_EXT2_FS=y CONFIG_EXT2_FS=y

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@ -142,7 +142,6 @@ CONFIG_USB_UHCI_HCD=y
CONFIG_USB_SL811_HCD=y CONFIG_USB_SL811_HCD=y
CONFIG_USB_STORAGE=y CONFIG_USB_STORAGE=y
CONFIG_EDAC=y CONFIG_EDAC=y
CONFIG_EDAC_MM_EDAC=y
CONFIG_EDAC_PASEMI=y CONFIG_EDAC_PASEMI=y
CONFIG_RTC_CLASS=y CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_DS1307=y

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@ -262,7 +262,6 @@ CONFIG_INFINIBAND_IPOIB_CM=y
CONFIG_INFINIBAND_SRP=m CONFIG_INFINIBAND_SRP=m
CONFIG_INFINIBAND_ISER=m CONFIG_INFINIBAND_ISER=m
CONFIG_EDAC=y CONFIG_EDAC=y
CONFIG_EDAC_MM_EDAC=y
CONFIG_EDAC_PASEMI=y CONFIG_EDAC_PASEMI=y
CONFIG_RTC_CLASS=y CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_DS1307=y

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@ -173,7 +173,6 @@ CONFIG_INFINIBAND_MTHCA=m
CONFIG_INFINIBAND_IPOIB=m CONFIG_INFINIBAND_IPOIB=m
CONFIG_INFINIBAND_ISER=m CONFIG_INFINIBAND_ISER=m
CONFIG_EDAC=y CONFIG_EDAC=y
CONFIG_EDAC_MM_EDAC=y
CONFIG_RTC_CLASS=y CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_DS1307=y
CONFIG_FS_DAX=y CONFIG_FS_DAX=y

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@ -988,8 +988,7 @@ CONFIG_LEDS_TRIGGER_BACKLIGHT=m
CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
CONFIG_ACCESSIBILITY=y CONFIG_ACCESSIBILITY=y
CONFIG_A11Y_BRAILLE_CONSOLE=y CONFIG_A11Y_BRAILLE_CONSOLE=y
CONFIG_EDAC=y CONFIG_EDAC=m
CONFIG_EDAC_MM_EDAC=m
CONFIG_RTC_CLASS=y CONFIG_RTC_CLASS=y
# CONFIG_RTC_HCTOSYS is not set # CONFIG_RTC_HCTOSYS is not set
CONFIG_RTC_DRV_DS1307=m CONFIG_RTC_DRV_DS1307=m

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@ -249,7 +249,6 @@ CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_HCD=y
CONFIG_USB_STORAGE=y CONFIG_USB_STORAGE=y
CONFIG_EDAC=y CONFIG_EDAC=y
CONFIG_EDAC_MM_EDAC=y
CONFIG_RTC_CLASS=y CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_TILE=y CONFIG_RTC_DRV_TILE=y
CONFIG_EXT2_FS=y CONFIG_EXT2_FS=y

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@ -358,7 +358,6 @@ CONFIG_WATCHDOG_NOWAYOUT=y
# CONFIG_VGA_ARB is not set # CONFIG_VGA_ARB is not set
# CONFIG_USB_SUPPORT is not set # CONFIG_USB_SUPPORT is not set
CONFIG_EDAC=y CONFIG_EDAC=y
CONFIG_EDAC_MM_EDAC=y
CONFIG_RTC_CLASS=y CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_TILE=y CONFIG_RTC_DRV_TILE=y
CONFIG_EXT2_FS=y CONFIG_EXT2_FS=y

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@ -471,7 +471,6 @@ config ACPI_EXTLOG
tristate "Extended Error Log support" tristate "Extended Error Log support"
depends on X86_MCE && X86_LOCAL_APIC && EDAC depends on X86_MCE && X86_LOCAL_APIC && EDAC
select UEFI_CPER select UEFI_CPER
select RAS
default n default n
help help
Certain usages such as Predictive Failure Analysis (PFA) require Certain usages such as Predictive Failure Analysis (PFA) require

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@ -10,8 +10,8 @@ config EDAC_SUPPORT
bool bool
menuconfig EDAC menuconfig EDAC
bool "EDAC (Error Detection And Correction) reporting" tristate "EDAC (Error Detection And Correction) reporting"
depends on HAS_IOMEM && EDAC_SUPPORT depends on HAS_IOMEM && EDAC_SUPPORT && RAS
help help
EDAC is designed to report errors in the core system. EDAC is designed to report errors in the core system.
These are low-level errors that are reported in the CPU or These are low-level errors that are reported in the CPU or
@ -62,20 +62,9 @@ config EDAC_DECODE_MCE
which occur really early upon boot, before the module infrastructure which occur really early upon boot, before the module infrastructure
has been initialized. has been initialized.
config EDAC_MM_EDAC
tristate "Main Memory EDAC (Error Detection And Correction) reporting"
select RAS
help
Some systems are able to detect and correct errors in main
memory. EDAC can report statistics on memory error
detection and correction (EDAC - or commonly referred to ECC
errors). EDAC will also try to decode where these errors
occurred so that a particular failing memory module can be
replaced. If unsure, select 'Y'.
config EDAC_GHES config EDAC_GHES
bool "Output ACPI APEI/GHES BIOS detected errors via EDAC" bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
depends on ACPI_APEI_GHES && (EDAC_MM_EDAC=y) depends on ACPI_APEI_GHES && (EDAC=y)
default y default y
help help
Not all machines support hardware-driven error report. Some of those Not all machines support hardware-driven error report. Some of those
@ -98,7 +87,7 @@ config EDAC_GHES
config EDAC_AMD64 config EDAC_AMD64
tristate "AMD64 (Opteron, Athlon64)" tristate "AMD64 (Opteron, Athlon64)"
depends on EDAC_MM_EDAC && AMD_NB && EDAC_DECODE_MCE depends on AMD_NB && EDAC_DECODE_MCE
help help
Support for error detection and correction of DRAM ECC errors on Support for error detection and correction of DRAM ECC errors on
the AMD64 families (>= K8) of memory controllers. the AMD64 families (>= K8) of memory controllers.
@ -124,28 +113,28 @@ config EDAC_AMD64_ERROR_INJECTION
config EDAC_AMD76X config EDAC_AMD76X
tristate "AMD 76x (760, 762, 768)" tristate "AMD 76x (760, 762, 768)"
depends on EDAC_MM_EDAC && PCI && X86_32 depends on PCI && X86_32
help help
Support for error detection and correction on the AMD 76x Support for error detection and correction on the AMD 76x
series of chipsets used with the Athlon processor. series of chipsets used with the Athlon processor.
config EDAC_E7XXX config EDAC_E7XXX
tristate "Intel e7xxx (e7205, e7500, e7501, e7505)" tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
depends on EDAC_MM_EDAC && PCI && X86_32 depends on PCI && X86_32
help help
Support for error detection and correction on the Intel Support for error detection and correction on the Intel
E7205, E7500, E7501 and E7505 server chipsets. E7205, E7500, E7501 and E7505 server chipsets.
config EDAC_E752X config EDAC_E752X
tristate "Intel e752x (e7520, e7525, e7320) and 3100" tristate "Intel e752x (e7520, e7525, e7320) and 3100"
depends on EDAC_MM_EDAC && PCI && X86 depends on PCI && X86
help help
Support for error detection and correction on the Intel Support for error detection and correction on the Intel
E7520, E7525, E7320 server chipsets. E7520, E7525, E7320 server chipsets.
config EDAC_I82443BXGX config EDAC_I82443BXGX
tristate "Intel 82443BX/GX (440BX/GX)" tristate "Intel 82443BX/GX (440BX/GX)"
depends on EDAC_MM_EDAC && PCI && X86_32 depends on PCI && X86_32
depends on BROKEN depends on BROKEN
help help
Support for error detection and correction on the Intel Support for error detection and correction on the Intel
@ -153,56 +142,56 @@ config EDAC_I82443BXGX
config EDAC_I82875P config EDAC_I82875P
tristate "Intel 82875p (D82875P, E7210)" tristate "Intel 82875p (D82875P, E7210)"
depends on EDAC_MM_EDAC && PCI && X86_32 depends on PCI && X86_32
help help
Support for error detection and correction on the Intel Support for error detection and correction on the Intel
DP82785P and E7210 server chipsets. DP82785P and E7210 server chipsets.
config EDAC_I82975X config EDAC_I82975X
tristate "Intel 82975x (D82975x)" tristate "Intel 82975x (D82975x)"
depends on EDAC_MM_EDAC && PCI && X86 depends on PCI && X86
help help
Support for error detection and correction on the Intel Support for error detection and correction on the Intel
DP82975x server chipsets. DP82975x server chipsets.
config EDAC_I3000 config EDAC_I3000
tristate "Intel 3000/3010" tristate "Intel 3000/3010"
depends on EDAC_MM_EDAC && PCI && X86 depends on PCI && X86
help help
Support for error detection and correction on the Intel Support for error detection and correction on the Intel
3000 and 3010 server chipsets. 3000 and 3010 server chipsets.
config EDAC_I3200 config EDAC_I3200
tristate "Intel 3200" tristate "Intel 3200"
depends on EDAC_MM_EDAC && PCI && X86 depends on PCI && X86
help help
Support for error detection and correction on the Intel Support for error detection and correction on the Intel
3200 and 3210 server chipsets. 3200 and 3210 server chipsets.
config EDAC_IE31200 config EDAC_IE31200
tristate "Intel e312xx" tristate "Intel e312xx"
depends on EDAC_MM_EDAC && PCI && X86 depends on PCI && X86
help help
Support for error detection and correction on the Intel Support for error detection and correction on the Intel
E3-1200 based DRAM controllers. E3-1200 based DRAM controllers.
config EDAC_X38 config EDAC_X38
tristate "Intel X38" tristate "Intel X38"
depends on EDAC_MM_EDAC && PCI && X86 depends on PCI && X86
help help
Support for error detection and correction on the Intel Support for error detection and correction on the Intel
X38 server chipsets. X38 server chipsets.
config EDAC_I5400 config EDAC_I5400
tristate "Intel 5400 (Seaburg) chipsets" tristate "Intel 5400 (Seaburg) chipsets"
depends on EDAC_MM_EDAC && PCI && X86 depends on PCI && X86
help help
Support for error detection and correction the Intel Support for error detection and correction the Intel
i5400 MCH chipset (Seaburg). i5400 MCH chipset (Seaburg).
config EDAC_I7CORE config EDAC_I7CORE
tristate "Intel i7 Core (Nehalem) processors" tristate "Intel i7 Core (Nehalem) processors"
depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL depends on PCI && X86 && X86_MCE_INTEL
help help
Support for error detection and correction the Intel Support for error detection and correction the Intel
i7 Core (Nehalem) Integrated Memory Controller that exists on i7 Core (Nehalem) Integrated Memory Controller that exists on
@ -211,58 +200,56 @@ config EDAC_I7CORE
config EDAC_I82860 config EDAC_I82860
tristate "Intel 82860" tristate "Intel 82860"
depends on EDAC_MM_EDAC && PCI && X86_32 depends on PCI && X86_32
help help
Support for error detection and correction on the Intel Support for error detection and correction on the Intel
82860 chipset. 82860 chipset.
config EDAC_R82600 config EDAC_R82600
tristate "Radisys 82600 embedded chipset" tristate "Radisys 82600 embedded chipset"
depends on EDAC_MM_EDAC && PCI && X86_32 depends on PCI && X86_32
help help
Support for error detection and correction on the Radisys Support for error detection and correction on the Radisys
82600 embedded chipset. 82600 embedded chipset.
config EDAC_I5000 config EDAC_I5000
tristate "Intel Greencreek/Blackford chipset" tristate "Intel Greencreek/Blackford chipset"
depends on EDAC_MM_EDAC && X86 && PCI depends on X86 && PCI
help help
Support for error detection and correction the Intel Support for error detection and correction the Intel
Greekcreek/Blackford chipsets. Greekcreek/Blackford chipsets.
config EDAC_I5100 config EDAC_I5100
tristate "Intel San Clemente MCH" tristate "Intel San Clemente MCH"
depends on EDAC_MM_EDAC && X86 && PCI depends on X86 && PCI
help help
Support for error detection and correction the Intel Support for error detection and correction the Intel
San Clemente MCH. San Clemente MCH.
config EDAC_I7300 config EDAC_I7300
tristate "Intel Clarksboro MCH" tristate "Intel Clarksboro MCH"
depends on EDAC_MM_EDAC && X86 && PCI depends on X86 && PCI
help help
Support for error detection and correction the Intel Support for error detection and correction the Intel
Clarksboro MCH (Intel 7300 chipset). Clarksboro MCH (Intel 7300 chipset).
config EDAC_SBRIDGE config EDAC_SBRIDGE
tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC" tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
depends on PCI_MMCONFIG
help help
Support for error detection and correction the Intel Support for error detection and correction the Intel
Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers. Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
config EDAC_SKX config EDAC_SKX
tristate "Intel Skylake server Integrated MC" tristate "Intel Skylake server Integrated MC"
depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
depends on PCI_MMCONFIG
help help
Support for error detection and correction the Intel Support for error detection and correction the Intel
Skylake server Integrated Memory Controllers. Skylake server Integrated Memory Controllers.
config EDAC_PND2 config EDAC_PND2
tristate "Intel Pondicherry2" tristate "Intel Pondicherry2"
depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL depends on PCI && X86_64 && X86_MCE_INTEL
help help
Support for error detection and correction on the Intel Support for error detection and correction on the Intel
Pondicherry2 Integrated Memory Controller. This SoC IP is Pondicherry2 Integrated Memory Controller. This SoC IP is
@ -271,36 +258,35 @@ config EDAC_PND2
config EDAC_MPC85XX config EDAC_MPC85XX
tristate "Freescale MPC83xx / MPC85xx" tristate "Freescale MPC83xx / MPC85xx"
depends on EDAC_MM_EDAC && FSL_SOC depends on FSL_SOC
help help
Support for error detection and correction on the Freescale Support for error detection and correction on the Freescale
MPC8349, MPC8560, MPC8540, MPC8548, T4240 MPC8349, MPC8560, MPC8540, MPC8548, T4240
config EDAC_LAYERSCAPE config EDAC_LAYERSCAPE
tristate "Freescale Layerscape DDR" tristate "Freescale Layerscape DDR"
depends on EDAC_MM_EDAC && ARCH_LAYERSCAPE depends on ARCH_LAYERSCAPE
help help
Support for error detection and correction on Freescale memory Support for error detection and correction on Freescale memory
controllers on Layerscape SoCs. controllers on Layerscape SoCs.
config EDAC_MV64X60 config EDAC_MV64X60
tristate "Marvell MV64x60" tristate "Marvell MV64x60"
depends on EDAC_MM_EDAC && MV64X60 depends on MV64X60
help help
Support for error detection and correction on the Marvell Support for error detection and correction on the Marvell
MV64360 and MV64460 chipsets. MV64360 and MV64460 chipsets.
config EDAC_PASEMI config EDAC_PASEMI
tristate "PA Semi PWRficient" tristate "PA Semi PWRficient"
depends on EDAC_MM_EDAC && PCI depends on PPC_PASEMI && PCI
depends on PPC_PASEMI
help help
Support for error detection and correction on PA Semi Support for error detection and correction on PA Semi
PWRficient. PWRficient.
config EDAC_CELL config EDAC_CELL
tristate "Cell Broadband Engine memory controller" tristate "Cell Broadband Engine memory controller"
depends on EDAC_MM_EDAC && PPC_CELL_COMMON depends on PPC_CELL_COMMON
help help
Support for error detection and correction on the Support for error detection and correction on the
Cell Broadband Engine internal memory controller Cell Broadband Engine internal memory controller
@ -308,7 +294,7 @@ config EDAC_CELL
config EDAC_PPC4XX config EDAC_PPC4XX
tristate "PPC4xx IBM DDR2 Memory Controller" tristate "PPC4xx IBM DDR2 Memory Controller"
depends on EDAC_MM_EDAC && 4xx depends on 4xx
help help
This enables support for EDAC on the ECC memory used This enables support for EDAC on the ECC memory used
with the IBM DDR2 memory controller found in various with the IBM DDR2 memory controller found in various
@ -317,7 +303,7 @@ config EDAC_PPC4XX
config EDAC_AMD8131 config EDAC_AMD8131
tristate "AMD8131 HyperTransport PCI-X Tunnel" tristate "AMD8131 HyperTransport PCI-X Tunnel"
depends on EDAC_MM_EDAC && PCI && PPC_MAPLE depends on PCI && PPC_MAPLE
help help
Support for error detection and correction on the Support for error detection and correction on the
AMD8131 HyperTransport PCI-X Tunnel chip. AMD8131 HyperTransport PCI-X Tunnel chip.
@ -326,7 +312,7 @@ config EDAC_AMD8131
config EDAC_AMD8111 config EDAC_AMD8111
tristate "AMD8111 HyperTransport I/O Hub" tristate "AMD8111 HyperTransport I/O Hub"
depends on EDAC_MM_EDAC && PCI && PPC_MAPLE depends on PCI && PPC_MAPLE
help help
Support for error detection and correction on the Support for error detection and correction on the
AMD8111 HyperTransport I/O Hub chip. AMD8111 HyperTransport I/O Hub chip.
@ -335,7 +321,7 @@ config EDAC_AMD8111
config EDAC_CPC925 config EDAC_CPC925
tristate "IBM CPC925 Memory Controller (PPC970FX)" tristate "IBM CPC925 Memory Controller (PPC970FX)"
depends on EDAC_MM_EDAC && PPC64 depends on PPC64
help help
Support for error detection and correction on the Support for error detection and correction on the
IBM CPC925 Bridge and Memory Controller, which is IBM CPC925 Bridge and Memory Controller, which is
@ -344,7 +330,7 @@ config EDAC_CPC925
config EDAC_TILE config EDAC_TILE
tristate "Tilera Memory Controller" tristate "Tilera Memory Controller"
depends on EDAC_MM_EDAC && TILE depends on TILE
default y default y
help help
Support for error detection and correction on the Support for error detection and correction on the
@ -352,49 +338,48 @@ config EDAC_TILE
config EDAC_HIGHBANK_MC config EDAC_HIGHBANK_MC
tristate "Highbank Memory Controller" tristate "Highbank Memory Controller"
depends on EDAC_MM_EDAC && ARCH_HIGHBANK depends on ARCH_HIGHBANK
help help
Support for error detection and correction on the Support for error detection and correction on the
Calxeda Highbank memory controller. Calxeda Highbank memory controller.
config EDAC_HIGHBANK_L2 config EDAC_HIGHBANK_L2
tristate "Highbank L2 Cache" tristate "Highbank L2 Cache"
depends on EDAC_MM_EDAC && ARCH_HIGHBANK depends on ARCH_HIGHBANK
help help
Support for error detection and correction on the Support for error detection and correction on the
Calxeda Highbank memory controller. Calxeda Highbank memory controller.
config EDAC_OCTEON_PC config EDAC_OCTEON_PC
tristate "Cavium Octeon Primary Caches" tristate "Cavium Octeon Primary Caches"
depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON depends on CPU_CAVIUM_OCTEON
help help
Support for error detection and correction on the primary caches of Support for error detection and correction on the primary caches of
the cnMIPS cores of Cavium Octeon family SOCs. the cnMIPS cores of Cavium Octeon family SOCs.
config EDAC_OCTEON_L2C config EDAC_OCTEON_L2C
tristate "Cavium Octeon Secondary Caches (L2C)" tristate "Cavium Octeon Secondary Caches (L2C)"
depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC depends on CAVIUM_OCTEON_SOC
help help
Support for error detection and correction on the Support for error detection and correction on the
Cavium Octeon family of SOCs. Cavium Octeon family of SOCs.
config EDAC_OCTEON_LMC config EDAC_OCTEON_LMC
tristate "Cavium Octeon DRAM Memory Controller (LMC)" tristate "Cavium Octeon DRAM Memory Controller (LMC)"
depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC depends on CAVIUM_OCTEON_SOC
help help
Support for error detection and correction on the Support for error detection and correction on the
Cavium Octeon family of SOCs. Cavium Octeon family of SOCs.
config EDAC_OCTEON_PCI config EDAC_OCTEON_PCI
tristate "Cavium Octeon PCI Controller" tristate "Cavium Octeon PCI Controller"
depends on EDAC_MM_EDAC && PCI && CAVIUM_OCTEON_SOC depends on PCI && CAVIUM_OCTEON_SOC
help help
Support for error detection and correction on the Support for error detection and correction on the
Cavium Octeon family of SOCs. Cavium Octeon family of SOCs.
config EDAC_THUNDERX config EDAC_THUNDERX
tristate "Cavium ThunderX EDAC" tristate "Cavium ThunderX EDAC"
depends on EDAC_MM_EDAC
depends on ARM64 depends on ARM64
depends on PCI depends on PCI
help help
@ -405,7 +390,7 @@ config EDAC_THUNDERX
config EDAC_ALTERA config EDAC_ALTERA
bool "Altera SOCFPGA ECC" bool "Altera SOCFPGA ECC"
depends on EDAC_MM_EDAC=y && ARCH_SOCFPGA depends on EDAC=y && ARCH_SOCFPGA
help help
Support for error detection and correction on the Support for error detection and correction on the
Altera SOCs. This must be selected for SDRAM ECC. Altera SOCs. This must be selected for SDRAM ECC.
@ -471,14 +456,14 @@ config EDAC_ALTERA_SDMMC
config EDAC_SYNOPSYS config EDAC_SYNOPSYS
tristate "Synopsys DDR Memory Controller" tristate "Synopsys DDR Memory Controller"
depends on EDAC_MM_EDAC && ARCH_ZYNQ depends on ARCH_ZYNQ
help help
Support for error detection and correction on the Synopsys DDR Support for error detection and correction on the Synopsys DDR
memory controller. memory controller.
config EDAC_XGENE config EDAC_XGENE
tristate "APM X-Gene SoC" tristate "APM X-Gene SoC"
depends on EDAC_MM_EDAC && (ARM64 || COMPILE_TEST) depends on (ARM64 || COMPILE_TEST)
help help
Support for error detection and correction on the Support for error detection and correction on the
APM X-Gene family of SOCs. APM X-Gene family of SOCs.

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@ -6,8 +6,7 @@
# GNU General Public License. # GNU General Public License.
# #
obj-$(CONFIG_EDAC) := edac_stub.o obj-$(CONFIG_EDAC) := edac_stub.o edac_core.o
obj-$(CONFIG_EDAC_MM_EDAC) += edac_core.o
edac_core-y := edac_mc.o edac_device.o edac_mc_sysfs.o edac_core-y := edac_mc.o edac_device.o edac_mc_sysfs.o
edac_core-y += edac_module.o edac_device_sysfs.o wq.o edac_core-y += edac_module.o edac_device_sysfs.o wq.o

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@ -20,7 +20,7 @@
int edac_report_status = EDAC_REPORTING_ENABLED; int edac_report_status = EDAC_REPORTING_ENABLED;
EXPORT_SYMBOL_GPL(edac_report_status); EXPORT_SYMBOL_GPL(edac_report_status);
static int __init edac_report_setup(char *str) static int __init __maybe_unused edac_report_setup(char *str)
{ {
if (!str) if (!str)
return -EINVAL; return -EINVAL;