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@ -10,8 +10,8 @@ config EDAC_SUPPORT
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bool
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bool
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menuconfig EDAC
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menuconfig EDAC
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bool "EDAC (Error Detection And Correction) reporting"
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tristate "EDAC (Error Detection And Correction) reporting"
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depends on HAS_IOMEM && EDAC_SUPPORT
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depends on HAS_IOMEM && EDAC_SUPPORT && RAS
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help
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help
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EDAC is designed to report errors in the core system.
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EDAC is designed to report errors in the core system.
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These are low-level errors that are reported in the CPU or
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These are low-level errors that are reported in the CPU or
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@ -62,20 +62,9 @@ config EDAC_DECODE_MCE
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which occur really early upon boot, before the module infrastructure
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which occur really early upon boot, before the module infrastructure
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has been initialized.
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has been initialized.
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config EDAC_MM_EDAC
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tristate "Main Memory EDAC (Error Detection And Correction) reporting"
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select RAS
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help
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Some systems are able to detect and correct errors in main
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memory. EDAC can report statistics on memory error
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detection and correction (EDAC - or commonly referred to ECC
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errors). EDAC will also try to decode where these errors
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occurred so that a particular failing memory module can be
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replaced. If unsure, select 'Y'.
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config EDAC_GHES
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config EDAC_GHES
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bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
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bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
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depends on ACPI_APEI_GHES && (EDAC_MM_EDAC=y)
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depends on ACPI_APEI_GHES && (EDAC=y)
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default y
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default y
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help
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help
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Not all machines support hardware-driven error report. Some of those
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Not all machines support hardware-driven error report. Some of those
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@ -98,7 +87,7 @@ config EDAC_GHES
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config EDAC_AMD64
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config EDAC_AMD64
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tristate "AMD64 (Opteron, Athlon64)"
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tristate "AMD64 (Opteron, Athlon64)"
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depends on EDAC_MM_EDAC && AMD_NB && EDAC_DECODE_MCE
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depends on AMD_NB && EDAC_DECODE_MCE
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help
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help
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Support for error detection and correction of DRAM ECC errors on
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Support for error detection and correction of DRAM ECC errors on
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the AMD64 families (>= K8) of memory controllers.
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the AMD64 families (>= K8) of memory controllers.
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@ -124,28 +113,28 @@ config EDAC_AMD64_ERROR_INJECTION
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config EDAC_AMD76X
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config EDAC_AMD76X
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tristate "AMD 76x (760, 762, 768)"
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tristate "AMD 76x (760, 762, 768)"
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depends on EDAC_MM_EDAC && PCI && X86_32
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depends on PCI && X86_32
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help
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help
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Support for error detection and correction on the AMD 76x
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Support for error detection and correction on the AMD 76x
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series of chipsets used with the Athlon processor.
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series of chipsets used with the Athlon processor.
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config EDAC_E7XXX
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config EDAC_E7XXX
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tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
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tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
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depends on EDAC_MM_EDAC && PCI && X86_32
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depends on PCI && X86_32
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help
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help
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Support for error detection and correction on the Intel
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Support for error detection and correction on the Intel
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E7205, E7500, E7501 and E7505 server chipsets.
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E7205, E7500, E7501 and E7505 server chipsets.
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config EDAC_E752X
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config EDAC_E752X
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tristate "Intel e752x (e7520, e7525, e7320) and 3100"
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tristate "Intel e752x (e7520, e7525, e7320) and 3100"
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depends on EDAC_MM_EDAC && PCI && X86
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depends on PCI && X86
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help
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help
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Support for error detection and correction on the Intel
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Support for error detection and correction on the Intel
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E7520, E7525, E7320 server chipsets.
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E7520, E7525, E7320 server chipsets.
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config EDAC_I82443BXGX
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config EDAC_I82443BXGX
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tristate "Intel 82443BX/GX (440BX/GX)"
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tristate "Intel 82443BX/GX (440BX/GX)"
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depends on EDAC_MM_EDAC && PCI && X86_32
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depends on PCI && X86_32
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depends on BROKEN
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depends on BROKEN
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help
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help
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Support for error detection and correction on the Intel
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Support for error detection and correction on the Intel
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@ -153,56 +142,56 @@ config EDAC_I82443BXGX
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config EDAC_I82875P
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config EDAC_I82875P
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tristate "Intel 82875p (D82875P, E7210)"
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tristate "Intel 82875p (D82875P, E7210)"
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depends on EDAC_MM_EDAC && PCI && X86_32
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depends on PCI && X86_32
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help
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help
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Support for error detection and correction on the Intel
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Support for error detection and correction on the Intel
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DP82785P and E7210 server chipsets.
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DP82785P and E7210 server chipsets.
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config EDAC_I82975X
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config EDAC_I82975X
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tristate "Intel 82975x (D82975x)"
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tristate "Intel 82975x (D82975x)"
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depends on EDAC_MM_EDAC && PCI && X86
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depends on PCI && X86
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help
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help
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Support for error detection and correction on the Intel
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Support for error detection and correction on the Intel
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DP82975x server chipsets.
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DP82975x server chipsets.
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config EDAC_I3000
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config EDAC_I3000
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tristate "Intel 3000/3010"
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tristate "Intel 3000/3010"
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depends on EDAC_MM_EDAC && PCI && X86
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depends on PCI && X86
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help
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help
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Support for error detection and correction on the Intel
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Support for error detection and correction on the Intel
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3000 and 3010 server chipsets.
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3000 and 3010 server chipsets.
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config EDAC_I3200
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config EDAC_I3200
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tristate "Intel 3200"
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tristate "Intel 3200"
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depends on EDAC_MM_EDAC && PCI && X86
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depends on PCI && X86
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help
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help
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Support for error detection and correction on the Intel
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Support for error detection and correction on the Intel
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3200 and 3210 server chipsets.
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3200 and 3210 server chipsets.
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config EDAC_IE31200
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config EDAC_IE31200
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tristate "Intel e312xx"
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tristate "Intel e312xx"
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depends on EDAC_MM_EDAC && PCI && X86
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depends on PCI && X86
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help
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help
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Support for error detection and correction on the Intel
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Support for error detection and correction on the Intel
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E3-1200 based DRAM controllers.
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E3-1200 based DRAM controllers.
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config EDAC_X38
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config EDAC_X38
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tristate "Intel X38"
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tristate "Intel X38"
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depends on EDAC_MM_EDAC && PCI && X86
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depends on PCI && X86
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help
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help
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Support for error detection and correction on the Intel
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Support for error detection and correction on the Intel
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X38 server chipsets.
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X38 server chipsets.
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config EDAC_I5400
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config EDAC_I5400
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tristate "Intel 5400 (Seaburg) chipsets"
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tristate "Intel 5400 (Seaburg) chipsets"
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depends on EDAC_MM_EDAC && PCI && X86
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depends on PCI && X86
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help
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help
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Support for error detection and correction the Intel
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Support for error detection and correction the Intel
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i5400 MCH chipset (Seaburg).
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i5400 MCH chipset (Seaburg).
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config EDAC_I7CORE
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config EDAC_I7CORE
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tristate "Intel i7 Core (Nehalem) processors"
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tristate "Intel i7 Core (Nehalem) processors"
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depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL
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depends on PCI && X86 && X86_MCE_INTEL
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help
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help
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Support for error detection and correction the Intel
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Support for error detection and correction the Intel
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i7 Core (Nehalem) Integrated Memory Controller that exists on
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i7 Core (Nehalem) Integrated Memory Controller that exists on
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@ -211,58 +200,56 @@ config EDAC_I7CORE
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config EDAC_I82860
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config EDAC_I82860
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tristate "Intel 82860"
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tristate "Intel 82860"
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depends on EDAC_MM_EDAC && PCI && X86_32
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depends on PCI && X86_32
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help
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help
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Support for error detection and correction on the Intel
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Support for error detection and correction on the Intel
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82860 chipset.
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82860 chipset.
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config EDAC_R82600
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config EDAC_R82600
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tristate "Radisys 82600 embedded chipset"
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tristate "Radisys 82600 embedded chipset"
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depends on EDAC_MM_EDAC && PCI && X86_32
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depends on PCI && X86_32
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help
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help
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Support for error detection and correction on the Radisys
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Support for error detection and correction on the Radisys
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82600 embedded chipset.
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82600 embedded chipset.
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config EDAC_I5000
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config EDAC_I5000
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tristate "Intel Greencreek/Blackford chipset"
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tristate "Intel Greencreek/Blackford chipset"
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depends on EDAC_MM_EDAC && X86 && PCI
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depends on X86 && PCI
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help
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help
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Support for error detection and correction the Intel
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Support for error detection and correction the Intel
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Greekcreek/Blackford chipsets.
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Greekcreek/Blackford chipsets.
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config EDAC_I5100
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config EDAC_I5100
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tristate "Intel San Clemente MCH"
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tristate "Intel San Clemente MCH"
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depends on EDAC_MM_EDAC && X86 && PCI
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depends on X86 && PCI
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help
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help
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Support for error detection and correction the Intel
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Support for error detection and correction the Intel
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San Clemente MCH.
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San Clemente MCH.
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config EDAC_I7300
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config EDAC_I7300
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tristate "Intel Clarksboro MCH"
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tristate "Intel Clarksboro MCH"
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depends on EDAC_MM_EDAC && X86 && PCI
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depends on X86 && PCI
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help
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help
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Support for error detection and correction the Intel
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Support for error detection and correction the Intel
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Clarksboro MCH (Intel 7300 chipset).
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Clarksboro MCH (Intel 7300 chipset).
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config EDAC_SBRIDGE
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config EDAC_SBRIDGE
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tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
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tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
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depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
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depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
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depends on PCI_MMCONFIG
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help
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help
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Support for error detection and correction the Intel
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Support for error detection and correction the Intel
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Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
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Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
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config EDAC_SKX
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config EDAC_SKX
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tristate "Intel Skylake server Integrated MC"
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tristate "Intel Skylake server Integrated MC"
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depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
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depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
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depends on PCI_MMCONFIG
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help
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help
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Support for error detection and correction the Intel
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Support for error detection and correction the Intel
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Skylake server Integrated Memory Controllers.
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Skylake server Integrated Memory Controllers.
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config EDAC_PND2
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config EDAC_PND2
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tristate "Intel Pondicherry2"
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tristate "Intel Pondicherry2"
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depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
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depends on PCI && X86_64 && X86_MCE_INTEL
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help
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help
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Support for error detection and correction on the Intel
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Support for error detection and correction on the Intel
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|
Pondicherry2 Integrated Memory Controller. This SoC IP is
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Pondicherry2 Integrated Memory Controller. This SoC IP is
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|
@ -271,36 +258,35 @@ config EDAC_PND2
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config EDAC_MPC85XX
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config EDAC_MPC85XX
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tristate "Freescale MPC83xx / MPC85xx"
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tristate "Freescale MPC83xx / MPC85xx"
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depends on EDAC_MM_EDAC && FSL_SOC
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depends on FSL_SOC
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help
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help
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Support for error detection and correction on the Freescale
|
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Support for error detection and correction on the Freescale
|
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MPC8349, MPC8560, MPC8540, MPC8548, T4240
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MPC8349, MPC8560, MPC8540, MPC8548, T4240
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|
config EDAC_LAYERSCAPE
|
|
|
|
config EDAC_LAYERSCAPE
|
|
|
|
tristate "Freescale Layerscape DDR"
|
|
|
|
tristate "Freescale Layerscape DDR"
|
|
|
|
depends on EDAC_MM_EDAC && ARCH_LAYERSCAPE
|
|
|
|
depends on ARCH_LAYERSCAPE
|
|
|
|
help
|
|
|
|
help
|
|
|
|
Support for error detection and correction on Freescale memory
|
|
|
|
Support for error detection and correction on Freescale memory
|
|
|
|
controllers on Layerscape SoCs.
|
|
|
|
controllers on Layerscape SoCs.
|
|
|
|
|
|
|
|
|
|
|
|
config EDAC_MV64X60
|
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|
|
config EDAC_MV64X60
|
|
|
|
tristate "Marvell MV64x60"
|
|
|
|
tristate "Marvell MV64x60"
|
|
|
|
depends on EDAC_MM_EDAC && MV64X60
|
|
|
|
depends on MV64X60
|
|
|
|
help
|
|
|
|
help
|
|
|
|
Support for error detection and correction on the Marvell
|
|
|
|
Support for error detection and correction on the Marvell
|
|
|
|
MV64360 and MV64460 chipsets.
|
|
|
|
MV64360 and MV64460 chipsets.
|
|
|
|
|
|
|
|
|
|
|
|
config EDAC_PASEMI
|
|
|
|
config EDAC_PASEMI
|
|
|
|
tristate "PA Semi PWRficient"
|
|
|
|
tristate "PA Semi PWRficient"
|
|
|
|
depends on EDAC_MM_EDAC && PCI
|
|
|
|
depends on PPC_PASEMI && PCI
|
|
|
|
depends on PPC_PASEMI
|
|
|
|
|
|
|
|
help
|
|
|
|
help
|
|
|
|
Support for error detection and correction on PA Semi
|
|
|
|
Support for error detection and correction on PA Semi
|
|
|
|
PWRficient.
|
|
|
|
PWRficient.
|
|
|
|
|
|
|
|
|
|
|
|
config EDAC_CELL
|
|
|
|
config EDAC_CELL
|
|
|
|
tristate "Cell Broadband Engine memory controller"
|
|
|
|
tristate "Cell Broadband Engine memory controller"
|
|
|
|
depends on EDAC_MM_EDAC && PPC_CELL_COMMON
|
|
|
|
depends on PPC_CELL_COMMON
|
|
|
|
help
|
|
|
|
help
|
|
|
|
Support for error detection and correction on the
|
|
|
|
Support for error detection and correction on the
|
|
|
|
Cell Broadband Engine internal memory controller
|
|
|
|
Cell Broadband Engine internal memory controller
|
|
|
@ -308,7 +294,7 @@ config EDAC_CELL
|
|
|
|
|
|
|
|
|
|
|
|
config EDAC_PPC4XX
|
|
|
|
config EDAC_PPC4XX
|
|
|
|
tristate "PPC4xx IBM DDR2 Memory Controller"
|
|
|
|
tristate "PPC4xx IBM DDR2 Memory Controller"
|
|
|
|
depends on EDAC_MM_EDAC && 4xx
|
|
|
|
depends on 4xx
|
|
|
|
help
|
|
|
|
help
|
|
|
|
This enables support for EDAC on the ECC memory used
|
|
|
|
This enables support for EDAC on the ECC memory used
|
|
|
|
with the IBM DDR2 memory controller found in various
|
|
|
|
with the IBM DDR2 memory controller found in various
|
|
|
@ -317,7 +303,7 @@ config EDAC_PPC4XX
|
|
|
|
|
|
|
|
|
|
|
|
config EDAC_AMD8131
|
|
|
|
config EDAC_AMD8131
|
|
|
|
tristate "AMD8131 HyperTransport PCI-X Tunnel"
|
|
|
|
tristate "AMD8131 HyperTransport PCI-X Tunnel"
|
|
|
|
depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
|
|
|
|
depends on PCI && PPC_MAPLE
|
|
|
|
help
|
|
|
|
help
|
|
|
|
Support for error detection and correction on the
|
|
|
|
Support for error detection and correction on the
|
|
|
|
AMD8131 HyperTransport PCI-X Tunnel chip.
|
|
|
|
AMD8131 HyperTransport PCI-X Tunnel chip.
|
|
|
@ -326,7 +312,7 @@ config EDAC_AMD8131
|
|
|
|
|
|
|
|
|
|
|
|
config EDAC_AMD8111
|
|
|
|
config EDAC_AMD8111
|
|
|
|
tristate "AMD8111 HyperTransport I/O Hub"
|
|
|
|
tristate "AMD8111 HyperTransport I/O Hub"
|
|
|
|
depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
|
|
|
|
depends on PCI && PPC_MAPLE
|
|
|
|
help
|
|
|
|
help
|
|
|
|
Support for error detection and correction on the
|
|
|
|
Support for error detection and correction on the
|
|
|
|
AMD8111 HyperTransport I/O Hub chip.
|
|
|
|
AMD8111 HyperTransport I/O Hub chip.
|
|
|
@ -335,7 +321,7 @@ config EDAC_AMD8111
|
|
|
|
|
|
|
|
|
|
|
|
config EDAC_CPC925
|
|
|
|
config EDAC_CPC925
|
|
|
|
tristate "IBM CPC925 Memory Controller (PPC970FX)"
|
|
|
|
tristate "IBM CPC925 Memory Controller (PPC970FX)"
|
|
|
|
depends on EDAC_MM_EDAC && PPC64
|
|
|
|
depends on PPC64
|
|
|
|
help
|
|
|
|
help
|
|
|
|
Support for error detection and correction on the
|
|
|
|
Support for error detection and correction on the
|
|
|
|
IBM CPC925 Bridge and Memory Controller, which is
|
|
|
|
IBM CPC925 Bridge and Memory Controller, which is
|
|
|
@ -344,7 +330,7 @@ config EDAC_CPC925
|
|
|
|
|
|
|
|
|
|
|
|
config EDAC_TILE
|
|
|
|
config EDAC_TILE
|
|
|
|
tristate "Tilera Memory Controller"
|
|
|
|
tristate "Tilera Memory Controller"
|
|
|
|
depends on EDAC_MM_EDAC && TILE
|
|
|
|
depends on TILE
|
|
|
|
default y
|
|
|
|
default y
|
|
|
|
help
|
|
|
|
help
|
|
|
|
Support for error detection and correction on the
|
|
|
|
Support for error detection and correction on the
|
|
|
@ -352,49 +338,48 @@ config EDAC_TILE
|
|
|
|
|
|
|
|
|
|
|
|
config EDAC_HIGHBANK_MC
|
|
|
|
config EDAC_HIGHBANK_MC
|
|
|
|
tristate "Highbank Memory Controller"
|
|
|
|
tristate "Highbank Memory Controller"
|
|
|
|
depends on EDAC_MM_EDAC && ARCH_HIGHBANK
|
|
|
|
depends on ARCH_HIGHBANK
|
|
|
|
help
|
|
|
|
help
|
|
|
|
Support for error detection and correction on the
|
|
|
|
Support for error detection and correction on the
|
|
|
|
Calxeda Highbank memory controller.
|
|
|
|
Calxeda Highbank memory controller.
|
|
|
|
|
|
|
|
|
|
|
|
config EDAC_HIGHBANK_L2
|
|
|
|
config EDAC_HIGHBANK_L2
|
|
|
|
tristate "Highbank L2 Cache"
|
|
|
|
tristate "Highbank L2 Cache"
|
|
|
|
depends on EDAC_MM_EDAC && ARCH_HIGHBANK
|
|
|
|
depends on ARCH_HIGHBANK
|
|
|
|
help
|
|
|
|
help
|
|
|
|
Support for error detection and correction on the
|
|
|
|
Support for error detection and correction on the
|
|
|
|
Calxeda Highbank memory controller.
|
|
|
|
Calxeda Highbank memory controller.
|
|
|
|
|
|
|
|
|
|
|
|
config EDAC_OCTEON_PC
|
|
|
|
config EDAC_OCTEON_PC
|
|
|
|
tristate "Cavium Octeon Primary Caches"
|
|
|
|
tristate "Cavium Octeon Primary Caches"
|
|
|
|
depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
|
|
|
|
depends on CPU_CAVIUM_OCTEON
|
|
|
|
help
|
|
|
|
help
|
|
|
|
Support for error detection and correction on the primary caches of
|
|
|
|
Support for error detection and correction on the primary caches of
|
|
|
|
the cnMIPS cores of Cavium Octeon family SOCs.
|
|
|
|
the cnMIPS cores of Cavium Octeon family SOCs.
|
|
|
|
|
|
|
|
|
|
|
|
config EDAC_OCTEON_L2C
|
|
|
|
config EDAC_OCTEON_L2C
|
|
|
|
tristate "Cavium Octeon Secondary Caches (L2C)"
|
|
|
|
tristate "Cavium Octeon Secondary Caches (L2C)"
|
|
|
|
depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC
|
|
|
|
depends on CAVIUM_OCTEON_SOC
|
|
|
|
help
|
|
|
|
help
|
|
|
|
Support for error detection and correction on the
|
|
|
|
Support for error detection and correction on the
|
|
|
|
Cavium Octeon family of SOCs.
|
|
|
|
Cavium Octeon family of SOCs.
|
|
|
|
|
|
|
|
|
|
|
|
config EDAC_OCTEON_LMC
|
|
|
|
config EDAC_OCTEON_LMC
|
|
|
|
tristate "Cavium Octeon DRAM Memory Controller (LMC)"
|
|
|
|
tristate "Cavium Octeon DRAM Memory Controller (LMC)"
|
|
|
|
depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC
|
|
|
|
depends on CAVIUM_OCTEON_SOC
|
|
|
|
help
|
|
|
|
help
|
|
|
|
Support for error detection and correction on the
|
|
|
|
Support for error detection and correction on the
|
|
|
|
Cavium Octeon family of SOCs.
|
|
|
|
Cavium Octeon family of SOCs.
|
|
|
|
|
|
|
|
|
|
|
|
config EDAC_OCTEON_PCI
|
|
|
|
config EDAC_OCTEON_PCI
|
|
|
|
tristate "Cavium Octeon PCI Controller"
|
|
|
|
tristate "Cavium Octeon PCI Controller"
|
|
|
|
depends on EDAC_MM_EDAC && PCI && CAVIUM_OCTEON_SOC
|
|
|
|
depends on PCI && CAVIUM_OCTEON_SOC
|
|
|
|
help
|
|
|
|
help
|
|
|
|
Support for error detection and correction on the
|
|
|
|
Support for error detection and correction on the
|
|
|
|
Cavium Octeon family of SOCs.
|
|
|
|
Cavium Octeon family of SOCs.
|
|
|
|
|
|
|
|
|
|
|
|
config EDAC_THUNDERX
|
|
|
|
config EDAC_THUNDERX
|
|
|
|
tristate "Cavium ThunderX EDAC"
|
|
|
|
tristate "Cavium ThunderX EDAC"
|
|
|
|
depends on EDAC_MM_EDAC
|
|
|
|
|
|
|
|
depends on ARM64
|
|
|
|
depends on ARM64
|
|
|
|
depends on PCI
|
|
|
|
depends on PCI
|
|
|
|
help
|
|
|
|
help
|
|
|
@ -405,7 +390,7 @@ config EDAC_THUNDERX
|
|
|
|
|
|
|
|
|
|
|
|
config EDAC_ALTERA
|
|
|
|
config EDAC_ALTERA
|
|
|
|
bool "Altera SOCFPGA ECC"
|
|
|
|
bool "Altera SOCFPGA ECC"
|
|
|
|
depends on EDAC_MM_EDAC=y && ARCH_SOCFPGA
|
|
|
|
depends on EDAC=y && ARCH_SOCFPGA
|
|
|
|
help
|
|
|
|
help
|
|
|
|
Support for error detection and correction on the
|
|
|
|
Support for error detection and correction on the
|
|
|
|
Altera SOCs. This must be selected for SDRAM ECC.
|
|
|
|
Altera SOCs. This must be selected for SDRAM ECC.
|
|
|
@ -471,14 +456,14 @@ config EDAC_ALTERA_SDMMC
|
|
|
|
|
|
|
|
|
|
|
|
config EDAC_SYNOPSYS
|
|
|
|
config EDAC_SYNOPSYS
|
|
|
|
tristate "Synopsys DDR Memory Controller"
|
|
|
|
tristate "Synopsys DDR Memory Controller"
|
|
|
|
depends on EDAC_MM_EDAC && ARCH_ZYNQ
|
|
|
|
depends on ARCH_ZYNQ
|
|
|
|
help
|
|
|
|
help
|
|
|
|
Support for error detection and correction on the Synopsys DDR
|
|
|
|
Support for error detection and correction on the Synopsys DDR
|
|
|
|
memory controller.
|
|
|
|
memory controller.
|
|
|
|
|
|
|
|
|
|
|
|
config EDAC_XGENE
|
|
|
|
config EDAC_XGENE
|
|
|
|
tristate "APM X-Gene SoC"
|
|
|
|
tristate "APM X-Gene SoC"
|
|
|
|
depends on EDAC_MM_EDAC && (ARM64 || COMPILE_TEST)
|
|
|
|
depends on (ARM64 || COMPILE_TEST)
|
|
|
|
help
|
|
|
|
help
|
|
|
|
Support for error detection and correction on the
|
|
|
|
Support for error detection and correction on the
|
|
|
|
APM X-Gene family of SOCs.
|
|
|
|
APM X-Gene family of SOCs.
|
|
|
|