[AVR32] Make I/O access macros work with external devices
Fix the I/O access macros so that they work with externally connected devices accessed in little-endian mode over any bus width: * Use a set of macros to define I/O port- and memory operations borrowed from MIPS. * Allow subarchitecture to specify address- and data-mangling * Implement at32ap-specific port mangling (with build-time configurable bus width. Only one bus width at a time supported for now.) * Rewrite iowriteN and friends to use write[bwl] and friends (not the __raw counterparts.) This has been tested using pata_pcmcia to access a CompactFlash card connected to the EBI (16-bit bus width.) Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
This commit is contained in:
Haavard Skinnemoen
Родитель
92b728c147
Коммит
e3e7d8d4ea
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@ -2,6 +2,30 @@ if PLATFORM_AT32AP
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menu "Atmel AVR32 AP options"
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choice
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prompt "AT32AP7000 static memory bus width"
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depends on CPU_AT32AP7000
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default AP7000_16_BIT_SMC
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help
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Define the width of the AP7000 external static memory interface.
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This is used to determine how to mangle the address and/or data
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when doing little-endian port access.
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The current code can only support a single external memory bus
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width for all chip selects, excluding the flash (which is using
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raw access and is thus not affected by any of this.)
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config AP7000_32_BIT_SMC
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bool "32 bit"
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config AP7000_16_BIT_SMC
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bool "16 bit"
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config AP7000_8_BIT_SMC
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bool "8 bit"
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endchoice
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endmenu
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endif
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endif # PLATFORM_AT32AP
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@ -0,0 +1,39 @@
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#ifndef __ASM_AVR32_ARCH_AT32AP_IO_H
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#define __ASM_AVR32_ARCH_AT32AP_IO_H
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/* For "bizarre" halfword swapping */
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#include <linux/byteorder/swabb.h>
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#if defined(CONFIG_AP7000_32_BIT_SMC)
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# define __swizzle_addr_b(addr) (addr ^ 3UL)
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# define __swizzle_addr_w(addr) (addr ^ 2UL)
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# define __swizzle_addr_l(addr) (addr)
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# define ioswabb(a, x) (x)
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# define ioswabw(a, x) (x)
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# define ioswabl(a, x) (x)
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# define __mem_ioswabb(a, x) (x)
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# define __mem_ioswabw(a, x) swab16(x)
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# define __mem_ioswabl(a, x) swab32(x)
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#elif defined(CONFIG_AP7000_16_BIT_SMC)
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# define __swizzle_addr_b(addr) (addr ^ 1UL)
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# define __swizzle_addr_w(addr) (addr)
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# define __swizzle_addr_l(addr) (addr)
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# define ioswabb(a, x) (x)
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# define ioswabw(a, x) (x)
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# define ioswabl(a, x) swahw32(x)
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# define __mem_ioswabb(a, x) (x)
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# define __mem_ioswabw(a, x) swab16(x)
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# define __mem_ioswabl(a, x) swahb32(x)
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#else
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# define __swizzle_addr_b(addr) (addr)
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# define __swizzle_addr_w(addr) (addr)
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# define __swizzle_addr_l(addr) (addr)
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# define ioswabb(a, x) (x)
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# define ioswabw(a, x) swab16(x)
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# define ioswabl(a, x) swab32(x)
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# define __mem_ioswabb(a, x) (x)
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# define __mem_ioswabw(a, x) (x)
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# define __mem_ioswabl(a, x) (x)
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#endif
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#endif /* __ASM_AVR32_ARCH_AT32AP_IO_H */
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@ -1,13 +1,15 @@
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#ifndef __ASM_AVR32_IO_H
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#define __ASM_AVR32_IO_H
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#include <linux/kernel.h>
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#include <linux/string.h>
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#ifdef __KERNEL__
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#include <linux/types.h>
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#include <asm/addrspace.h>
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#include <asm/byteorder.h>
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#include <asm/arch/io.h>
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/* virt_to_phys will only work when address is in P1 or P2 */
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static __inline__ unsigned long virt_to_phys(volatile void *address)
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{
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@ -36,205 +38,236 @@ extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen);
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extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
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extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
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static inline void writeb(unsigned char b, volatile void __iomem *addr)
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static inline void __raw_writeb(u8 v, volatile void __iomem *addr)
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{
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*(volatile unsigned char __force *)addr = b;
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*(volatile u8 __force *)addr = v;
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}
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static inline void writew(unsigned short b, volatile void __iomem *addr)
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static inline void __raw_writew(u16 v, volatile void __iomem *addr)
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{
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*(volatile unsigned short __force *)addr = b;
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*(volatile u16 __force *)addr = v;
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}
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static inline void writel(unsigned int b, volatile void __iomem *addr)
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static inline void __raw_writel(u32 v, volatile void __iomem *addr)
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{
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*(volatile unsigned int __force *)addr = b;
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*(volatile u32 __force *)addr = v;
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}
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#define __raw_writeb writeb
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#define __raw_writew writew
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#define __raw_writel writel
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static inline unsigned char readb(const volatile void __iomem *addr)
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static inline u8 __raw_readb(const volatile void __iomem *addr)
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{
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return *(const volatile unsigned char __force *)addr;
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return *(const volatile u8 __force *)addr;
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}
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static inline unsigned short readw(const volatile void __iomem *addr)
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static inline u16 __raw_readw(const volatile void __iomem *addr)
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{
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return *(const volatile unsigned short __force *)addr;
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return *(const volatile u16 __force *)addr;
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}
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static inline unsigned int readl(const volatile void __iomem *addr)
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static inline u32 __raw_readl(const volatile void __iomem *addr)
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{
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return *(const volatile unsigned int __force *)addr;
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return *(const volatile u32 __force *)addr;
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}
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#define __raw_readb readb
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#define __raw_readw readw
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#define __raw_readl readl
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#define writesb(p, d, l) __raw_writesb((unsigned int)p, d, l)
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#define writesw(p, d, l) __raw_writesw((unsigned int)p, d, l)
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#define writesl(p, d, l) __raw_writesl((unsigned int)p, d, l)
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/* Convert I/O port address to virtual address */
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#ifndef __io
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# define __io(p) ((void *)phys_to_uncached(p))
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#endif
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#define readsb(p, d, l) __raw_readsb((unsigned int)p, d, l)
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#define readsw(p, d, l) __raw_readsw((unsigned int)p, d, l)
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#define readsl(p, d, l) __raw_readsl((unsigned int)p, d, l)
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/*
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* Not really sure about the best way to slow down I/O on
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* AVR32. Defining it as a no-op until we have an actual test case.
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*/
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#define SLOW_DOWN_IO do { } while (0)
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#define __BUILD_MEMORY_SINGLE(pfx, bwl, type) \
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static inline void \
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pfx##write##bwl(type val, volatile void __iomem *addr) \
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{ \
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volatile type *__addr; \
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type __val; \
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\
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__addr = (void *)__swizzle_addr_##bwl((unsigned long)(addr)); \
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__val = pfx##ioswab##bwl(__addr, val); \
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\
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BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
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\
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*__addr = __val; \
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} \
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\
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static inline type pfx##read##bwl(const volatile void __iomem *addr) \
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{ \
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volatile type *__addr; \
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type __val; \
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\
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__addr = (void *)__swizzle_addr_##bwl((unsigned long)(addr)); \
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\
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BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
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\
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__val = *__addr; \
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return pfx##ioswab##bwl(__addr, __val); \
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}
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#define __BUILD_IOPORT_SINGLE(pfx, bwl, type, p, slow) \
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static inline void pfx##out##bwl##p(type val, unsigned long port) \
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{ \
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volatile type *__addr; \
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type __val; \
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\
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__addr = __io(__swizzle_addr_##bwl(port)); \
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__val = pfx##ioswab##bwl(__addr, val); \
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\
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BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
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\
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*__addr = __val; \
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slow; \
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} \
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\
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static inline type pfx##in##bwl##p(unsigned long port) \
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{ \
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volatile type *__addr; \
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type __val; \
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\
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__addr = __io(__swizzle_addr_##bwl(port)); \
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\
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BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
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\
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__val = *__addr; \
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slow; \
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\
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return pfx##ioswab##bwl(__addr, __val); \
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}
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#define __BUILD_MEMORY_PFX(bus, bwl, type) \
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__BUILD_MEMORY_SINGLE(bus, bwl, type)
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#define BUILDIO_MEM(bwl, type) \
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__BUILD_MEMORY_PFX(, bwl, type) \
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__BUILD_MEMORY_PFX(__mem_, bwl, type)
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#define __BUILD_IOPORT_PFX(bus, bwl, type) \
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__BUILD_IOPORT_SINGLE(bus, bwl, type, ,) \
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__BUILD_IOPORT_SINGLE(bus, bwl, type, _p, SLOW_DOWN_IO)
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#define BUILDIO_IOPORT(bwl, type) \
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__BUILD_IOPORT_PFX(, bwl, type) \
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__BUILD_IOPORT_PFX(__mem_, bwl, type)
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BUILDIO_MEM(b, u8)
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BUILDIO_MEM(w, u16)
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BUILDIO_MEM(l, u32)
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BUILDIO_IOPORT(b, u8)
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BUILDIO_IOPORT(w, u16)
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BUILDIO_IOPORT(l, u32)
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#define readb_relaxed readb
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#define readw_relaxed readw
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#define readl_relaxed readl
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#define __BUILD_MEMORY_STRING(bwl, type) \
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static inline void writes##bwl(volatile void __iomem *addr, \
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const void *data, unsigned int count) \
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{ \
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const type *__data = data; \
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\
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while (count--) \
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__mem_write##bwl(*__data++, addr); \
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} \
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\
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static inline void reads##bwl(const volatile void __iomem *addr, \
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void *data, unsigned int count) \
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{ \
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type *__data = data; \
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\
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while (count--) \
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*__data++ = __mem_read##bwl(addr); \
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}
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#define __BUILD_IOPORT_STRING(bwl, type) \
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static inline void outs##bwl(unsigned long port, const void *data, \
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unsigned int count) \
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{ \
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const type *__data = data; \
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\
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while (count--) \
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__mem_out##bwl(*__data++, port); \
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} \
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\
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static inline void ins##bwl(unsigned long port, void *data, \
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unsigned int count) \
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{ \
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type *__data = data; \
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\
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while (count--) \
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*__data++ = __mem_in##bwl(port); \
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}
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#define BUILDSTRING(bwl, type) \
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__BUILD_MEMORY_STRING(bwl, type) \
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__BUILD_IOPORT_STRING(bwl, type)
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BUILDSTRING(b, u8)
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BUILDSTRING(w, u16)
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BUILDSTRING(l, u32)
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/*
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* io{read,write}{8,16,32} macros in both le (for PCI style consumers) and native be
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*/
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#ifndef ioread8
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#define ioread8(p) ({ unsigned int __v = __raw_readb(p); __v; })
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#define ioread8(p) ((unsigned int)readb(p))
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#define ioread16(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(p)); __v; })
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#define ioread16be(p) ({ unsigned int __v = be16_to_cpu(__raw_readw(p)); __v; })
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#define ioread16(p) ((unsigned int)readw(p))
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#define ioread16be(p) ((unsigned int)__raw_readw(p))
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#define ioread32(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(p)); __v; })
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#define ioread32be(p) ({ unsigned int __v = be32_to_cpu(__raw_readl(p)); __v; })
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#define ioread32(p) ((unsigned int)readl(p))
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#define ioread32be(p) ((unsigned int)__raw_readl(p))
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#define iowrite8(v,p) __raw_writeb(v, p)
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#define iowrite8(v,p) writeb(v, p)
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#define iowrite16(v,p) __raw_writew(cpu_to_le16(v), p)
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#define iowrite16be(v,p) __raw_writew(cpu_to_be16(v), p)
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#define iowrite16(v,p) writew(v, p)
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#define iowrite16be(v,p) __raw_writew(v, p)
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#define iowrite32(v,p) __raw_writel(cpu_to_le32(v), p)
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#define iowrite32be(v,p) __raw_writel(cpu_to_be32(v), p)
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#define iowrite32(v,p) writel(v, p)
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#define iowrite32be(v,p) __raw_writel(v, p)
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#define ioread8_rep(p,d,c) __raw_readsb(p,d,c)
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#define ioread16_rep(p,d,c) __raw_readsw(p,d,c)
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#define ioread32_rep(p,d,c) __raw_readsl(p,d,c)
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#define ioread8_rep(p,d,c) readsb(p,d,c)
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#define ioread16_rep(p,d,c) readsw(p,d,c)
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#define ioread32_rep(p,d,c) readsl(p,d,c)
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#define iowrite8_rep(p,s,c) __raw_writesb(p,s,c)
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#define iowrite16_rep(p,s,c) __raw_writesw(p,s,c)
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#define iowrite32_rep(p,s,c) __raw_writesl(p,s,c)
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#define iowrite8_rep(p,s,c) writesb(p,s,c)
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#define iowrite16_rep(p,s,c) writesw(p,s,c)
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#define iowrite32_rep(p,s,c) writesl(p,s,c)
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#endif
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/*
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* These two are only here because ALSA _thinks_ it needs them...
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*/
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static inline void memcpy_fromio(void * to, const volatile void __iomem *from,
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unsigned long count)
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{
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char *p = to;
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while (count) {
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count--;
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*p = readb(from);
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p++;
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from++;
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}
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volatile const char __iomem *addr = from;
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while (count--)
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*p++ = readb(addr++);
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}
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static inline void memcpy_toio(volatile void __iomem *to, const void * from,
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unsigned long count)
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{
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const char *p = from;
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while (count) {
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count--;
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writeb(*p, to);
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p++;
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to++;
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}
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volatile char __iomem *addr = to;
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while (count--)
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writeb(*p++, addr++);
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}
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|
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static inline void memset_io(volatile void __iomem *addr, unsigned char val,
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unsigned long count)
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{
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memset((void __force *)addr, val, count);
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}
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volatile char __iomem *p = addr;
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|
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/*
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* Bad read/write accesses...
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*/
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extern void __readwrite_bug(const char *fn);
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while (count--)
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writeb(val, p++);
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}
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|
||||
#define IO_SPACE_LIMIT 0xffffffff
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|
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/* Convert I/O port address to virtual address */
|
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#define __io(p) ((void __iomem *)phys_to_uncached(p))
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|
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/*
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* IO port access primitives
|
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* -------------------------
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*
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* The AVR32 doesn't have special IO access instructions; all IO is memory
|
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* mapped. Note that these are defined to perform little endian accesses
|
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* only. Their primary purpose is to access PCI and ISA peripherals.
|
||||
*
|
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* Note that for a big endian machine, this implies that the following
|
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* big endian mode connectivity is in place.
|
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*
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||||
* The machine specific io.h include defines __io to translate an "IO"
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* address to a memory address.
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*
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* Note that we prevent GCC re-ordering or caching values in expressions
|
||||
* by introducing sequence points into the in*() definitions. Note that
|
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* __raw_* do not guarantee this behaviour.
|
||||
*
|
||||
* The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
|
||||
*/
|
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#define outb(v, p) __raw_writeb(v, __io(p))
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#define outw(v, p) __raw_writew(cpu_to_le16(v), __io(p))
|
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#define outl(v, p) __raw_writel(cpu_to_le32(v), __io(p))
|
||||
|
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#define inb(p) __raw_readb(__io(p))
|
||||
#define inw(p) le16_to_cpu(__raw_readw(__io(p)))
|
||||
#define inl(p) le32_to_cpu(__raw_readl(__io(p)))
|
||||
|
||||
static inline void __outsb(unsigned long port, void *addr, unsigned int count)
|
||||
{
|
||||
while (count--) {
|
||||
outb(*(u8 *)addr, port);
|
||||
addr++;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void __insb(unsigned long port, void *addr, unsigned int count)
|
||||
{
|
||||
while (count--) {
|
||||
*(u8 *)addr = inb(port);
|
||||
addr++;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void __outsw(unsigned long port, void *addr, unsigned int count)
|
||||
{
|
||||
while (count--) {
|
||||
outw(*(u16 *)addr, port);
|
||||
addr += 2;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void __insw(unsigned long port, void *addr, unsigned int count)
|
||||
{
|
||||
while (count--) {
|
||||
*(u16 *)addr = inw(port);
|
||||
addr += 2;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void __outsl(unsigned long port, void *addr, unsigned int count)
|
||||
{
|
||||
while (count--) {
|
||||
outl(*(u32 *)addr, port);
|
||||
addr += 4;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void __insl(unsigned long port, void *addr, unsigned int count)
|
||||
{
|
||||
while (count--) {
|
||||
*(u32 *)addr = inl(port);
|
||||
addr += 4;
|
||||
}
|
||||
}
|
||||
|
||||
#define outsb(port, addr, count) __outsb(port, addr, count)
|
||||
#define insb(port, addr, count) __insb(port, addr, count)
|
||||
#define outsw(port, addr, count) __outsw(port, addr, count)
|
||||
#define insw(port, addr, count) __insw(port, addr, count)
|
||||
#define outsl(port, addr, count) __outsl(port, addr, count)
|
||||
#define insl(port, addr, count) __insl(port, addr, count)
|
||||
|
||||
extern void __iomem *__ioremap(unsigned long offset, size_t size,
|
||||
unsigned long flags);
|
||||
extern void __iounmap(void __iomem *addr);
|
||||
|
|
@ -292,6 +325,4 @@ extern void __iounmap(void __iomem *addr);
|
|||
*/
|
||||
#define xlate_dev_kmem_ptr(p) p
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#endif /* __ASM_AVR32_IO_H */
|
||||
|
|
|
|||
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