ARM: dts: Configure system timers for omap3
We can now init system timers using the dmtimer and 32k counter based on only devicetree data and drivers/clocksource timers. Let's configure the clocksource and clockevent, and drop the old unused platform data. As we're just dropping platform data, and the early platform data init is based on the custom ti,hwmods property, we want to drop both the platform data and ti,hwmods property in a single patch. Since the dmtimer can use both 32k clock and system clock as the source, let's also configure the SoC specific default values. The board specific dts files can reconfigure these with assigned-clocks and assigned-clock-parents as needed. Let's also update the dts file to use #include while at it. Cc: devicetree@vger.kernel.org Cc: Adam Ford <aford173@gmail.com> Cc: Andreas Kemnade <andreas@kemnade.info> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Cc: "H. Nikolaus Schaller" <hns@goldelico.com> Cc: Keerthy <j-keerthy@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Cc: Rob Herring <robh@kernel.org> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tony Lindgren
Родитель
036a3d42bb
Коммит
e428e250fd
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@ -169,5 +169,25 @@
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status = "disabled";
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};
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/include/ "am35xx-clocks.dtsi"
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/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
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#include "am35xx-clocks.dtsi"
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#include "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
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/* Preferred always-on timer for clocksource */
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&timer1_target {
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ti,no-reset-on-init;
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ti,no-idle;
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timer@0 {
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assigned-clocks = <&gpt1_fck>;
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assigned-clock-parents = <&sys_ck>;
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};
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};
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/* Preferred timer for clockevent */
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&timer2_target {
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ti,no-reset-on-init;
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ti,no-idle;
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timer@0 {
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assigned-clocks = <&gpt2_fck>;
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assigned-clock-parents = <&sys_ck>;
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};
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};
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@ -304,6 +304,39 @@
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phys = <0 &hsusb2_phy>;
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};
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/* Unusable as clocksource because of unreliable oscillator */
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&counter32k {
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status = "disabled";
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};
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/* Unusable as clockevent because if unreliable oscillator, allow to idle */
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&timer1_target {
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/delete-property/ti,no-reset-on-init;
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/delete-property/ti,no-idle;
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timer@0 {
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/delete-property/ti,timer-alwon;
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};
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};
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/* Preferred always-on timer for clocksource */
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&timer12_target {
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ti,no-reset-on-init;
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ti,no-idle;
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timer@0 {
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/* Always clocked by secure_32k_fck */
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};
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};
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/* Preferred timer for clockevent */
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&timer2_target {
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ti,no-reset-on-init;
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ti,no-idle;
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timer@0 {
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assigned-clocks = <&gpt2_fck>;
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assigned-clock-parents = <&sys_ck>;
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};
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};
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&twl_gpio {
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ti,use-leds;
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/* pullups: BIT(1) */
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@ -14,3 +14,36 @@
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display2 = &tv0;
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};
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};
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/* Unusable as clocksource because of unreliable oscillator */
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&counter32k {
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status = "disabled";
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};
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/* Unusable as clockevent because if unreliable oscillator, allow to idle */
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&timer1_target {
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/delete-property/ti,no-reset-on-init;
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/delete-property/ti,no-idle;
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timer@0 {
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/delete-property/ti,timer-alwon;
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};
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};
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/* Preferred always-on timer for clocksource */
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&timer12_target {
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ti,no-reset-on-init;
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ti,no-idle;
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timer@0 {
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/* Always clocked by secure_32k_fck */
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};
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};
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/* Preferred timer for clockevent */
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&timer2_target {
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ti,no-reset-on-init;
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ti,no-idle;
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timer@0 {
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assigned-clocks = <&gpt2_fck>;
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assigned-clock-parents = <&sys_ck>;
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};
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};
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@ -193,10 +193,23 @@
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};
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};
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counter32k: counter@48320000 {
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compatible = "ti,omap-counter32k";
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reg = <0x48320000 0x20>;
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ti,hwmods = "counter_32k";
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target-module@48320000 {
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compatible = "ti,sysc-omap2", "ti,sysc";
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reg = <0x48320000 0x4>,
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<0x48320004 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>;
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clocks = <&wkup_32k_fck>, <&omap_32ksync_ick>;
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clock-names = "fck", "ick";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x48320000 0x1000>;
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counter32k: counter@0 {
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compatible = "ti,omap-counter32k";
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reg = <0x0 0x20>;
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};
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};
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intc: interrupt-controller@48200000 {
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@ -637,19 +650,63 @@
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dma-names = "rx";
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};
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timer1: timer@48318000 {
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compatible = "ti,omap3430-timer";
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reg = <0x48318000 0x400>;
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interrupts = <37>;
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ti,hwmods = "timer1";
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ti,timer-alwon;
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timer1_target: target-module@48318000 {
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compatible = "ti,sysc-omap2-timer", "ti,sysc";
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reg = <0x48318000 0x4>,
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<0x48318010 0x4>,
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<0x48318014 0x4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
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SYSC_OMAP2_EMUFREE |
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SYSC_OMAP2_ENAWAKEUP |
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SYSC_OMAP2_SOFTRESET |
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SYSC_OMAP2_AUTOIDLE)>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,syss-mask = <1>;
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clocks = <&gpt1_fck>, <&gpt1_ick>;
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clock-names = "fck", "ick";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x48318000 0x1000>;
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timer1: timer@0 {
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compatible = "ti,omap3430-timer";
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reg = <0x0 0x80>;
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clocks = <&gpt1_fck>;
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clock-names = "fck";
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interrupts = <37>;
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ti,timer-alwon;
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};
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};
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timer2: timer@49032000 {
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compatible = "ti,omap3430-timer";
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reg = <0x49032000 0x400>;
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interrupts = <38>;
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ti,hwmods = "timer2";
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timer2_target: target-module@49032000 {
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compatible = "ti,sysc-omap2-timer", "ti,sysc";
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reg = <0x49032000 0x4>,
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<0x49032010 0x4>,
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<0x49032014 0x4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
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SYSC_OMAP2_EMUFREE |
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SYSC_OMAP2_ENAWAKEUP |
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SYSC_OMAP2_SOFTRESET |
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SYSC_OMAP2_AUTOIDLE)>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,syss-mask = <1>;
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clocks = <&gpt2_fck>, <&gpt2_ick>;
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clock-names = "fck", "ick";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x49032000 0x1000>;
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timer2: timer@0 {
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compatible = "ti,omap3430-timer";
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reg = <0 0x400>;
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interrupts = <38>;
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};
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};
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timer3: timer@49034000 {
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@ -723,13 +780,34 @@
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ti,timer-pwm;
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};
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timer12: timer@48304000 {
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compatible = "ti,omap3430-timer";
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reg = <0x48304000 0x400>;
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interrupts = <95>;
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ti,hwmods = "timer12";
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ti,timer-alwon;
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ti,timer-secure;
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timer12_target: target-module@48304000 {
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compatible = "ti,sysc-omap2-timer", "ti,sysc";
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reg = <0x48304000 0x4>,
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<0x48304010 0x4>,
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<0x48304014 0x4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
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SYSC_OMAP2_EMUFREE |
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SYSC_OMAP2_ENAWAKEUP |
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SYSC_OMAP2_SOFTRESET |
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SYSC_OMAP2_AUTOIDLE)>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,syss-mask = <1>;
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clocks = <&gpt12_fck>, <&gpt12_ick>;
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clock-names = "fck", "ick";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x48304000 0x1000>;
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timer12: timer@0 {
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compatible = "ti,omap3430-timer";
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reg = <0 0x400>;
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interrupts = <95>;
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ti,timer-alwon;
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ti,timer-secure;
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};
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};
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usbhstll: usbhstll@48062000 {
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@ -886,4 +964,14 @@
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};
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};
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/include/ "omap3xxx-clocks.dtsi"
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#include "omap3xxx-clocks.dtsi"
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/* Preferred always-on timer for clockevent. Some boards must use dmtimer12 */
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&timer1_target {
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ti,no-reset-on-init;
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ti,no-idle;
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timer@0 {
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assigned-clocks = <&gpt1_fck>;
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assigned-clock-parents = <&omap_32k_fck>;
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};
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};
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@ -114,7 +114,7 @@ DT_MACHINE_START(OMAP3_N900_DT, "Nokia RX-51 board")
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.init_early = omap3430_init_early,
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.init_machine = omap_generic_init,
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.init_late = omap3_init_late,
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.init_time = omap_init_time,
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.init_time = omap_init_time_of,
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.dt_compat = n900_boards_compat,
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.restart = omap3xxx_restart,
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MACHINE_END
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@ -132,7 +132,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
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.init_early = omap3430_init_early,
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.init_machine = omap_generic_init,
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.init_late = omap3_init_late,
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.init_time = omap_init_time,
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.init_time = omap_init_time_of,
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.dt_compat = omap3_boards_compat,
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.restart = omap3xxx_restart,
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MACHINE_END
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@ -149,7 +149,7 @@ DT_MACHINE_START(OMAP36XX_DT, "Generic OMAP36xx (Flattened Device Tree)")
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.init_early = omap3630_init_early,
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.init_machine = omap_generic_init,
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.init_late = omap3_init_late,
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.init_time = omap_init_time,
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.init_time = omap_init_time_of,
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.dt_compat = omap36xx_boards_compat,
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.restart = omap3xxx_restart,
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MACHINE_END
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@ -166,7 +166,7 @@ DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)")
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.init_early = omap3430_init_early,
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.init_machine = omap_generic_init,
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.init_late = omap3_init_late,
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.init_time = omap3_secure_sync32k_timer_init,
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.init_time = omap_init_time_of,
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.dt_compat = omap3_gp_boards_compat,
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.restart = omap3xxx_restart,
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MACHINE_END
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@ -182,7 +182,7 @@ DT_MACHINE_START(AM3517_DT, "Generic AM3517 (Flattened Device Tree)")
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.init_early = am35xx_init_early,
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.init_machine = omap_generic_init,
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.init_late = omap3_init_late,
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.init_time = omap3_gptimer_timer_init,
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.init_time = omap_init_time_of,
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.dt_compat = am3517_boards_compat,
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.restart = omap3xxx_restart,
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MACHINE_END
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@ -147,36 +147,6 @@ static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
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.sysc = &omap3xxx_timer_sysc,
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};
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/* timer1 */
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static struct omap_hwmod omap3xxx_timer1_hwmod = {
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.name = "timer1",
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.main_clk = "gpt1_fck",
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.prcm = {
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.omap2 = {
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.module_offs = WKUP_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
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},
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},
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.class = &omap3xxx_timer_hwmod_class,
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.flags = HWMOD_SET_DEFAULT_CLOCKACT,
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};
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/* timer2 */
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static struct omap_hwmod omap3xxx_timer2_hwmod = {
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.name = "timer2",
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.main_clk = "gpt2_fck",
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.prcm = {
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.omap2 = {
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.module_offs = OMAP3430_PER_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
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},
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},
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.class = &omap3xxx_timer_hwmod_class,
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.flags = HWMOD_SET_DEFAULT_CLOCKACT,
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};
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/* timer3 */
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static struct omap_hwmod omap3xxx_timer3_hwmod = {
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.name = "timer3",
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@ -312,21 +282,6 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
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.flags = HWMOD_SET_DEFAULT_CLOCKACT,
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};
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/* timer12 */
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static struct omap_hwmod omap3xxx_timer12_hwmod = {
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.name = "timer12",
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.main_clk = "gpt12_fck",
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.prcm = {
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.omap2 = {
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.module_offs = WKUP_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
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},
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},
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.class = &omap3xxx_timer_hwmod_class,
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.flags = HWMOD_SET_DEFAULT_CLOCKACT,
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};
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/*
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* 'wd_timer' class
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* 32-bit watchdog upward counter that generates a pulse on the reset pin on
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@ -1524,38 +1479,6 @@ static struct omap_hwmod omap3xxx_sad2d_hwmod = {
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.class = &omap3xxx_sad2d_class,
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};
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/*
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* '32K sync counter' class
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* 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
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*/
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static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0004,
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.sysc_flags = SYSC_HAS_SIDLEMODE,
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.idlemodes = (SIDLE_FORCE | SIDLE_NO),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
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.name = "counter",
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.sysc = &omap3xxx_counter_sysc,
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};
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static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
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.name = "counter_32k",
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.class = &omap3xxx_counter_hwmod_class,
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.clkdm_name = "wkup_clkdm",
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.flags = HWMOD_SWSUP_SIDLE,
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.main_clk = "wkup_32k_fck",
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.prcm = {
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.omap2 = {
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.module_offs = WKUP_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
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},
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},
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};
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/*
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* 'gpmc' class
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* general purpose memory controller
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@ -1868,25 +1791,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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||||
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||||
/* l4_wkup -> timer1 */
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static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
|
||||
.master = &omap3xxx_l4_wkup_hwmod,
|
||||
.slave = &omap3xxx_timer1_hwmod,
|
||||
.clk = "gpt1_ick",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
|
||||
/* l4_per -> timer2 */
|
||||
static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
|
||||
.master = &omap3xxx_l4_per_hwmod,
|
||||
.slave = &omap3xxx_timer2_hwmod,
|
||||
.clk = "gpt2_ick",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
|
||||
/* l4_per -> timer3 */
|
||||
static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
|
||||
.master = &omap3xxx_l4_per_hwmod,
|
||||
|
|
@ -1965,15 +1869,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
|
|||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
|
||||
/* l4_core -> timer12 */
|
||||
static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
|
||||
.master = &omap3xxx_l4_sec_hwmod,
|
||||
.slave = &omap3xxx_timer12_hwmod,
|
||||
.clk = "gpt12_ick",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_wkup -> wd_timer2 */
|
||||
|
||||
static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
|
||||
|
|
@ -2325,16 +2220,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
|
|||
.flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
|
||||
};
|
||||
|
||||
/* l4_wkup -> 32ksync_counter */
|
||||
|
||||
|
||||
static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
|
||||
.master = &omap3xxx_l4_wkup_hwmod,
|
||||
.slave = &omap3xxx_counter_32k_hwmod,
|
||||
.clk = "omap_32ksync_ick",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* am35xx has Davinci MDIO & EMAC */
|
||||
static struct omap_hwmod_class am35xx_mdio_class = {
|
||||
.name = "davinci_mdio",
|
||||
|
|
@ -2551,8 +2436,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
|
|||
&omap3_l4_core__i2c2,
|
||||
&omap3_l4_core__i2c3,
|
||||
&omap3xxx_l4_wkup__l4_sec,
|
||||
&omap3xxx_l4_wkup__timer1,
|
||||
&omap3xxx_l4_per__timer2,
|
||||
&omap3xxx_l4_per__timer3,
|
||||
&omap3xxx_l4_per__timer4,
|
||||
&omap3xxx_l4_per__timer5,
|
||||
|
|
@ -2580,27 +2463,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
|
|||
&omap34xx_l4_core__mcspi2,
|
||||
&omap34xx_l4_core__mcspi3,
|
||||
&omap34xx_l4_core__mcspi4,
|
||||
&omap3xxx_l4_wkup__counter_32k,
|
||||
&omap3xxx_l3_main__gpmc,
|
||||
NULL,
|
||||
};
|
||||
|
||||
/* GP-only hwmod links */
|
||||
static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
|
||||
&omap3xxx_l4_sec__timer12,
|
||||
NULL,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
|
||||
&omap3xxx_l4_sec__timer12,
|
||||
NULL,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
|
||||
&omap3xxx_l4_sec__timer12,
|
||||
NULL,
|
||||
};
|
||||
|
||||
/* crypto hwmod links */
|
||||
static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = {
|
||||
&omap3xxx_l4_core__sham,
|
||||
|
|
@ -2774,7 +2640,7 @@ static bool __init omap3xxx_hwmod_is_hs_ip_block_usable(struct device_node *bus,
|
|||
int __init omap3xxx_hwmod_init(void)
|
||||
{
|
||||
int r;
|
||||
struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL, **h_sham = NULL;
|
||||
struct omap_hwmod_ocp_if **h = NULL, **h_sham = NULL;
|
||||
struct omap_hwmod_ocp_if **h_aes = NULL;
|
||||
struct device_node *bus;
|
||||
unsigned int rev;
|
||||
|
|
@ -2797,18 +2663,15 @@ int __init omap3xxx_hwmod_init(void)
|
|||
rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
|
||||
rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
|
||||
h = omap34xx_hwmod_ocp_ifs;
|
||||
h_gp = omap34xx_gp_hwmod_ocp_ifs;
|
||||
h_sham = omap34xx_sham_hwmod_ocp_ifs;
|
||||
h_aes = omap34xx_aes_hwmod_ocp_ifs;
|
||||
} else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
|
||||
h = am35xx_hwmod_ocp_ifs;
|
||||
h_gp = am35xx_gp_hwmod_ocp_ifs;
|
||||
h_sham = am35xx_sham_hwmod_ocp_ifs;
|
||||
h_aes = am35xx_aes_hwmod_ocp_ifs;
|
||||
} else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
|
||||
rev == OMAP3630_REV_ES1_2) {
|
||||
h = omap36xx_hwmod_ocp_ifs;
|
||||
h_gp = omap36xx_gp_hwmod_ocp_ifs;
|
||||
h_sham = omap36xx_sham_hwmod_ocp_ifs;
|
||||
h_aes = omap36xx_aes_hwmod_ocp_ifs;
|
||||
} else {
|
||||
|
|
@ -2820,13 +2683,6 @@ int __init omap3xxx_hwmod_init(void)
|
|||
if (r < 0)
|
||||
return r;
|
||||
|
||||
/* Register GP-only hwmod links. */
|
||||
if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) {
|
||||
r = omap_hwmod_register_links(h_gp);
|
||||
if (r < 0)
|
||||
return r;
|
||||
}
|
||||
|
||||
/*
|
||||
* Register crypto hwmod links only if they are not disabled in DT.
|
||||
* If DT information is missing, enable them only for GP devices.
|
||||
|
|
|
|||
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