media: rc: ir-hix5hd2: add hi3796cv300-ir support
The IR device on Hi3796CV300 SoC is mostly same as hix5hd2, except the following two things. - IR_CLK offset is 0x60 instead of 0x48. - It needs to set an extra bit in IR_ENABLE register to enable IR. The following changes are made to deal with them. - Define a SoC specific data to accommodate IR_CLK offset and the flag telling requirement of extra enable bit. - Create function hix5hd2_ir_enable() to handle IR enabling. The original hix5hd2_ir_enable() is all about managing IR clock, so gets renamed to hix5hd2_ir_clk_enable(). - Device table hix5hd2_ir_table[] gets moved forward, as it's being used by hix5hd2_ir_probe() now. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Sean Young <sean@mess.org> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
This commit is contained in:
Shawn Guo
Mauro Carvalho Chehab
Родитель
61cd2d5ca0
Коммит
e4b9b6454d
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@ -37,10 +37,13 @@
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#define INT_CLR_RCV BIT(16)
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#define INT_CLR_RCVTIMEOUT (BIT(16) | BIT(17))
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#define IR_CLK 0x48
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#define IR_CLK_ENABLE BIT(4)
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#define IR_CLK_RESET BIT(5)
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/* IR_ENABLE register bits */
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#define IR_ENABLE_EN BIT(0)
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#define IR_ENABLE_EN_EXTRA BIT(8)
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#define IR_CFG_WIDTH_MASK 0xffff
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#define IR_CFG_WIDTH_SHIFT 16
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#define IR_CFG_FORMAT_MASK 0x3
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@ -58,6 +61,23 @@
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#define IR_HIX5HD2_NAME "hix5hd2-ir"
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/* Need to set extra bit for enabling IR */
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#define HIX5HD2_FLAG_EXTRA_ENABLE BIT(0)
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struct hix5hd2_soc_data {
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u32 clk_reg;
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u32 flags;
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};
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static const struct hix5hd2_soc_data hix5hd2_data = {
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.clk_reg = 0x48,
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};
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static const struct hix5hd2_soc_data hi3796cv300_data = {
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.clk_reg = 0x60,
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.flags = HIX5HD2_FLAG_EXTRA_ENABLE,
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};
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struct hix5hd2_ir_priv {
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int irq;
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void __iomem *base;
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@ -66,15 +86,17 @@ struct hix5hd2_ir_priv {
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struct regmap *regmap;
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struct clk *clock;
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unsigned long rate;
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const struct hix5hd2_soc_data *socdata;
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};
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static int hix5hd2_ir_enable(struct hix5hd2_ir_priv *dev, bool on)
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static int hix5hd2_ir_clk_enable(struct hix5hd2_ir_priv *dev, bool on)
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{
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u32 clk_reg = dev->socdata->clk_reg;
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u32 val;
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int ret = 0;
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if (dev->regmap) {
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regmap_read(dev->regmap, IR_CLK, &val);
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regmap_read(dev->regmap, clk_reg, &val);
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if (on) {
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val &= ~IR_CLK_RESET;
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val |= IR_CLK_ENABLE;
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@ -82,7 +104,7 @@ static int hix5hd2_ir_enable(struct hix5hd2_ir_priv *dev, bool on)
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val &= ~IR_CLK_ENABLE;
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val |= IR_CLK_RESET;
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}
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regmap_write(dev->regmap, IR_CLK, val);
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regmap_write(dev->regmap, clk_reg, val);
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} else {
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if (on)
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ret = clk_prepare_enable(dev->clock);
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@ -92,12 +114,23 @@ static int hix5hd2_ir_enable(struct hix5hd2_ir_priv *dev, bool on)
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return ret;
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}
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static inline void hix5hd2_ir_enable(struct hix5hd2_ir_priv *priv)
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{
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u32 val = IR_ENABLE_EN;
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if (priv->socdata->flags & HIX5HD2_FLAG_EXTRA_ENABLE)
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val |= IR_ENABLE_EN_EXTRA;
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writel_relaxed(val, priv->base + IR_ENABLE);
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}
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static int hix5hd2_ir_config(struct hix5hd2_ir_priv *priv)
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{
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int timeout = 10000;
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u32 val, rate;
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writel_relaxed(0x01, priv->base + IR_ENABLE);
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hix5hd2_ir_enable(priv);
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while (readl_relaxed(priv->base + IR_BUSY)) {
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if (timeout--) {
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udelay(1);
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@ -128,13 +161,13 @@ static int hix5hd2_ir_open(struct rc_dev *rdev)
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struct hix5hd2_ir_priv *priv = rdev->priv;
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int ret;
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ret = hix5hd2_ir_enable(priv, true);
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ret = hix5hd2_ir_clk_enable(priv, true);
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if (ret)
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return ret;
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ret = hix5hd2_ir_config(priv);
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if (ret) {
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hix5hd2_ir_enable(priv, false);
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hix5hd2_ir_clk_enable(priv, false);
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return ret;
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}
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return 0;
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@ -144,7 +177,7 @@ static void hix5hd2_ir_close(struct rc_dev *rdev)
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{
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struct hix5hd2_ir_priv *priv = rdev->priv;
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hix5hd2_ir_enable(priv, false);
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hix5hd2_ir_clk_enable(priv, false);
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}
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static irqreturn_t hix5hd2_ir_rx_interrupt(int irq, void *data)
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@ -205,6 +238,13 @@ static irqreturn_t hix5hd2_ir_rx_interrupt(int irq, void *data)
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return IRQ_HANDLED;
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}
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static const struct of_device_id hix5hd2_ir_table[] = {
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{ .compatible = "hisilicon,hix5hd2-ir", &hix5hd2_data, },
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{ .compatible = "hisilicon,hi3796cv300-ir", &hi3796cv300_data, },
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{},
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};
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MODULE_DEVICE_TABLE(of, hix5hd2_ir_table);
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static int hix5hd2_ir_probe(struct platform_device *pdev)
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{
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struct rc_dev *rdev;
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@ -212,6 +252,7 @@ static int hix5hd2_ir_probe(struct platform_device *pdev)
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struct resource *res;
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struct hix5hd2_ir_priv *priv;
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struct device_node *node = pdev->dev.of_node;
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const struct of_device_id *of_id;
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const char *map_name;
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int ret;
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@ -219,6 +260,13 @@ static int hix5hd2_ir_probe(struct platform_device *pdev)
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if (!priv)
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return -ENOMEM;
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of_id = of_match_device(hix5hd2_ir_table, dev);
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if (!of_id) {
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dev_err(dev, "Unable to initialize IR data\n");
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return -ENODEV;
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}
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priv->socdata = of_id->data;
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priv->regmap = syscon_regmap_lookup_by_phandle(node,
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"hisilicon,power-syscon");
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if (IS_ERR(priv->regmap)) {
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@ -309,7 +357,7 @@ static int hix5hd2_ir_suspend(struct device *dev)
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struct hix5hd2_ir_priv *priv = dev_get_drvdata(dev);
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clk_disable_unprepare(priv->clock);
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hix5hd2_ir_enable(priv, false);
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hix5hd2_ir_clk_enable(priv, false);
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return 0;
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}
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@ -319,17 +367,18 @@ static int hix5hd2_ir_resume(struct device *dev)
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struct hix5hd2_ir_priv *priv = dev_get_drvdata(dev);
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int ret;
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ret = hix5hd2_ir_enable(priv, true);
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ret = hix5hd2_ir_clk_enable(priv, true);
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if (ret)
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return ret;
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ret = clk_prepare_enable(priv->clock);
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if (ret) {
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hix5hd2_ir_enable(priv, false);
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hix5hd2_ir_clk_enable(priv, false);
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return ret;
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}
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writel_relaxed(0x01, priv->base + IR_ENABLE);
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hix5hd2_ir_enable(priv);
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writel_relaxed(0x00, priv->base + IR_INTM);
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writel_relaxed(0xff, priv->base + IR_INTC);
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writel_relaxed(0x01, priv->base + IR_START);
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@ -341,12 +390,6 @@ static int hix5hd2_ir_resume(struct device *dev)
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static SIMPLE_DEV_PM_OPS(hix5hd2_ir_pm_ops, hix5hd2_ir_suspend,
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hix5hd2_ir_resume);
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static const struct of_device_id hix5hd2_ir_table[] = {
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{ .compatible = "hisilicon,hix5hd2-ir", },
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{},
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};
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MODULE_DEVICE_TABLE(of, hix5hd2_ir_table);
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static struct platform_driver hix5hd2_ir_driver = {
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.driver = {
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.name = IR_HIX5HD2_NAME,
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