This patch modifies the psc and clock control code to use ioremap()ed
registers.

Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This commit is contained in:
Cyril Chemparathy 2010-05-07 17:06:36 -04:00 коммит произвёл Kevin Hilman
Родитель 1bcd38ad2d
Коммит e4c822c7e9
9 изменённых файлов: 23 добавлений и 26 удалений

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@ -302,7 +302,6 @@ static unsigned long clk_pllclk_recalc(struct clk *clk)
struct pll_data *pll = clk->pll_data;
unsigned long rate = clk->rate;
pll->base = IO_ADDRESS(pll->phys_base);
ctrl = __raw_readl(pll->base + PLLCTL);
rate = pll->input_rate = clk->parent->rate;
@ -458,8 +457,17 @@ int __init davinci_clk_init(struct clk_lookup *clocks)
clk->recalc = clk_leafclk_recalc;
}
if (clk->pll_data && !clk->pll_data->div_ratio_mask)
clk->pll_data->div_ratio_mask = PLLDIV_RATIO_MASK;
if (clk->pll_data) {
struct pll_data *pll = clk->pll_data;
if (!pll->div_ratio_mask)
pll->div_ratio_mask = PLLDIV_RATIO_MASK;
if (pll->phys_base && !pll->base) {
pll->base = ioremap(pll->phys_base, SZ_4K);
WARN_ON(!pll->base);
}
}
if (clk->recalc)
clk->rate = clk->recalc(clk);

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@ -1127,10 +1127,7 @@ static struct map_desc da830_io_desc[] = {
},
};
static void __iomem *da830_psc_bases[] = {
IO_ADDRESS(DA8XX_PSC0_BASE),
IO_ADDRESS(DA8XX_PSC1_BASE),
};
static u32 da830_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
/* Contents of JTAG ID register used to identify exact cpu type */
static struct davinci_id da830_ids[] = {

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@ -782,10 +782,7 @@ static struct map_desc da850_io_desc[] = {
},
};
static void __iomem *da850_psc_bases[] = {
IO_ADDRESS(DA8XX_PSC0_BASE),
IO_ADDRESS(DA8XX_PSC1_BASE),
};
static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
/* Contents of JTAG ID register used to identify exact cpu type */
static struct davinci_id da850_ids[] = {

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@ -783,9 +783,7 @@ static struct davinci_id dm355_ids[] = {
},
};
static void __iomem *dm355_psc_bases[] = {
IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
};
static u32 dm355_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
/*
* T0_BOT: Timer 0, bottom: clockevent source for hrtimers

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@ -1002,9 +1002,7 @@ static struct davinci_id dm365_ids[] = {
},
};
static void __iomem *dm365_psc_bases[] = {
IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
};
static u32 dm365_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
static struct davinci_timer_info dm365_timer_info = {
.timers = davinci_timer_instance,

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@ -674,9 +674,7 @@ static struct davinci_id dm644x_ids[] = {
},
};
static void __iomem *dm644x_psc_bases[] = {
IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
};
static u32 dm644x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
/*
* T0_BOT: Timer 0, bottom: clockevent source for hrtimers

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@ -758,9 +758,7 @@ static struct davinci_id dm646x_ids[] = {
},
};
static void __iomem *dm646x_psc_bases[] = {
IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
};
static u32 dm646x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
/*
* T0_BOT: Timer 0, bottom: clockevent source for hrtimers

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@ -49,7 +49,7 @@ struct davinci_soc_info {
struct davinci_id *ids;
unsigned long ids_num;
struct clk_lookup *cpu_clks;
void __iomem **psc_bases;
u32 *psc_bases;
unsigned long psc_bases_num;
void __iomem *pinmux_base;
const struct mux_config *pinmux_pins;

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@ -38,8 +38,9 @@ int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)
return 0;
}
psc_base = soc_info->psc_bases[ctlr];
psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K);
mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
iounmap(psc_base);
/* if clocked, state can be "Enable" or "SyncReset" */
return mdstat & BIT(12);
@ -59,7 +60,7 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr,
return;
}
psc_base = soc_info->psc_bases[ctlr];
psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K);
mdctl = __raw_readl(psc_base + MDCTL + 4 * id);
mdctl &= ~MDSTAT_STATE_MASK;
@ -99,4 +100,6 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr,
do {
mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
} while (!((mdstat & MDSTAT_STATE_MASK) == next_state));
iounmap(psc_base);
}