drm/i915: Split out parking from the idle worker for reuse
We will want to park GEM before disengaging the drive^W^W^W unwedging. Since we already do the work for idling, expose the guts as a new function that we can then reuse. v2: Just skip if already parked; makes it more forgiving to use by future callers. v3: Extract mark_busy, rename it to i915_gem_unpark and place it next to i915_gem_park so that we can evaluate it for symmetry more easily. Calling GEM from inside i915_request looks to be a bit of a layering violation, for the moment I am imaging them as being notify_cb. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> #v1 Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180406155144.27791-1-chris@chris-wilson.co.uk
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Chris Wilson
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e4d2006f8f
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@ -136,6 +136,100 @@ int i915_mutex_lock_interruptible(struct drm_device *dev)
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return 0;
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}
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static u32 __i915_gem_park(struct drm_i915_private *i915)
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{
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lockdep_assert_held(&i915->drm.struct_mutex);
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GEM_BUG_ON(i915->gt.active_requests);
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if (!i915->gt.awake)
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return I915_EPOCH_INVALID;
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GEM_BUG_ON(i915->gt.epoch == I915_EPOCH_INVALID);
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/*
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* Be paranoid and flush a concurrent interrupt to make sure
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* we don't reactivate any irq tasklets after parking.
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*
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* FIXME: Note that even though we have waited for execlists to be idle,
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* there may still be an in-flight interrupt even though the CSB
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* is now empty. synchronize_irq() makes sure that a residual interrupt
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* is completed before we continue, but it doesn't prevent the HW from
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* raising a spurious interrupt later. To complete the shield we should
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* coordinate disabling the CS irq with flushing the interrupts.
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*/
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synchronize_irq(i915->drm.irq);
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intel_engines_park(i915);
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i915_gem_timelines_park(i915);
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i915_pmu_gt_parked(i915);
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i915->gt.awake = false;
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if (INTEL_GEN(i915) >= 6)
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gen6_rps_idle(i915);
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intel_display_power_put(i915, POWER_DOMAIN_GT_IRQ);
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intel_runtime_pm_put(i915);
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return i915->gt.epoch;
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}
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void i915_gem_park(struct drm_i915_private *i915)
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{
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lockdep_assert_held(&i915->drm.struct_mutex);
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GEM_BUG_ON(i915->gt.active_requests);
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if (!i915->gt.awake)
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return;
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/* Defer the actual call to __i915_gem_park() to prevent ping-pongs */
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mod_delayed_work(i915->wq, &i915->gt.idle_work, msecs_to_jiffies(100));
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}
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void i915_gem_unpark(struct drm_i915_private *i915)
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{
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lockdep_assert_held(&i915->drm.struct_mutex);
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GEM_BUG_ON(!i915->gt.active_requests);
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if (i915->gt.awake)
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return;
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intel_runtime_pm_get_noresume(i915);
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/*
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* It seems that the DMC likes to transition between the DC states a lot
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* when there are no connected displays (no active power domains) during
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* command submission.
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*
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* This activity has negative impact on the performance of the chip with
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* huge latencies observed in the interrupt handler and elsewhere.
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*
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* Work around it by grabbing a GT IRQ power domain whilst there is any
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* GT activity, preventing any DC state transitions.
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*/
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intel_display_power_get(i915, POWER_DOMAIN_GT_IRQ);
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i915->gt.awake = true;
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if (unlikely(++i915->gt.epoch == 0)) /* keep 0 as invalid */
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i915->gt.epoch = 1;
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intel_enable_gt_powersave(i915);
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i915_update_gfx_val(i915);
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if (INTEL_GEN(i915) >= 6)
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gen6_rps_busy(i915);
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i915_pmu_gt_unparked(i915);
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intel_engines_unpark(i915);
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i915_queue_hangcheck(i915);
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queue_delayed_work(i915->wq,
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&i915->gt.retire_work,
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round_jiffies_up_relative(HZ));
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}
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int
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i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file)
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@ -3496,36 +3590,9 @@ i915_gem_idle_work_handler(struct work_struct *work)
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if (new_requests_since_last_retire(dev_priv))
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goto out_unlock;
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/*
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* Be paranoid and flush a concurrent interrupt to make sure
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* we don't reactivate any irq tasklets after parking.
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*
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* FIXME: Note that even though we have waited for execlists to be idle,
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* there may still be an in-flight interrupt even though the CSB
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* is now empty. synchronize_irq() makes sure that a residual interrupt
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* is completed before we continue, but it doesn't prevent the HW from
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* raising a spurious interrupt later. To complete the shield we should
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* coordinate disabling the CS irq with flushing the interrupts.
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*/
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synchronize_irq(dev_priv->drm.irq);
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epoch = __i915_gem_park(dev_priv);
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intel_engines_park(dev_priv);
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i915_gem_timelines_park(dev_priv);
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i915_pmu_gt_parked(dev_priv);
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GEM_BUG_ON(!dev_priv->gt.awake);
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dev_priv->gt.awake = false;
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epoch = dev_priv->gt.epoch;
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GEM_BUG_ON(epoch == I915_EPOCH_INVALID);
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rearm_hangcheck = false;
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if (INTEL_GEN(dev_priv) >= 6)
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gen6_rps_idle(dev_priv);
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intel_display_power_put(dev_priv, POWER_DOMAIN_GT_IRQ);
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intel_runtime_pm_put(dev_priv);
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out_unlock:
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mutex_unlock(&dev_priv->drm.struct_mutex);
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@ -27,6 +27,8 @@
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#include <linux/bug.h>
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struct drm_i915_private;
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#ifdef CONFIG_DRM_I915_DEBUG_GEM
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#define GEM_BUG_ON(condition) do { if (unlikely((condition))) { \
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pr_err("%s:%d GEM_BUG_ON(%s)\n", \
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@ -61,4 +63,7 @@
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#define I915_NUM_ENGINES 8
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void i915_gem_park(struct drm_i915_private *i915);
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void i915_gem_unpark(struct drm_i915_private *i915);
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#endif /* __I915_GEM_H__ */
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@ -255,47 +255,6 @@ int i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno)
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return reset_all_global_seqno(i915, seqno - 1);
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}
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static void mark_busy(struct drm_i915_private *i915)
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{
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if (i915->gt.awake)
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return;
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GEM_BUG_ON(!i915->gt.active_requests);
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intel_runtime_pm_get_noresume(i915);
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/*
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* It seems that the DMC likes to transition between the DC states a lot
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* when there are no connected displays (no active power domains) during
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* command submission.
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*
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* This activity has negative impact on the performance of the chip with
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* huge latencies observed in the interrupt handler and elsewhere.
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*
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* Work around it by grabbing a GT IRQ power domain whilst there is any
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* GT activity, preventing any DC state transitions.
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*/
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intel_display_power_get(i915, POWER_DOMAIN_GT_IRQ);
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i915->gt.awake = true;
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if (unlikely(++i915->gt.epoch == 0)) /* keep 0 as invalid */
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i915->gt.epoch = 1;
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intel_enable_gt_powersave(i915);
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i915_update_gfx_val(i915);
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if (INTEL_GEN(i915) >= 6)
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gen6_rps_busy(i915);
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i915_pmu_gt_unparked(i915);
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intel_engines_unpark(i915);
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i915_queue_hangcheck(i915);
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queue_delayed_work(i915->wq,
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&i915->gt.retire_work,
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round_jiffies_up_relative(HZ));
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}
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static int reserve_engine(struct intel_engine_cs *engine)
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{
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struct drm_i915_private *i915 = engine->i915;
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@ -313,7 +272,7 @@ static int reserve_engine(struct intel_engine_cs *engine)
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}
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if (!i915->gt.active_requests++)
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mark_busy(i915);
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i915_gem_unpark(i915);
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return 0;
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}
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@ -322,13 +281,8 @@ static void unreserve_engine(struct intel_engine_cs *engine)
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{
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struct drm_i915_private *i915 = engine->i915;
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if (!--i915->gt.active_requests) {
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/* Cancel the mark_busy() from our reserve_engine() */
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GEM_BUG_ON(!i915->gt.awake);
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mod_delayed_work(i915->wq,
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&i915->gt.idle_work,
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msecs_to_jiffies(100));
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}
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if (!--i915->gt.active_requests)
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i915_gem_park(i915);
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GEM_BUG_ON(!engine->timeline->inflight_seqnos);
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engine->timeline->inflight_seqnos--;
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