KVM: PPC: Book3S HV: Add transactional memory support
This adds saving of the transactional memory (TM) checkpointed state on guest entry and exit. We only do this if we see that the guest has an active transaction. It also adds emulation of the TM state changes when delivering IRQs into the guest. According to the architecture, if we are transactional when an IRQ occurs, the TM state is changed to suspended, otherwise it's left unchanged. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Paul Mackerras <paulus@samba.org> Acked-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
Michael Neuling
Paul Mackerras
Родитель
7505258c5f
Коммит
e4e3812150
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@ -213,6 +213,7 @@
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#define SPRN_ACOP 0x1F /* Available Coprocessor Register */
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#define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */
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#define SPRN_TEXASR 0x82 /* Transaction EXception & Summary */
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#define TEXASR_FS __MASK(63-36) /* Transaction Failure Summary */
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#define SPRN_TEXASRU 0x83 /* '' '' '' Upper 32 */
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#define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */
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#define SPRN_CTRLF 0x088
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@ -7,6 +7,8 @@
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#include <uapi/asm/tm.h>
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#ifndef __ASSEMBLY__
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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extern void do_load_up_transact_fpu(struct thread_struct *thread);
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extern void do_load_up_transact_altivec(struct thread_struct *thread);
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@ -20,3 +22,5 @@ extern void tm_recheckpoint(struct thread_struct *thread,
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extern void tm_abort(uint8_t cause);
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extern void tm_save_sprs(struct thread_struct *thread);
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extern void tm_restore_sprs(struct thread_struct *thread);
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#endif /* __ASSEMBLY__ */
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@ -262,7 +262,14 @@ int kvmppc_mmu_hv_init(void)
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static void kvmppc_mmu_book3s_64_hv_reset_msr(struct kvm_vcpu *vcpu)
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{
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kvmppc_set_msr(vcpu, vcpu->arch.intr_msr);
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unsigned long msr = vcpu->arch.intr_msr;
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/* If transactional, change to suspend mode on IRQ delivery */
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if (MSR_TM_TRANSACTIONAL(vcpu->arch.shregs.msr))
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msr |= MSR_TS_S;
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else
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msr |= vcpu->arch.shregs.msr & MSR_TS_MASK;
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kvmppc_set_msr(vcpu, msr);
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}
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/*
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@ -28,6 +28,9 @@
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#include <asm/exception-64s.h>
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#include <asm/kvm_book3s_asm.h>
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#include <asm/mmu-hash64.h>
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#include <asm/tm.h>
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#define VCPU_GPRS_TM(reg) (((reg) * ULONG_SIZE) + VCPU_GPR_TM)
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#ifdef __LITTLE_ENDIAN__
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#error Need to fix lppaca and SLB shadow accesses in little endian mode
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@ -597,6 +600,116 @@ BEGIN_FTR_SECTION
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END_FTR_SECTION_NESTED(CPU_FTR_ARCH_206, CPU_FTR_ARCH_206, 89)
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END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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BEGIN_FTR_SECTION
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b skip_tm
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END_FTR_SECTION_IFCLR(CPU_FTR_TM)
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/* Turn on TM/FP/VSX/VMX so we can restore them. */
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mfmsr r5
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li r6, MSR_TM >> 32
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sldi r6, r6, 32
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or r5, r5, r6
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ori r5, r5, MSR_FP
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oris r5, r5, (MSR_VEC | MSR_VSX)@h
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mtmsrd r5
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/*
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* The user may change these outside of a transaction, so they must
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* always be context switched.
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*/
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ld r5, VCPU_TFHAR(r4)
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ld r6, VCPU_TFIAR(r4)
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ld r7, VCPU_TEXASR(r4)
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mtspr SPRN_TFHAR, r5
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mtspr SPRN_TFIAR, r6
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mtspr SPRN_TEXASR, r7
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ld r5, VCPU_MSR(r4)
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rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
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beq skip_tm /* TM not active in guest */
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/* Make sure the failure summary is set, otherwise we'll program check
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* when we trechkpt. It's possible that this might have been not set
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* on a kvmppc_set_one_reg() call but we shouldn't let this crash the
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* host.
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*/
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oris r7, r7, (TEXASR_FS)@h
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mtspr SPRN_TEXASR, r7
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/*
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* We need to load up the checkpointed state for the guest.
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* We need to do this early as it will blow away any GPRs, VSRs and
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* some SPRs.
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*/
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mr r31, r4
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addi r3, r31, VCPU_FPRS_TM
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bl .load_fp_state
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addi r3, r31, VCPU_VRS_TM
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bl .load_vr_state
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mr r4, r31
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lwz r7, VCPU_VRSAVE_TM(r4)
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mtspr SPRN_VRSAVE, r7
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ld r5, VCPU_LR_TM(r4)
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lwz r6, VCPU_CR_TM(r4)
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ld r7, VCPU_CTR_TM(r4)
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ld r8, VCPU_AMR_TM(r4)
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ld r9, VCPU_TAR_TM(r4)
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mtlr r5
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mtcr r6
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mtctr r7
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mtspr SPRN_AMR, r8
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mtspr SPRN_TAR, r9
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/*
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* Load up PPR and DSCR values but don't put them in the actual SPRs
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* till the last moment to avoid running with userspace PPR and DSCR for
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* too long.
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*/
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ld r29, VCPU_DSCR_TM(r4)
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ld r30, VCPU_PPR_TM(r4)
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std r2, PACATMSCRATCH(r13) /* Save TOC */
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/* Clear the MSR RI since r1, r13 are all going to be foobar. */
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li r5, 0
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mtmsrd r5, 1
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/* Load GPRs r0-r28 */
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reg = 0
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.rept 29
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ld reg, VCPU_GPRS_TM(reg)(r31)
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reg = reg + 1
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.endr
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mtspr SPRN_DSCR, r29
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mtspr SPRN_PPR, r30
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/* Load final GPRs */
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ld 29, VCPU_GPRS_TM(29)(r31)
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ld 30, VCPU_GPRS_TM(30)(r31)
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ld 31, VCPU_GPRS_TM(31)(r31)
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/* TM checkpointed state is now setup. All GPRs are now volatile. */
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TRECHKPT
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/* Now let's get back the state we need. */
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HMT_MEDIUM
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GET_PACA(r13)
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ld r29, HSTATE_DSCR(r13)
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mtspr SPRN_DSCR, r29
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ld r4, HSTATE_KVM_VCPU(r13)
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ld r1, HSTATE_HOST_R1(r13)
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ld r2, PACATMSCRATCH(r13)
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/* Set the MSR RI since we have our registers back. */
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li r5, MSR_RI
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mtmsrd r5, 1
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skip_tm:
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#endif
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/* Load guest PMU registers */
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/* R4 is live here (vcpu pointer) */
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li r3, 1
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@ -704,14 +817,6 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
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ld r6, VCPU_VTB(r4)
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mtspr SPRN_IC, r5
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mtspr SPRN_VTB, r6
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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ld r5, VCPU_TFHAR(r4)
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ld r6, VCPU_TFIAR(r4)
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ld r7, VCPU_TEXASR(r4)
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mtspr SPRN_TFHAR, r5
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mtspr SPRN_TFIAR, r6
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mtspr SPRN_TEXASR, r7
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#endif
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ld r8, VCPU_EBBHR(r4)
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mtspr SPRN_EBBHR, r8
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ld r5, VCPU_EBBRR(r4)
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@ -817,7 +922,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
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12: mtspr SPRN_SRR0, r10
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mr r10,r0
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mtspr SPRN_SRR1, r11
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ld r11, VCPU_INTR_MSR(r4)
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mr r9, r4
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bl kvmppc_msr_interrupt
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5:
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/*
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@ -1103,12 +1209,6 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201)
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BEGIN_FTR_SECTION
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b 8f
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END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
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/* Turn on TM so we can access TFHAR/TFIAR/TEXASR */
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mfmsr r8
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li r0, 1
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rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
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mtmsrd r8
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/* Save POWER8-specific registers */
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mfspr r5, SPRN_IAMR
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mfspr r6, SPRN_PSPB
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@ -1122,14 +1222,6 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
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std r5, VCPU_IC(r9)
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std r6, VCPU_VTB(r9)
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std r7, VCPU_TAR(r9)
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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mfspr r5, SPRN_TFHAR
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mfspr r6, SPRN_TFIAR
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mfspr r7, SPRN_TEXASR
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std r5, VCPU_TFHAR(r9)
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std r6, VCPU_TFIAR(r9)
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std r7, VCPU_TEXASR(r9)
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#endif
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mfspr r8, SPRN_EBBHR
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std r8, VCPU_EBBHR(r9)
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mfspr r5, SPRN_EBBRR
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@ -1557,7 +1649,7 @@ kvmppc_hdsi:
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mtspr SPRN_SRR0, r10
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mtspr SPRN_SRR1, r11
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li r10, BOOK3S_INTERRUPT_DATA_STORAGE
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ld r11, VCPU_INTR_MSR(r9)
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bl kvmppc_msr_interrupt
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fast_interrupt_c_return:
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6: ld r7, VCPU_CTR(r9)
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lwz r8, VCPU_XER(r9)
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@ -1626,7 +1718,7 @@ kvmppc_hisi:
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1: mtspr SPRN_SRR0, r10
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mtspr SPRN_SRR1, r11
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li r10, BOOK3S_INTERRUPT_INST_STORAGE
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ld r11, VCPU_INTR_MSR(r9)
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bl kvmppc_msr_interrupt
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b fast_interrupt_c_return
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3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
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@ -1669,7 +1761,7 @@ sc_1_fast_return:
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mtspr SPRN_SRR0,r10
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mtspr SPRN_SRR1,r11
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li r10, BOOK3S_INTERRUPT_SYSCALL
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ld r11, VCPU_INTR_MSR(r9)
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bl kvmppc_msr_interrupt
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mr r4,r9
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b fast_guest_return
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@ -1997,7 +2089,7 @@ machine_check_realmode:
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beq mc_cont
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/* If not, deliver a machine check. SRR0/1 are already set */
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li r10, BOOK3S_INTERRUPT_MACHINE_CHECK
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ld r11, VCPU_INTR_MSR(r9)
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bl kvmppc_msr_interrupt
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b fast_interrupt_c_return
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/*
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@ -2138,8 +2230,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
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mfspr r6,SPRN_VRSAVE
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stw r6,VCPU_VRSAVE(r31)
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mtlr r30
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mtmsrd r5
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isync
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blr
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/*
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@ -2186,3 +2276,20 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
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*/
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kvmppc_bad_host_intr:
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b .
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/*
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* This mimics the MSR transition on IRQ delivery. The new guest MSR is taken
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* from VCPU_INTR_MSR and is modified based on the required TM state changes.
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* r11 has the guest MSR value (in/out)
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* r9 has a vcpu pointer (in)
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* r0 is used as a scratch register
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*/
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kvmppc_msr_interrupt:
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rldicl r0, r11, 64 - MSR_TS_S_LG, 62
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cmpwi r0, 2 /* Check if we are in transactional state.. */
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ld r11, VCPU_INTR_MSR(r9)
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bne 1f
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/* ... if transactional, change to suspended */
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li r0, 1
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1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG
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blr
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