iommu/amd: Specify PCI segment ID when getting pci device
Upcoming AMD systems can have multiple PCI segments. Hence pass PCI segment ID to pci_get_domain_bus_and_slot() instead of '0'. Co-developed-by: Vasant Hegde <vasant.hegde@amd.com> Signed-off-by: Vasant Hegde <vasant.hegde@amd.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Link: https://lore.kernel.org/r/20220706113825.25582-32-vasant.hegde@amd.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
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a45627baa7
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e5670e1822
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@ -1962,7 +1962,8 @@ static int __init iommu_init_pci(struct amd_iommu *iommu)
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int cap_ptr = iommu->cap_ptr;
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int ret;
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iommu->dev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(iommu->devid),
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iommu->dev = pci_get_domain_bus_and_slot(iommu->pci_seg->id,
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PCI_BUS_NUM(iommu->devid),
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iommu->devid & 0xff);
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if (!iommu->dev)
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return -ENODEV;
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@ -2025,7 +2026,8 @@ static int __init iommu_init_pci(struct amd_iommu *iommu)
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int i, j;
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iommu->root_pdev =
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pci_get_domain_bus_and_slot(0, iommu->dev->bus->number,
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pci_get_domain_bus_and_slot(iommu->pci_seg->id,
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iommu->dev->bus->number,
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PCI_DEVFN(0, 0));
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/*
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@ -473,7 +473,7 @@ static void dump_command(unsigned long phys_addr)
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pr_err("CMD[%d]: %08x\n", i, cmd->data[i]);
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}
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static void amd_iommu_report_rmp_hw_error(volatile u32 *event)
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static void amd_iommu_report_rmp_hw_error(struct amd_iommu *iommu, volatile u32 *event)
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{
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struct iommu_dev_data *dev_data = NULL;
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int devid, vmg_tag, flags;
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@ -485,7 +485,7 @@ static void amd_iommu_report_rmp_hw_error(volatile u32 *event)
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flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
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spa = ((u64)event[3] << 32) | (event[2] & 0xFFFFFFF8);
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pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
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pdev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, PCI_BUS_NUM(devid),
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devid & 0xff);
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if (pdev)
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dev_data = dev_iommu_priv_get(&pdev->dev);
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@ -505,7 +505,7 @@ static void amd_iommu_report_rmp_hw_error(volatile u32 *event)
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pci_dev_put(pdev);
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}
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static void amd_iommu_report_rmp_fault(volatile u32 *event)
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static void amd_iommu_report_rmp_fault(struct amd_iommu *iommu, volatile u32 *event)
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{
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struct iommu_dev_data *dev_data = NULL;
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int devid, flags_rmp, vmg_tag, flags;
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@ -518,7 +518,7 @@ static void amd_iommu_report_rmp_fault(volatile u32 *event)
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flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
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gpa = ((u64)event[3] << 32) | event[2];
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pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
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pdev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, PCI_BUS_NUM(devid),
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devid & 0xff);
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if (pdev)
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dev_data = dev_iommu_priv_get(&pdev->dev);
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@ -544,13 +544,14 @@ static void amd_iommu_report_rmp_fault(volatile u32 *event)
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#define IS_WRITE_REQUEST(flags) \
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((flags) & EVENT_FLAG_RW)
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static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
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static void amd_iommu_report_page_fault(struct amd_iommu *iommu,
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u16 devid, u16 domain_id,
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u64 address, int flags)
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{
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struct iommu_dev_data *dev_data = NULL;
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struct pci_dev *pdev;
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pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
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pdev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, PCI_BUS_NUM(devid),
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devid & 0xff);
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if (pdev)
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dev_data = dev_iommu_priv_get(&pdev->dev);
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@ -613,7 +614,7 @@ retry:
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}
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if (type == EVENT_TYPE_IO_FAULT) {
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amd_iommu_report_page_fault(devid, pasid, address, flags);
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amd_iommu_report_page_fault(iommu, devid, pasid, address, flags);
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return;
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}
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@ -654,10 +655,10 @@ retry:
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pasid, address, flags);
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break;
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case EVENT_TYPE_RMP_FAULT:
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amd_iommu_report_rmp_fault(event);
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amd_iommu_report_rmp_fault(iommu, event);
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break;
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case EVENT_TYPE_RMP_HW_ERR:
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amd_iommu_report_rmp_hw_error(event);
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amd_iommu_report_rmp_hw_error(iommu, event);
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break;
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case EVENT_TYPE_INV_PPR_REQ:
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pasid = PPR_PASID(*((u64 *)__evt));
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