mfd: Add device-tree binding doc for PMIC MAX77620/MAX20024
The MAXIM PMIC MAX77620 and MAX20024 are power management IC which supports RTC, GPIO, DCDC/LDO regulators, interrupt, watchdog etc. Add DT binding document for the different functionality of this device. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
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Laxman Dewangan
Lee Jones
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MAX77620 Power management IC from Maxim Semiconductor.
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Required properties:
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-------------------
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- compatible: Must be one of
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"maxim,max77620"
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"maxim,max20024".
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- reg: I2C device address.
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Optional properties:
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-------------------
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- interrupts: The interrupt on the parent the controller is
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connected to.
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- interrupt-controller: Marks the device node as an interrupt controller.
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- #interrupt-cells: is <2> and their usage is compliant to the 2 cells
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variant of <../interrupt-controller/interrupts.txt>
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IRQ numbers for different interrupt source of MAX77620
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are defined at dt-bindings/mfd/max77620.h.
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Optional subnodes and their properties:
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=======================================
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Flexible power sequence configurations:
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--------------------------------------
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The Flexible Power Sequencer (FPS) allows each regulator to power up under
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hardware or software control. Additionally, each regulator can power on
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independently or among a group of other regulators with an adjustable power-up
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and power-down delays (sequencing). GPIO1, GPIO2, and GPIO3 can be programmed
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to be part of a sequence allowing external regulators to be sequenced along
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with internal regulators. 32KHz clock can be programmed to be part of a
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sequence.
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The flexible sequencing structure consists of two hardware enable inputs
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(EN0, EN1), and 3 master sequencing timers called FPS0, FPS1 and FPS2.
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Each master sequencing timer is programmable through its configuration
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register to have a hardware enable source (EN1 or EN2) or a software enable
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source (SW). When enabled/disabled, the master sequencing timer generates
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eight sequencing events on different time periods called slots. The time
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period between each event is programmable within the configuration register.
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Each regulator, GPIO1, GPIO2, GPIO3, and 32KHz clock has a flexible power
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sequence slave register which allows its enable source to be specified as
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a flexible power sequencer timer or a software bit. When a FPS source of
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regulators, GPIOs and clocks specifies the enable source to be a flexible
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power sequencer, the power up and power down delays can be specified in
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the regulators, GPIOs and clocks flexible power sequencer configuration
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registers.
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When FPS event cleared (set to LOW), regulators, GPIOs and 32KHz
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clock are set into following state at the sequencing event that
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corresponds to its flexible sequencer configuration register.
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Sleep state: In this state, regulators, GPIOs
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and 32KHz clock get disabled at
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the sequencing event.
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Global Low Power Mode (GLPM): In this state, regulators are set in
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low power mode at the sequencing event.
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The configuration parameters of FPS is provided through sub-node "fps"
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and their child for FPS specific. The child node name for FPS are "fps0",
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"fps1", and "fps2" for FPS0, FPS1 and FPS2 respectively.
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The FPS configurations like FPS source, power up and power down slots for
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regulators, GPIOs and 32kHz clocks are provided in their respective
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configuration nodes which is explained in respective sub-system DT
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binding document.
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There is need for different FPS configuration parameters based on system
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state like when system state changed from active to suspend or active to
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power off (shutdown).
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Optional properties:
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-------------------
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-maxim,fps-event-source: u32, FPS event source like external
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hardware input to PMIC i.e. EN0, EN1 or
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software (SW).
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The macros are defined on
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dt-bindings/mfd/max77620.h
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for different control source.
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- MAX77620_FPS_EVENT_SRC_EN0
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for hardware input pin EN0.
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- MAX77620_FPS_EVENT_SRC_EN1
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for hardware input pin EN1.
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- MAX77620_FPS_EVENT_SRC_SW
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for software control.
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-maxim,shutdown-fps-time-period-us: u32, FPS time period in microseconds
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when system enters in to shutdown
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state.
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-maxim,suspend-fps-time-period-us: u32, FPS time period in microseconds
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when system enters in to suspend state.
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-maxim,device-state-on-disabled-event: u32, describe the PMIC state when FPS
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event cleared (set to LOW) whether it
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should go to sleep state or low-power
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state. Following are valid values:
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- MAX77620_FPS_INACTIVE_STATE_SLEEP
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to set the PMIC state to sleep.
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- MAX77620_FPS_INACTIVE_STATE_LOW_POWER
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to set the PMIC state to low
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power.
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Absence of this property or other value
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will not change device state when FPS
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event get cleared.
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Here supported time periods by device in microseconds are as follows:
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MAX77620 supports 40, 80, 160, 320, 640, 1280, 2560 and 5120 microseconds.
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MAX20024 supports 20, 40, 80, 160, 320, 640, 1280 and 2540 microseconds.
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For DT binding details of different sub modules like GPIO, pincontrol,
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regulator, power, please refer respective device-tree binding document
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under their respective sub-system directories.
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Example:
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--------
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#include <dt-bindings/mfd/max77620.h>
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max77620@3c {
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compatible = "maxim,max77620";
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reg = <0x3c>;
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interrupt-parent = <&intc>;
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interrupts = <0 86 IRQ_TYPE_NONE>;
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interrupt-controller;
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#interrupt-cells = <2>;
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fps {
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fps0 {
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maxim,shutdown-fps-time-period-us = <1280>;
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maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
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};
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fps1 {
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maxim,shutdown-fps-time-period-us = <1280>;
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maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
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};
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fps2 {
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maxim,shutdown-fps-time-period-us = <1280>;
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maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_SW>;
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};
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};
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};
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/*
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* This header provides macros for MAXIM MAX77620 device bindings.
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*
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* Copyright (c) 2016, NVIDIA Corporation.
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* Author: Laxman Dewangan <ldewangan@nvidia.com>
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*/
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#ifndef _DT_BINDINGS_MFD_MAX77620_H
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#define _DT_BINDINGS_MFD_MAX77620_H
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/* MAX77620 interrupts */
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#define MAX77620_IRQ_TOP_GLBL 0 /* Low-Battery */
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#define MAX77620_IRQ_TOP_SD 1 /* SD power fail */
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#define MAX77620_IRQ_TOP_LDO 2 /* LDO power fail */
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#define MAX77620_IRQ_TOP_GPIO 3 /* GPIO internal int to MAX77620 */
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#define MAX77620_IRQ_TOP_RTC 4 /* RTC */
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#define MAX77620_IRQ_TOP_32K 5 /* 32kHz oscillator */
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#define MAX77620_IRQ_TOP_ONOFF 6 /* ON/OFF oscillator */
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#define MAX77620_IRQ_LBT_MBATLOW 7 /* Thermal alarm status, > 120C */
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#define MAX77620_IRQ_LBT_TJALRM1 8 /* Thermal alarm status, > 120C */
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#define MAX77620_IRQ_LBT_TJALRM2 9 /* Thermal alarm status, > 140C */
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/* FPS event source */
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#define MAX77620_FPS_EVENT_SRC_EN0 0
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#define MAX77620_FPS_EVENT_SRC_EN1 1
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#define MAX77620_FPS_EVENT_SRC_SW 2
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/* Device state when FPS event LOW */
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#define MAX77620_FPS_INACTIVE_STATE_SLEEP 0
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#define MAX77620_FPS_INACTIVE_STATE_LOW_POWER 1
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/* FPS source */
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#define MAX77620_FPS_SRC_0 0
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#define MAX77620_FPS_SRC_1 1
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#define MAX77620_FPS_SRC_2 2
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#define MAX77620_FPS_SRC_NONE 3
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#define MAX77620_FPS_SRC_DEF 4
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#endif
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