Merge branch 'for-next/trbe-errata' into for-next/core
* for-next/trbe-errata: arm64: errata: Add detection for TRBE write to out-of-range arm64: errata: Add workaround for TSB flush failures arm64: errata: Add detection for TRBE overwrite in FILL mode arm64: Add Neoverse-N2, Cortex-A710 CPU part definition
This commit is contained in:
Will Deacon
Коммит
e5f5210212
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@ -92,12 +92,24 @@ stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A710 | #2054223 | ARM64_ERRATUM_2054223 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A710 | #2224489 | ARM64_ERRATUM_2224489 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N1 | #1349291 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N2 | #2139208 | ARM64_ERRATUM_2139208 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N2 | #2067961 | ARM64_ERRATUM_2067961 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N2 | #2253138 | ARM64_ERRATUM_2253138 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | MMU-500 | #841119,826419 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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@ -666,6 +666,121 @@ config ARM64_ERRATUM_1508412
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If unsure, say Y.
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config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
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bool
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config ARM64_ERRATUM_2119858
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bool "Cortex-A710: 2119858: workaround TRBE overwriting trace data in FILL mode"
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default y
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depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
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depends on CORESIGHT_TRBE
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select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
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help
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This option adds the workaround for ARM Cortex-A710 erratum 2119858.
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Affected Cortex-A710 cores could overwrite up to 3 cache lines of trace
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data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
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the event of a WRAP event.
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Work around the issue by always making sure we move the TRBPTR_EL1 by
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256 bytes before enabling the buffer and filling the first 256 bytes of
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the buffer with ETM ignore packets upon disabling.
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If unsure, say Y.
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config ARM64_ERRATUM_2139208
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bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
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default y
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depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
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depends on CORESIGHT_TRBE
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select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
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help
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This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
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Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
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data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
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the event of a WRAP event.
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Work around the issue by always making sure we move the TRBPTR_EL1 by
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256 bytes before enabling the buffer and filling the first 256 bytes of
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the buffer with ETM ignore packets upon disabling.
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If unsure, say Y.
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config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
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bool
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config ARM64_ERRATUM_2054223
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bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
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default y
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select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
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help
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Enable workaround for ARM Cortex-A710 erratum 2054223
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Affected cores may fail to flush the trace data on a TSB instruction, when
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the PE is in trace prohibited state. This will cause losing a few bytes
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of the trace cached.
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Workaround is to issue two TSB consecutively on affected cores.
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If unsure, say Y.
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config ARM64_ERRATUM_2067961
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bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
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default y
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select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
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help
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Enable workaround for ARM Neoverse-N2 erratum 2067961
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Affected cores may fail to flush the trace data on a TSB instruction, when
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the PE is in trace prohibited state. This will cause losing a few bytes
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of the trace cached.
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Workaround is to issue two TSB consecutively on affected cores.
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If unsure, say Y.
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config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
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bool
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config ARM64_ERRATUM_2253138
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bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
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depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
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depends on CORESIGHT_TRBE
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default y
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select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
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help
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This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
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Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
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for TRBE. Under some conditions, the TRBE might generate a write to the next
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virtually addressed page following the last page of the TRBE address space
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(i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
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Work around this in the driver by always making sure that there is a
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page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
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If unsure, say Y.
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config ARM64_ERRATUM_2224489
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bool "Cortex-A710: 2224489: workaround TRBE writing to address out-of-range"
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depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
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depends on CORESIGHT_TRBE
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default y
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select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
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help
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This option adds the workaround for ARM Cortex-A710 erratum 2224489.
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Affected Cortex-A710 cores might write to an out-of-range address, not reserved
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for TRBE. Under some conditions, the TRBE might generate a write to the next
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virtually addressed page following the last page of the TRBE address space
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(i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
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Work around this in the driver by always making sure that there is a
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page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
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If unsure, say Y.
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config CAVIUM_ERRATUM_22375
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bool "Cavium erratum 22375, 24313"
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default y
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@ -23,7 +23,7 @@
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#define dsb(opt) asm volatile("dsb " #opt : : : "memory")
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#define psb_csync() asm volatile("hint #17" : : : "memory")
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#define tsb_csync() asm volatile("hint #18" : : : "memory")
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#define __tsb_csync() asm volatile("hint #18" : : : "memory")
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#define csdb() asm volatile("hint #20" : : : "memory")
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#ifdef CONFIG_ARM64_PSEUDO_NMI
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@ -46,6 +46,20 @@
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#define dma_rmb() dmb(oshld)
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#define dma_wmb() dmb(oshst)
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#define tsb_csync() \
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do { \
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/* \
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* CPUs affected by Arm Erratum 2054223 or 2067961 needs \
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* another TSB to ensure the trace is flushed. The barriers \
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* don't have to be strictly back to back, as long as the \
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* CPU is in trace prohibited state. \
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*/ \
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if (cpus_have_final_cap(ARM64_WORKAROUND_TSB_FLUSH_FAILURE)) \
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__tsb_csync(); \
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__tsb_csync(); \
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} while (0)
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/*
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* Generate a mask for array_index__nospec() that is ~0UL when 0 <= idx < sz
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* and 0 otherwise.
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@ -73,6 +73,8 @@
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#define ARM_CPU_PART_CORTEX_A76 0xD0B
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#define ARM_CPU_PART_NEOVERSE_N1 0xD0C
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#define ARM_CPU_PART_CORTEX_A77 0xD0D
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#define ARM_CPU_PART_CORTEX_A710 0xD47
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#define ARM_CPU_PART_NEOVERSE_N2 0xD49
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#define APM_CPU_PART_POTENZA 0x000
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@ -113,6 +115,8 @@
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#define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
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#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
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#define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)
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#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)
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#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
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#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
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#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
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#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
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@ -340,6 +340,42 @@ static const struct midr_range erratum_1463225[] = {
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};
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#endif
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#ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
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static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
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#ifdef CONFIG_ARM64_ERRATUM_2139208
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_2119858
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
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#endif
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{},
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};
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#endif /* CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE */
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#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE
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static const struct midr_range tsb_flush_fail_cpus[] = {
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#ifdef CONFIG_ARM64_ERRATUM_2067961
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_2054223
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
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#endif
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{},
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};
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#endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */
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#ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
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static struct midr_range trbe_write_out_of_range_cpus[] = {
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#ifdef CONFIG_ARM64_ERRATUM_2253138
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_2224489
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
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#endif
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{},
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};
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#endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */
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const struct arm64_cpu_capabilities arm64_errata[] = {
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#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
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{
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@ -533,6 +569,34 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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.capability = ARM64_WORKAROUND_NVIDIA_CARMEL_CNP,
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ERRATA_MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
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},
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#endif
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#ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
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{
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/*
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* The erratum work around is handled within the TRBE
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* driver and can be applied per-cpu. So, we can allow
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* a late CPU to come online with this erratum.
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*/
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.desc = "ARM erratum 2119858 or 2139208",
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.capability = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE,
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.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
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CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus),
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},
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#endif
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#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE
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{
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.desc = "ARM erratum 2067961 or 2054223",
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.capability = ARM64_WORKAROUND_TSB_FLUSH_FAILURE,
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ERRATA_MIDR_RANGE_LIST(tsb_flush_fail_cpus),
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},
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#endif
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#ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
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{
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.desc = "ARM erratum 2253138 or 2224489",
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.capability = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE,
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.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
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CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus),
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},
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#endif
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{
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}
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@ -55,6 +55,9 @@ WORKAROUND_1418040
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WORKAROUND_1463225
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WORKAROUND_1508412
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WORKAROUND_1542419
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WORKAROUND_TRBE_OVERWRITE_FILL_MODE
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WORKAROUND_TSB_FLUSH_FAILURE
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WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
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WORKAROUND_CAVIUM_23154
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WORKAROUND_CAVIUM_27456
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WORKAROUND_CAVIUM_30115
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