soc: qcom: gsbi: Add support for ADM CRCI muxing
This patch adds automatic configuration for the ADM CRCI muxing required to support DMA operations for GSBI clients. The GSBI mode and instance determine the correct TCSR ADM CRCI MUX value that must be programmed so that the DMA works properly. Signed-off-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
This commit is contained in:
Andy Gross
Kumar Gala
Родитель
767b0235dd
Коммит
e5fdad68d4
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@ -6,7 +6,8 @@ configuration settings. The mode setting will govern the input/output mode of
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the 4 GSBI IOs.
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Required properties:
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- compatible: must contain "qcom,gsbi-v1.0.0" for APQ8064/IPQ8064
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- compatible: Should contain "qcom,gsbi-v1.0.0"
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- cell-index: Should contain the GSBI index
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- reg: Address range for GSBI registers
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- clocks: required clock
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- clock-names: must contain "iface" entry
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@ -16,6 +17,8 @@ Required properties:
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Optional properties:
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- qcom,crci : indicates CRCI MUX value for QUP CRCI ports. Please reference
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dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
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- syscon-tcsr: indicates phandle of TCSR syscon node. Required if child uses
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dma.
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Required properties if child node exists:
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- #address-cells: Must be 1
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@ -39,6 +42,7 @@ Example for APQ8064:
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gsbi4@16300000 {
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compatible = "qcom,gsbi-v1.0.0";
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cell-index = <4>;
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reg = <0x16300000 0x100>;
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clocks = <&gcc GSBI4_H_CLK>;
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clock-names = "iface";
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@ -48,22 +52,24 @@ Example for APQ8064:
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qcom,mode = <GSBI_PROT_I2C_UART>;
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qcom,crci = <GSBI_CRCI_QUP>;
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syscon-tcsr = <&tcsr>;
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/* child nodes go under here */
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i2c_qup4: i2c@16380000 {
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compatible = "qcom,i2c-qup-v1.1.1";
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reg = <0x16380000 0x1000>;
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interrupts = <0 153 0>;
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compatible = "qcom,i2c-qup-v1.1.1";
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reg = <0x16380000 0x1000>;
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interrupts = <0 153 0>;
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clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
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clock-names = "core", "iface";
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clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
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clock-names = "core", "iface";
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clock-frequency = <200000>;
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clock-frequency = <200000>;
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#address-cells = <1>;
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#size-cells = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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uart4: serial@16340000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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@ -76,3 +82,7 @@ Example for APQ8064:
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};
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};
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tcsr: syscon@1a400000 {
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compatible = "qcom,apq8064-tcsr", "syscon";
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reg = <0x1a400000 0x100>;
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};
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@ -4,6 +4,7 @@
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config QCOM_GSBI
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tristate "QCOM General Serial Bus Interface"
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depends on ARCH_QCOM
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select MFD_SYSCON
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help
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Say y here to enable GSBI support. The GSBI provides control
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functions for connecting the underlying serial UART, SPI, and I2C
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@ -18,22 +18,129 @@
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#include <dt-bindings/soc/qcom,gsbi.h>
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#define GSBI_CTRL_REG 0x0000
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#define GSBI_PROTOCOL_SHIFT 4
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#define MAX_GSBI 12
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#define TCSR_ADM_CRCI_BASE 0x70
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struct crci_config {
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u32 num_rows;
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const u32 (*array)[MAX_GSBI];
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};
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static const u32 crci_ipq8064[][MAX_GSBI] = {
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{
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0x000003, 0x00000c, 0x000030, 0x0000c0,
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0x000300, 0x000c00, 0x003000, 0x00c000,
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0x030000, 0x0c0000, 0x300000, 0xc00000
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},
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{
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0x000003, 0x00000c, 0x000030, 0x0000c0,
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0x000300, 0x000c00, 0x003000, 0x00c000,
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0x030000, 0x0c0000, 0x300000, 0xc00000
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},
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};
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static const struct crci_config config_ipq8064 = {
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.num_rows = ARRAY_SIZE(crci_ipq8064),
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.array = crci_ipq8064,
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};
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static const unsigned int crci_apq8064[][MAX_GSBI] = {
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{
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0x001800, 0x006000, 0x000030, 0x0000c0,
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0x000300, 0x000400, 0x000000, 0x000000,
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0x000000, 0x000000, 0x000000, 0x000000
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},
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{
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0x000000, 0x000000, 0x000000, 0x000000,
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0x000000, 0x000020, 0x0000c0, 0x000000,
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0x000000, 0x000000, 0x000000, 0x000000
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},
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};
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static const struct crci_config config_apq8064 = {
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.num_rows = ARRAY_SIZE(crci_apq8064),
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.array = crci_apq8064,
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};
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static const unsigned int crci_msm8960[][MAX_GSBI] = {
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{
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0x000003, 0x00000c, 0x000030, 0x0000c0,
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0x000300, 0x000400, 0x000000, 0x000000,
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0x000000, 0x000000, 0x000000, 0x000000
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},
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{
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0x000000, 0x000000, 0x000000, 0x000000,
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0x000000, 0x000020, 0x0000c0, 0x000300,
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0x001800, 0x006000, 0x000000, 0x000000
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},
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};
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static const struct crci_config config_msm8960 = {
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.num_rows = ARRAY_SIZE(crci_msm8960),
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.array = crci_msm8960,
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};
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static const unsigned int crci_msm8660[][MAX_GSBI] = {
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{ /* ADM 0 - B */
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0x000003, 0x00000c, 0x000030, 0x0000c0,
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0x000300, 0x000c00, 0x003000, 0x00c000,
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0x030000, 0x0c0000, 0x300000, 0xc00000
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},
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{ /* ADM 0 - B */
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0x000003, 0x00000c, 0x000030, 0x0000c0,
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0x000300, 0x000c00, 0x003000, 0x00c000,
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0x030000, 0x0c0000, 0x300000, 0xc00000
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},
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{ /* ADM 1 - A */
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0x000003, 0x00000c, 0x000030, 0x0000c0,
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0x000300, 0x000c00, 0x003000, 0x00c000,
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0x030000, 0x0c0000, 0x300000, 0xc00000
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},
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{ /* ADM 1 - B */
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0x000003, 0x00000c, 0x000030, 0x0000c0,
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0x000300, 0x000c00, 0x003000, 0x00c000,
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0x030000, 0x0c0000, 0x300000, 0xc00000
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},
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};
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static const struct crci_config config_msm8660 = {
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.num_rows = ARRAY_SIZE(crci_msm8660),
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.array = crci_msm8660,
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};
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struct gsbi_info {
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struct clk *hclk;
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u32 mode;
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u32 crci;
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struct regmap *tcsr;
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};
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static const struct of_device_id tcsr_dt_match[] = {
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{ .compatible = "qcom,tcsr-ipq8064", .data = &config_ipq8064},
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{ .compatible = "qcom,tcsr-apq8064", .data = &config_apq8064},
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{ .compatible = "qcom,tcsr-msm8960", .data = &config_msm8960},
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{ .compatible = "qcom,tcsr-msm8660", .data = &config_msm8660},
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{ },
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};
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static int gsbi_probe(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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struct device_node *tcsr_node;
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const struct of_device_id *match;
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struct resource *res;
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void __iomem *base;
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struct gsbi_info *gsbi;
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int i;
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u32 mask, gsbi_num;
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const struct crci_config *config = NULL;
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gsbi = devm_kzalloc(&pdev->dev, sizeof(*gsbi), GFP_KERNEL);
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@ -45,6 +152,32 @@ static int gsbi_probe(struct platform_device *pdev)
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if (IS_ERR(base))
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return PTR_ERR(base);
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/* get the tcsr node and setup the config and regmap */
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gsbi->tcsr = syscon_regmap_lookup_by_phandle(node, "syscon-tcsr");
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if (!IS_ERR(gsbi->tcsr)) {
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tcsr_node = of_parse_phandle(node, "syscon-tcsr", 0);
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if (tcsr_node) {
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match = of_match_node(tcsr_dt_match, tcsr_node);
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if (match)
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config = match->data;
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else
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dev_warn(&pdev->dev, "no matching TCSR\n");
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of_node_put(tcsr_node);
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}
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}
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if (of_property_read_u32(node, "cell-index", &gsbi_num)) {
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dev_err(&pdev->dev, "missing cell-index\n");
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return -EINVAL;
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}
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if (gsbi_num < 1 || gsbi_num > MAX_GSBI) {
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dev_err(&pdev->dev, "invalid cell-index\n");
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return -EINVAL;
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}
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if (of_property_read_u32(node, "qcom,mode", &gsbi->mode)) {
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dev_err(&pdev->dev, "missing mode configuration\n");
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return -EINVAL;
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@ -64,6 +197,25 @@ static int gsbi_probe(struct platform_device *pdev)
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writel_relaxed((gsbi->mode << GSBI_PROTOCOL_SHIFT) | gsbi->crci,
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base + GSBI_CTRL_REG);
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/*
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* modify tcsr to reflect mode and ADM CRCI mux
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* Each gsbi contains a pair of bits, one for RX and one for TX
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* SPI mode requires both bits cleared, otherwise they are set
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*/
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if (config) {
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for (i = 0; i < config->num_rows; i++) {
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mask = config->array[i][gsbi_num - 1];
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if (gsbi->mode == GSBI_PROT_SPI)
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regmap_update_bits(gsbi->tcsr,
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TCSR_ADM_CRCI_BASE + 4 * i, mask, 0);
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else
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regmap_update_bits(gsbi->tcsr,
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TCSR_ADM_CRCI_BASE + 4 * i, mask, mask);
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}
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}
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/* make sure the gsbi control write is not reordered */
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wmb();
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