Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm radeon fixes from Dave Airlie: "One core fix, but mostly radeon fixes for s/r and big endian UVD support, and a fix to stop the GPU being reset for no good reason, and crashing people's machines." * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm/radeon: update lockup tracking when scheduling in empty ring drm/prime: Honor requested file flags when exporting a buffer drm/radeon: fix UVD on big endian drm/radeon: fix write back suspend regression with uvd v2 drm/radeon: do not try to uselessly update virtual memory pagetable
This commit is contained in:
Коммит
e61cd5e2e3
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@ -190,8 +190,7 @@ struct dma_buf *drm_gem_prime_export(struct drm_device *dev,
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if (ret)
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return ERR_PTR(ret);
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}
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return dma_buf_export(obj, &drm_gem_prime_dmabuf_ops, obj->size,
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0600);
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return dma_buf_export(obj, &drm_gem_prime_dmabuf_ops, obj->size, flags);
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}
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EXPORT_SYMBOL(drm_gem_prime_export);
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@ -2687,6 +2687,9 @@ void r600_uvd_rbc_stop(struct radeon_device *rdev)
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int r600_uvd_init(struct radeon_device *rdev)
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{
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int i, j, r;
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/* disable byte swapping */
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u32 lmi_swap_cntl = 0;
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u32 mp_swap_cntl = 0;
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/* raise clocks while booting up the VCPU */
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radeon_set_uvd_clocks(rdev, 53300, 40000);
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@ -2711,9 +2714,13 @@ int r600_uvd_init(struct radeon_device *rdev)
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WREG32(UVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
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(1 << 21) | (1 << 9) | (1 << 20));
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/* disable byte swapping */
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WREG32(UVD_LMI_SWAP_CNTL, 0);
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WREG32(UVD_MP_SWAP_CNTL, 0);
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#ifdef __BIG_ENDIAN
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/* swap (8 in 32) RB and IB */
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lmi_swap_cntl = 0xa;
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mp_swap_cntl = 0;
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#endif
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WREG32(UVD_LMI_SWAP_CNTL, lmi_swap_cntl);
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WREG32(UVD_MP_SWAP_CNTL, mp_swap_cntl);
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WREG32(UVD_MPC_SET_MUXA0, 0x40c2040);
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WREG32(UVD_MPC_SET_MUXA1, 0x0);
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@ -244,16 +244,6 @@ void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
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*/
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void radeon_wb_disable(struct radeon_device *rdev)
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{
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int r;
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if (rdev->wb.wb_obj) {
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r = radeon_bo_reserve(rdev->wb.wb_obj, false);
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if (unlikely(r != 0))
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return;
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radeon_bo_kunmap(rdev->wb.wb_obj);
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radeon_bo_unpin(rdev->wb.wb_obj);
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radeon_bo_unreserve(rdev->wb.wb_obj);
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}
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rdev->wb.enabled = false;
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}
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@ -269,6 +259,11 @@ void radeon_wb_fini(struct radeon_device *rdev)
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{
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radeon_wb_disable(rdev);
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if (rdev->wb.wb_obj) {
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if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) {
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radeon_bo_kunmap(rdev->wb.wb_obj);
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radeon_bo_unpin(rdev->wb.wb_obj);
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radeon_bo_unreserve(rdev->wb.wb_obj);
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}
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radeon_bo_unref(&rdev->wb.wb_obj);
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rdev->wb.wb = NULL;
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rdev->wb.wb_obj = NULL;
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@ -295,26 +290,26 @@ int radeon_wb_init(struct radeon_device *rdev)
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dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
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return r;
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}
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}
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r = radeon_bo_reserve(rdev->wb.wb_obj, false);
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if (unlikely(r != 0)) {
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radeon_wb_fini(rdev);
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return r;
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}
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r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
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&rdev->wb.gpu_addr);
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if (r) {
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r = radeon_bo_reserve(rdev->wb.wb_obj, false);
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if (unlikely(r != 0)) {
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radeon_wb_fini(rdev);
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return r;
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}
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r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
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&rdev->wb.gpu_addr);
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if (r) {
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radeon_bo_unreserve(rdev->wb.wb_obj);
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dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
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radeon_wb_fini(rdev);
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return r;
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}
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r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
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radeon_bo_unreserve(rdev->wb.wb_obj);
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dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
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radeon_wb_fini(rdev);
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return r;
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}
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r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
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radeon_bo_unreserve(rdev->wb.wb_obj);
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if (r) {
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dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
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radeon_wb_fini(rdev);
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return r;
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if (r) {
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dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
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radeon_wb_fini(rdev);
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return r;
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}
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}
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/* clear wb memory */
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@ -63,7 +63,9 @@ static void radeon_fence_write(struct radeon_device *rdev, u32 seq, int ring)
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{
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struct radeon_fence_driver *drv = &rdev->fence_drv[ring];
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if (likely(rdev->wb.enabled || !drv->scratch_reg)) {
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*drv->cpu_addr = cpu_to_le32(seq);
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if (drv->cpu_addr) {
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*drv->cpu_addr = cpu_to_le32(seq);
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}
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} else {
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WREG32(drv->scratch_reg, seq);
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}
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@ -84,7 +86,11 @@ static u32 radeon_fence_read(struct radeon_device *rdev, int ring)
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u32 seq = 0;
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if (likely(rdev->wb.enabled || !drv->scratch_reg)) {
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seq = le32_to_cpu(*drv->cpu_addr);
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if (drv->cpu_addr) {
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seq = le32_to_cpu(*drv->cpu_addr);
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} else {
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seq = lower_32_bits(atomic64_read(&drv->last_seq));
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}
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} else {
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seq = RREG32(drv->scratch_reg);
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}
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@ -1197,11 +1197,13 @@ int radeon_vm_bo_update_pte(struct radeon_device *rdev,
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int radeon_vm_bo_rmv(struct radeon_device *rdev,
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struct radeon_bo_va *bo_va)
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{
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int r;
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int r = 0;
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mutex_lock(&rdev->vm_manager.lock);
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mutex_lock(&bo_va->vm->mutex);
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r = radeon_vm_bo_update_pte(rdev, bo_va->vm, bo_va->bo, NULL);
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if (bo_va->soffset) {
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r = radeon_vm_bo_update_pte(rdev, bo_va->vm, bo_va->bo, NULL);
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}
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mutex_unlock(&rdev->vm_manager.lock);
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list_del(&bo_va->vm_list);
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mutex_unlock(&bo_va->vm->mutex);
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@ -402,6 +402,13 @@ int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsi
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return -ENOMEM;
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/* Align requested size with padding so unlock_commit can
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* pad safely */
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radeon_ring_free_size(rdev, ring);
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if (ring->ring_free_dw == (ring->ring_size / 4)) {
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/* This is an empty ring update lockup info to avoid
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* false positive.
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*/
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radeon_ring_lockup_update(ring);
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}
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ndw = (ndw + ring->align_mask) & ~ring->align_mask;
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while (ndw > (ring->ring_free_dw - 1)) {
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radeon_ring_free_size(rdev, ring);
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@ -159,7 +159,17 @@ int radeon_uvd_suspend(struct radeon_device *rdev)
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if (!r) {
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radeon_bo_kunmap(rdev->uvd.vcpu_bo);
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radeon_bo_unpin(rdev->uvd.vcpu_bo);
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rdev->uvd.cpu_addr = NULL;
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if (!radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_CPU, NULL)) {
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radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr);
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}
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radeon_bo_unreserve(rdev->uvd.vcpu_bo);
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if (rdev->uvd.cpu_addr) {
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radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX);
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} else {
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rdev->fence_drv[R600_RING_TYPE_UVD_INDEX].cpu_addr = NULL;
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}
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}
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return r;
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}
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@ -178,6 +188,10 @@ int radeon_uvd_resume(struct radeon_device *rdev)
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return r;
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}
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/* Have been pin in cpu unmap unpin */
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radeon_bo_kunmap(rdev->uvd.vcpu_bo);
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radeon_bo_unpin(rdev->uvd.vcpu_bo);
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r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM,
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&rdev->uvd.gpu_addr);
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if (r) {
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@ -613,19 +627,19 @@ int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
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}
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/* stitch together an UVD create msg */
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msg[0] = 0x00000de4;
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msg[1] = 0x00000000;
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msg[2] = handle;
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msg[3] = 0x00000000;
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msg[4] = 0x00000000;
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msg[5] = 0x00000000;
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msg[6] = 0x00000000;
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msg[7] = 0x00000780;
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msg[8] = 0x00000440;
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msg[9] = 0x00000000;
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msg[10] = 0x01b37000;
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msg[0] = cpu_to_le32(0x00000de4);
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msg[1] = cpu_to_le32(0x00000000);
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msg[2] = cpu_to_le32(handle);
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msg[3] = cpu_to_le32(0x00000000);
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msg[4] = cpu_to_le32(0x00000000);
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msg[5] = cpu_to_le32(0x00000000);
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msg[6] = cpu_to_le32(0x00000000);
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msg[7] = cpu_to_le32(0x00000780);
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msg[8] = cpu_to_le32(0x00000440);
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msg[9] = cpu_to_le32(0x00000000);
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msg[10] = cpu_to_le32(0x01b37000);
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for (i = 11; i < 1024; ++i)
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msg[i] = 0x0;
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msg[i] = cpu_to_le32(0x0);
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radeon_bo_kunmap(bo);
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radeon_bo_unreserve(bo);
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@ -659,12 +673,12 @@ int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
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}
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/* stitch together an UVD destroy msg */
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msg[0] = 0x00000de4;
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msg[1] = 0x00000002;
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msg[2] = handle;
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msg[3] = 0x00000000;
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msg[0] = cpu_to_le32(0x00000de4);
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msg[1] = cpu_to_le32(0x00000002);
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msg[2] = cpu_to_le32(handle);
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msg[3] = cpu_to_le32(0x00000000);
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for (i = 4; i < 1024; ++i)
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msg[i] = 0x0;
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msg[i] = cpu_to_le32(0x0);
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radeon_bo_kunmap(bo);
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radeon_bo_unreserve(bo);
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