drm/i915/gen9+: Program watermarks as a separate step during evasion, v3.
The watermark updates for SKL style watermarks are no longer done in the plane callbacks, but are now called in a separate watermark update function that's called during the same vblank evasion, before the plane updates. This also gets rid of the global skl_results, which was required for keeping track of the current atomic commit. Changes since v1: - Move line unwrap to correct patch. (Lyude) - Make sure we don't regress ILK watermarks. (Matt) - Rephrase commit message. (Matt) Changes since v2: - Fix disable watermark check to use the correct way to determine single step watermark support. Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lyude <cpaul@redhat.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1478609742-13603-3-git-send-email-maarten.lankhorst@linux.intel.com [mlankhorst: Small whitespace fix in skl_initial_wm]
This commit is contained in:
Maarten Lankhorst
Родитель
ccf010fb94
Коммит
e62929b3f6
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@ -2047,13 +2047,6 @@ struct drm_i915_private {
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*/
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uint16_t skl_latency[8];
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/*
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* The skl_wm_values structure is a bit too big for stack
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* allocation, so we keep the staging struct where we store
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* intermediate results here instead.
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*/
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struct skl_wm_values skl_results;
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/* current hardware state */
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union {
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struct ilk_wm_values hw;
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@ -3391,9 +3391,6 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
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struct drm_framebuffer *fb = plane_state->base.fb;
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const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
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const struct skl_plane_wm *p_wm =
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&crtc_state->wm.skl.optimal.planes[0];
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int pipe = intel_crtc->pipe;
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u32 plane_ctl;
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unsigned int rotation = plane_state->base.rotation;
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@ -3429,9 +3426,6 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
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intel_crtc->adjusted_x = src_x;
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intel_crtc->adjusted_y = src_y;
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if (wm->dirty_pipes & drm_crtc_mask(&intel_crtc->base))
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skl_write_plane_wm(intel_crtc, p_wm, &wm->ddb, 0);
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I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
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I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
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I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
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@ -3464,18 +3458,8 @@ static void skylake_disable_primary_plane(struct drm_plane *primary,
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
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const struct skl_plane_wm *p_wm = &cstate->wm.skl.optimal.planes[0];
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int pipe = intel_crtc->pipe;
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/*
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* We only populate skl_results on watermark updates, and if the
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* plane's visiblity isn't actually changing neither is its watermarks.
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*/
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if (!crtc->primary->state->visible)
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skl_write_plane_wm(intel_crtc, p_wm,
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&dev_priv->wm.skl_results.ddb, 0);
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I915_WRITE(PLANE_CTL(pipe, 0), 0);
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I915_WRITE(PLANE_SURF(pipe, 0), 0);
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POSTING_READ(PLANE_SURF(pipe, 0));
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@ -10865,16 +10849,9 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
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const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
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const struct skl_plane_wm *p_wm =
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&cstate->wm.skl.optimal.planes[PLANE_CURSOR];
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int pipe = intel_crtc->pipe;
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uint32_t cntl = 0;
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if (INTEL_GEN(dev_priv) >= 9 && wm->dirty_pipes & drm_crtc_mask(crtc))
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skl_write_cursor_wm(intel_crtc, p_wm, &wm->ddb);
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if (plane_state && plane_state->base.visible) {
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cntl = MCURSOR_GAMMA_ENABLE;
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switch (plane_state->base.crtc_w) {
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@ -14425,8 +14402,17 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
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intel_check_cpu_fifo_underruns(dev_priv);
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intel_check_pch_fifo_underruns(dev_priv);
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if (!crtc->state->active)
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intel_update_watermarks(intel_crtc);
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if (!crtc->state->active) {
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/*
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* Make sure we don't call initial_watermarks
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* for ILK-style watermark updates.
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*/
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if (dev_priv->display.atomic_update_watermarks)
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dev_priv->display.initial_watermarks(intel_state,
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to_intel_crtc_state(crtc->state));
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else
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intel_update_watermarks(intel_crtc);
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}
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}
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}
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@ -14622,7 +14608,6 @@ static int intel_atomic_commit(struct drm_device *dev,
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drm_atomic_helper_swap_state(state, true);
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dev_priv->wm.distrust_bios_wm = false;
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dev_priv->wm.skl_results = intel_state->wm_results;
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intel_shared_dpll_commit(state);
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intel_atomic_track_fbs(state);
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@ -14946,7 +14931,7 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc,
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intel_pipe_update_start(intel_crtc);
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if (modeset)
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return;
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goto out;
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if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
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intel_color_set_csc(crtc->state);
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@ -14958,6 +14943,7 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc,
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else if (INTEL_GEN(dev_priv) >= 9)
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skl_detach_scalers(intel_crtc);
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out:
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if (dev_priv->display.atomic_update_watermarks)
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dev_priv->display.atomic_update_watermarks(old_intel_state,
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intel_cstate);
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@ -1744,13 +1744,6 @@ bool skl_ddb_allocation_equals(const struct skl_ddb_allocation *old,
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enum pipe pipe);
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bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
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struct intel_crtc *intel_crtc);
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void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
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const struct skl_plane_wm *wm,
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const struct skl_ddb_allocation *ddb);
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void skl_write_plane_wm(struct intel_crtc *intel_crtc,
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const struct skl_plane_wm *wm,
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const struct skl_ddb_allocation *ddb,
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int plane);
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uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
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bool ilk_disable_lp_wm(struct drm_device *dev);
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int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
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@ -4202,19 +4202,29 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
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struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
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struct drm_i915_private *dev_priv = to_i915(state->base.dev);
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struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
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const struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
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enum pipe pipe = crtc->pipe;
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int plane;
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if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
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return;
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I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
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for_each_universal_plane(dev_priv, pipe, plane)
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skl_write_plane_wm(crtc, &pipe_wm->planes[plane], ddb, plane);
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skl_write_cursor_wm(crtc, &pipe_wm->planes[PLANE_CURSOR], ddb);
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}
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static void skl_update_wm(struct intel_crtc *intel_crtc)
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static void skl_initial_wm(struct intel_atomic_state *state,
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struct intel_crtc_state *cstate)
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{
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struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
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struct drm_device *dev = intel_crtc->base.dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct skl_wm_values *results = &dev_priv->wm.skl_results;
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struct skl_wm_values *results = &state->wm_results;
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struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
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struct intel_crtc_state *cstate = to_intel_crtc_state(intel_crtc->base.state);
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struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
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enum pipe pipe = intel_crtc->pipe;
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if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
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@ -4222,22 +4232,8 @@ static void skl_update_wm(struct intel_crtc *intel_crtc)
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mutex_lock(&dev_priv->wm.wm_mutex);
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/*
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* If this pipe isn't active already, we're going to be enabling it
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* very soon. Since it's safe to update a pipe's ddb allocation while
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* the pipe's shut off, just do so here. Already active pipes will have
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* their watermarks updated once we update their planes.
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*/
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if (intel_crtc->base.state->active_changed) {
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int plane;
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for_each_universal_plane(dev_priv, pipe, plane)
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skl_write_plane_wm(intel_crtc, &pipe_wm->planes[plane],
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&results->ddb, plane);
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skl_write_cursor_wm(intel_crtc, &pipe_wm->planes[PLANE_CURSOR],
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&results->ddb);
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}
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if (cstate->base.active_changed)
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skl_atomic_update_crtc_wm(state, cstate);
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skl_copy_wm_for_pipe(hw_vals, results, pipe);
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@ -7706,7 +7702,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
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/* For FIFO watermark updates */
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if (INTEL_GEN(dev_priv) >= 9) {
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skl_setup_wm_latency(dev_priv);
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dev_priv->display.update_wm = skl_update_wm;
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dev_priv->display.initial_watermarks = skl_initial_wm;
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dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;
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dev_priv->display.compute_global_watermarks = skl_compute_wm;
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} else if (HAS_PCH_SPLIT(dev_priv)) {
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@ -203,13 +203,8 @@ skl_update_plane(struct drm_plane *drm_plane,
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_plane *intel_plane = to_intel_plane(drm_plane);
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struct drm_framebuffer *fb = plane_state->base.fb;
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const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
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struct drm_crtc *crtc = crtc_state->base.crtc;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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const int pipe = intel_plane->pipe;
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const int plane = intel_plane->plane + 1;
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const struct skl_plane_wm *p_wm =
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&crtc_state->wm.skl.optimal.planes[plane];
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u32 plane_ctl;
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const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
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u32 surf_addr = plane_state->main.offset;
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@ -233,9 +228,6 @@ skl_update_plane(struct drm_plane *drm_plane,
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plane_ctl |= skl_plane_ctl_rotation(rotation);
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if (wm->dirty_pipes & drm_crtc_mask(crtc))
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skl_write_plane_wm(intel_crtc, p_wm, &wm->ddb, plane);
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if (key->flags) {
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I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value);
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I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value);
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@ -291,19 +283,9 @@ skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
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struct drm_device *dev = dplane->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_plane *intel_plane = to_intel_plane(dplane);
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struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
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const int pipe = intel_plane->pipe;
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const int plane = intel_plane->plane + 1;
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/*
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* We only populate skl_results on watermark updates, and if the
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* plane's visiblity isn't actually changing neither is its watermarks.
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*/
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if (!dplane->state->visible)
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skl_write_plane_wm(to_intel_crtc(crtc),
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&cstate->wm.skl.optimal.planes[plane],
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&dev_priv->wm.skl_results.ddb, plane);
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I915_WRITE(PLANE_CTL(pipe, plane), 0);
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I915_WRITE(PLANE_SURF(pipe, plane), 0);
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