OMAPDSS: DSI: Maintain own copy of timings in driver data
The DSI driver currently relies on the timings in omap_dss_device struct to configure the DISPC and DSI blocks accordingly. This makes the DSI interface driver dependent on the omap_dss_device struct. Make the DSI driver data maintain it's own timings field. A DSI video mode panel driver is expected to call omapdss_dsi_set_timings() to set these timings before the panel is enabled. Signed-off-by: Archit Taneja <archit@ti.com>
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bdcae3cc39
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e67458a831
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@ -333,6 +333,7 @@ struct dsi_data {
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unsigned scp_clk_refcount;
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struct dss_lcd_mgr_config mgr_config;
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struct omap_video_timings timings;
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};
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struct dsi_packet_sent_handler_data {
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@ -3610,9 +3611,10 @@ static void dsi_config_vp_num_line_buffers(struct omap_dss_device *dssdev)
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int num_line_buffers;
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if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
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struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
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int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
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unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
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struct omap_video_timings *timings = &dssdev->panel.timings;
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struct omap_video_timings *timings = &dsi->timings;
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/*
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* Don't use line buffers if width is greater than the video
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* port's line buffer size
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@ -3741,7 +3743,7 @@ static void dsi_config_cmd_mode_interleaving(struct omap_dss_device *dssdev)
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int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat;
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int tclk_trail, ths_exit, exiths_clk;
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bool ddr_alwon;
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struct omap_video_timings *timings = &dssdev->panel.timings;
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struct omap_video_timings *timings = &dsi->timings;
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int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
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int ndl = dsi->num_lanes_used - 1;
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int dsi_fclk_hsdiv = dssdev->clocks.dsi.regm_dsi + 1;
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@ -3994,7 +3996,7 @@ static void dsi_proto_timings(struct omap_dss_device *dssdev)
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int vbp = dssdev->panel.dsi_vm_data.vbp;
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int window_sync = dssdev->panel.dsi_vm_data.window_sync;
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bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end;
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struct omap_video_timings *timings = &dssdev->panel.timings;
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struct omap_video_timings *timings = &dsi->timings;
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int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
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int tl, t_he, width_bytes;
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@ -4103,6 +4105,7 @@ EXPORT_SYMBOL(omapdss_dsi_configure_pins);
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int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
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{
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struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
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struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
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int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
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u8 data_type;
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u16 word_count;
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@ -4133,7 +4136,7 @@ int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
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/* MODE, 1 = video mode */
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REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
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word_count = DIV_ROUND_UP(dssdev->panel.timings.x_res * bpp, 8);
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word_count = DIV_ROUND_UP(dsi->timings.x_res * bpp, 8);
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dsi_vc_write_long_header(dsidev, channel, data_type,
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word_count, 0);
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@ -4367,7 +4370,6 @@ static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
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{
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struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
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struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
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struct omap_video_timings timings;
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int r;
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u32 irq = 0;
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@ -4376,14 +4378,14 @@ static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
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dssdev->driver->get_resolution(dssdev, &dw, &dh);
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timings.x_res = dw;
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timings.y_res = dh;
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timings.hsw = 1;
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timings.hfp = 1;
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timings.hbp = 1;
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timings.vsw = 1;
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timings.vfp = 0;
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timings.vbp = 0;
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dsi->timings.x_res = dw;
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dsi->timings.y_res = dh;
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dsi->timings.hsw = 1;
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dsi->timings.hfp = 1;
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dsi->timings.hbp = 1;
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dsi->timings.vsw = 1;
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dsi->timings.vfp = 0;
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dsi->timings.vbp = 0;
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irq = dispc_mgr_get_framedone_irq(dssdev->manager->id);
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@ -4397,8 +4399,6 @@ static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
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dsi->mgr_config.stallmode = true;
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dsi->mgr_config.fifohandcheck = true;
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} else {
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timings = dssdev->panel.timings;
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dsi->mgr_config.stallmode = false;
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dsi->mgr_config.fifohandcheck = false;
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}
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@ -4407,14 +4407,14 @@ static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
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* override interlace, logic level and edge related parameters in
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* omap_video_timings with default values
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*/
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timings.interlace = false;
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timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
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timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
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timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
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timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH;
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timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES;
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dsi->timings.interlace = false;
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dsi->timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
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dsi->timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
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dsi->timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
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dsi->timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH;
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dsi->timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES;
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dss_mgr_set_timings(dssdev->manager, &timings);
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dss_mgr_set_timings(dssdev->manager, &dsi->timings);
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r = dsi_configure_dispc_clocks(dssdev);
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if (r)
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@ -4653,6 +4653,20 @@ int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
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}
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EXPORT_SYMBOL(omapdss_dsi_enable_te);
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void omapdss_dsi_set_timings(struct omap_dss_device *dssdev,
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struct omap_video_timings *timings)
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{
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struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
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struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
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mutex_lock(&dsi->lock);
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dsi->timings = *timings;
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mutex_unlock(&dsi->lock);
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}
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EXPORT_SYMBOL(omapdss_dsi_set_timings);
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static int __init dsi_init_display(struct omap_dss_device *dssdev)
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{
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struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
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@ -719,6 +719,8 @@ int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
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void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
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bool enable);
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int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
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void omapdss_dsi_set_timings(struct omap_dss_device *dssdev,
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struct omap_video_timings *timings);
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int omap_dsi_update(struct omap_dss_device *dssdev, int channel,
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void (*callback)(int, void *), void *data);
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