ASoC: Intel: Skylake: Support multi-core in Broxton
Add multicore DSP support in Broxton DSP operations. Signed-off-by: Jayachandran B <jayachandran.b@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Jayachandran B
Mark Brown
Родитель
40a166039a
Коммит
e68aca08d7
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@ -37,11 +37,19 @@
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#define BXT_ADSP_SRAM1_BASE 0xA0000
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#define BXT_INSTANCE_ID 0
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#define BXT_BASE_FW_MODULE_ID 0
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static unsigned int bxt_get_errorcode(struct sst_dsp *ctx)
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{
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return sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE);
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}
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/*
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* First boot sequence has some extra steps. Core 0 waits for power
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* status on core 1, so power up core 1 also momentarily, keep it in
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* reset/stall and then turn it off
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*/
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static int sst_bxt_prepare_fw(struct sst_dsp *ctx,
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const void *fwdata, u32 fwsize)
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{
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@ -49,7 +57,7 @@ static int sst_bxt_prepare_fw(struct sst_dsp *ctx,
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u32 reg;
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stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab);
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if (stream_tag < 0) {
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if (stream_tag <= 0) {
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dev_err(ctx->dev, "Failed to prepare DMA FW loading err: %x\n",
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stream_tag);
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return stream_tag;
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@ -58,16 +66,19 @@ static int sst_bxt_prepare_fw(struct sst_dsp *ctx,
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ctx->dsp_ops.stream_tag = stream_tag;
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memcpy(ctx->dmab.area, fwdata, fwsize);
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ret = skl_dsp_core_power_up(ctx, SKL_DSP_CORE0_MASK);
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/* Step 1: Power up core 0 and core1 */
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ret = skl_dsp_core_power_up(ctx, SKL_DSP_CORE0_MASK |
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SKL_DSP_CORE_MASK(1));
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if (ret < 0) {
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dev_err(ctx->dev, "Boot dsp core failed ret: %d\n", ret);
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dev_err(ctx->dev, "dsp core0/1 power up failed\n");
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goto base_fw_load_failed;
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}
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/* Purge FW request */
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/* Step 2: Purge FW request */
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sst_dsp_shim_write(ctx, SKL_ADSP_REG_HIPCI, SKL_ADSP_REG_HIPCI_BUSY |
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(BXT_IPC_PURGE_FW | ((stream_tag - 1) << 9)));
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/* Step 3: Unset core0 reset state & unstall/run core0 */
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ret = skl_dsp_start_core(ctx, SKL_DSP_CORE0_MASK);
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if (ret < 0) {
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dev_err(ctx->dev, "Start dsp core failed ret: %d\n", ret);
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@ -75,6 +86,7 @@ static int sst_bxt_prepare_fw(struct sst_dsp *ctx,
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goto base_fw_load_failed;
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}
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/* Step 4: Wait for DONE Bit */
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for (i = BXT_INIT_TIMEOUT; i > 0; --i) {
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reg = sst_dsp_shim_read(ctx, SKL_ADSP_REG_HIPCIE);
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@ -94,10 +106,18 @@ static int sst_bxt_prepare_fw(struct sst_dsp *ctx,
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SKL_ADSP_REG_HIPCIE_DONE);
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}
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/* enable Interrupt */
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/* Step 5: power down core1 */
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ret = skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
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if (ret < 0) {
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dev_err(ctx->dev, "dsp core1 power down failed\n");
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goto base_fw_load_failed;
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}
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/* Step 6: Enable Interrupt */
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skl_ipc_int_enable(ctx);
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skl_ipc_op_int_enable(ctx);
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/* Step 7: Wait for ROM init */
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for (i = BXT_INIT_TIMEOUT; i > 0; --i) {
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if (SKL_FW_INIT ==
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(sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS) &
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@ -194,7 +214,6 @@ static int bxt_load_base_firmware(struct sst_dsp *ctx)
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skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
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ret = -EIO;
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} else {
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skl_dsp_set_state_locked(ctx, SKL_DSP_RUNNING);
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ret = 0;
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skl->fw_loaded = true;
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}
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@ -209,67 +228,110 @@ static int bxt_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id)
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{
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struct skl_sst *skl = ctx->thread_context;
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int ret;
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skl->boot_complete = false;
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struct skl_ipc_dxstate_info dx;
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unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
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if (skl->fw_loaded == false) {
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dev_dbg(ctx->dev, "Re-loading fw\n");
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ret = bxt_load_base_firmware(ctx);
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if (ret < 0)
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dev_err(ctx->dev, "reload fw failed: %d\n", ret);
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return ret;
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}
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ret = skl_dsp_enable_core(ctx, SKL_DSP_CORE0_MASK);
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if (ret < 0) {
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dev_err(ctx->dev, "enable dsp core failed ret: %d\n", ret);
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return ret;
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/* If core 0 is being turned on, turn on core 1 as well */
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if (core_id == SKL_DSP_CORE0_ID)
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ret = skl_dsp_core_power_up(ctx, core_mask |
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SKL_DSP_CORE_MASK(1));
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else
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ret = skl_dsp_core_power_up(ctx, core_mask);
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if (ret < 0)
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goto err;
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if (core_id == SKL_DSP_CORE0_ID) {
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/*
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* Enable interrupt after SPA is set and before
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* DSP is unstalled
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*/
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skl_ipc_int_enable(ctx);
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skl_ipc_op_int_enable(ctx);
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skl->boot_complete = false;
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}
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/* enable interrupt */
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skl_ipc_int_enable(ctx);
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skl_ipc_op_int_enable(ctx);
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ret = skl_dsp_start_core(ctx, core_mask);
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if (ret < 0)
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goto err;
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ret = wait_event_timeout(skl->boot_wait, skl->boot_complete,
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msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
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if (ret == 0) {
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dev_err(ctx->dev, "ipc: error DSP boot timeout\n");
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dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
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sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
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sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
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return -EIO;
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if (core_id == SKL_DSP_CORE0_ID) {
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ret = wait_event_timeout(skl->boot_wait,
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skl->boot_complete,
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msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
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/* If core 1 was turned on for booting core 0, turn it off */
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skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
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if (ret == 0) {
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dev_err(ctx->dev, "%s: DSP boot timeout\n", __func__);
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dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
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sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
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sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
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dev_err(ctx->dev, "Failed to set core0 to D0 state\n");
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ret = -EIO;
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goto err;
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}
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}
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skl_dsp_set_state_locked(ctx, SKL_DSP_RUNNING);
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/* Tell FW if additional core in now On */
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if (core_id != SKL_DSP_CORE0_ID) {
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dx.core_mask = core_mask;
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dx.dx_mask = core_mask;
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ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID,
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BXT_BASE_FW_MODULE_ID, &dx);
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if (ret < 0) {
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dev_err(ctx->dev, "IPC set_dx for core %d fail: %d\n",
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core_id, ret);
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goto err;
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}
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}
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skl->cores.state[core_id] = SKL_DSP_RUNNING;
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return 0;
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err:
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if (core_id == SKL_DSP_CORE0_ID)
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core_mask |= SKL_DSP_CORE_MASK(1);
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skl_dsp_disable_core(ctx, core_mask);
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return ret;
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}
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static int bxt_set_dsp_D3(struct sst_dsp *ctx, unsigned int core_id)
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{
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int ret;
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struct skl_ipc_dxstate_info dx;
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struct skl_sst *skl = ctx->thread_context;
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int ret = 0;
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unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
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if (!is_skl_dsp_running(ctx))
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return ret;
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dx.core_mask = SKL_DSP_CORE0_MASK;
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dx.core_mask = core_mask;
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dx.dx_mask = SKL_IPC_D3_MASK;
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ret = skl_ipc_set_dx(&skl->ipc, SKL_INSTANCE_ID,
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SKL_BASE_FW_MODULE_ID, &dx);
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dev_dbg(ctx->dev, "core mask=%x dx_mask=%x\n",
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dx.core_mask, dx.dx_mask);
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ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID,
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BXT_BASE_FW_MODULE_ID, &dx);
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if (ret < 0)
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dev_err(ctx->dev,
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"Failed to set DSP to D3:core id = %d;Continue reset\n",
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core_id);
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ret = skl_dsp_disable_core(ctx, core_mask);
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if (ret < 0) {
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dev_err(ctx->dev, "Failed to set DSP to D3 state: %d\n", ret);
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dev_err(ctx->dev, "Failed to disable core %d", ret);
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return ret;
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}
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ret = skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
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if (ret < 0) {
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dev_err(ctx->dev, "disbale dsp core failed: %d\n", ret);
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ret = -EIO;
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}
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skl_dsp_set_state_locked(ctx, SKL_DSP_RESET);
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skl->cores.state[core_id] = SKL_DSP_RESET;
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return 0;
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}
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