Merge branch 'at91-3.4-base+9x5' of git://github.com/at91linux/linux-at91 into next/soc
* 'at91-3.4-base+9x5' of git://github.com/at91linux/linux-at91: ARM: at91/at91sam9x5: Device tree definition files ARM: at91/at91sam9x5: SoC basic support ARM: at91/at91sam9x5: Configuration and Makefile ARM: at91/at91sam9x5: clock management for at91sam9x5 chip family ARM: at91/at91sam9x5: PMC header file ARM: at91/at91sam9x5: overall definition ARM: at91: code removal of CAP9 SoC Conflicts: arch/arm/mach-at91/at91cap9.c
This commit is contained in:
Olof Johansson
Коммит
e69128b947
|
|
@ -510,17 +510,3 @@ Why: The pci_scan_bus_parented() interface creates a new root bus. The
|
||||||
convert to using pci_scan_root_bus() so they can supply a list of
|
convert to using pci_scan_root_bus() so they can supply a list of
|
||||||
bus resources when the bus is created.
|
bus resources when the bus is created.
|
||||||
Who: Bjorn Helgaas <bhelgaas@google.com>
|
Who: Bjorn Helgaas <bhelgaas@google.com>
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||||||
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|
||||||
----------------------------
|
|
||||||
|
|
||||||
What: The CAP9 SoC family will be removed
|
|
||||||
When: 3.4
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|
||||||
Files: arch/arm/mach-at91/at91cap9.c
|
|
||||||
arch/arm/mach-at91/at91cap9_devices.c
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|
||||||
arch/arm/mach-at91/include/mach/at91cap9.h
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|
||||||
arch/arm/mach-at91/include/mach/at91cap9_matrix.h
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|
||||||
arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
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|
||||||
arch/arm/mach-at91/board-cap9adk.c
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|
||||||
Why: The code is not actively maintained and platforms are now hard to find.
|
|
||||||
Who: Nicolas Ferre <nicolas.ferre@atmel.com>
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|
||||||
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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|
||||||
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||||||
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|
@ -324,7 +324,7 @@ config ARCH_AT91
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||||||
select CLKDEV_LOOKUP
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select CLKDEV_LOOKUP
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||||||
help
|
help
|
||||||
This enables support for systems based on the Atmel AT91RM9200,
|
This enables support for systems based on the Atmel AT91RM9200,
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||||||
AT91SAM9 and AT91CAP9 processors.
|
AT91SAM9 processors.
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||||||
|
|
||||||
config ARCH_BCMRING
|
config ARCH_BCMRING
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||||||
bool "Broadcom BCMRING"
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bool "Broadcom BCMRING"
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||||||
|
|
|
||||||
|
|
@ -86,7 +86,7 @@ choice
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||||||
depends on HAVE_AT91_DBGU0
|
depends on HAVE_AT91_DBGU0
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||||||
|
|
||||||
config AT91_DEBUG_LL_DBGU1
|
config AT91_DEBUG_LL_DBGU1
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||||||
bool "Kernel low-level debugging on 9263, 9g45 and cap9"
|
bool "Kernel low-level debugging on 9263 and 9g45"
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||||||
depends on HAVE_AT91_DBGU1
|
depends on HAVE_AT91_DBGU1
|
||||||
|
|
||||||
config DEBUG_CLPS711X_UART1
|
config DEBUG_CLPS711X_UART1
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||||||
|
|
|
||||||
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|
@ -0,0 +1,37 @@
|
||||||
|
/*
|
||||||
|
* at91sam9g25ek.dts - Device Tree file for AT91SAM9G25-EK board
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||||||
|
*
|
||||||
|
* Copyright (C) 2012 Atmel,
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||||||
|
* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
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||||||
|
*
|
||||||
|
* Licensed under GPLv2 or later.
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||||||
|
*/
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||||||
|
/dts-v1/;
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||||||
|
/include/ "at91sam9x5.dtsi"
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||||||
|
/include/ "at91sam9x5cm.dtsi"
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||||||
|
|
||||||
|
/ {
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||||||
|
model = "Atmel AT91SAM9G25-EK";
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||||||
|
compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
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||||||
|
|
||||||
|
chosen {
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||||||
|
bootargs = "128M console=ttyS0,115200 mtdparts=atmel_nand:8M(bootstrap/uboot/kernel)ro,-(rootfs) root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
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||||||
|
};
|
||||||
|
|
||||||
|
ahb {
|
||||||
|
apb {
|
||||||
|
dbgu: serial@fffff200 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
usart0: serial@f801c000 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
macb0: ethernet@f802c000 {
|
||||||
|
phy-mode = "rmii";
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,172 @@
|
||||||
|
/*
|
||||||
|
* at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
|
||||||
|
* applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
|
||||||
|
* AT91SAM9X25, AT91SAM9X35 SoC
|
||||||
|
*
|
||||||
|
* Copyright (C) 2012 Atmel,
|
||||||
|
* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||||
|
*
|
||||||
|
* Licensed under GPLv2 or later.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/include/ "skeleton.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Atmel AT91SAM9x5 family SoC";
|
||||||
|
compatible = "atmel,at91sam9x5";
|
||||||
|
interrupt-parent = <&aic>;
|
||||||
|
|
||||||
|
aliases {
|
||||||
|
serial0 = &dbgu;
|
||||||
|
serial1 = &usart0;
|
||||||
|
serial2 = &usart1;
|
||||||
|
serial3 = &usart2;
|
||||||
|
gpio0 = &pioA;
|
||||||
|
gpio1 = &pioB;
|
||||||
|
gpio2 = &pioC;
|
||||||
|
gpio3 = &pioD;
|
||||||
|
tcb0 = &tcb0;
|
||||||
|
tcb1 = &tcb1;
|
||||||
|
};
|
||||||
|
cpus {
|
||||||
|
cpu@0 {
|
||||||
|
compatible = "arm,arm926ejs";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
memory@20000000 {
|
||||||
|
reg = <0x20000000 0x10000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
ahb {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges;
|
||||||
|
|
||||||
|
apb {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges;
|
||||||
|
|
||||||
|
aic: interrupt-controller@fffff000 {
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
compatible = "atmel,at91rm9200-aic";
|
||||||
|
interrupt-controller;
|
||||||
|
interrupt-parent;
|
||||||
|
reg = <0xfffff000 0x200>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pit: timer@fffffe30 {
|
||||||
|
compatible = "atmel,at91sam9260-pit";
|
||||||
|
reg = <0xfffffe30 0xf>;
|
||||||
|
interrupts = <1 4>;
|
||||||
|
};
|
||||||
|
|
||||||
|
tcb0: timer@f8008000 {
|
||||||
|
compatible = "atmel,at91sam9x5-tcb";
|
||||||
|
reg = <0xf8008000 0x100>;
|
||||||
|
interrupts = <17 4>;
|
||||||
|
};
|
||||||
|
|
||||||
|
tcb1: timer@f800c000 {
|
||||||
|
compatible = "atmel,at91sam9x5-tcb";
|
||||||
|
reg = <0xf800c000 0x100>;
|
||||||
|
interrupts = <17 4>;
|
||||||
|
};
|
||||||
|
|
||||||
|
dma0: dma-controller@ffffec00 {
|
||||||
|
compatible = "atmel,at91sam9g45-dma";
|
||||||
|
reg = <0xffffec00 0x200>;
|
||||||
|
interrupts = <20 4>;
|
||||||
|
};
|
||||||
|
|
||||||
|
dma1: dma-controller@ffffee00 {
|
||||||
|
compatible = "atmel,at91sam9g45-dma";
|
||||||
|
reg = <0xffffee00 0x200>;
|
||||||
|
interrupts = <21 4>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pioA: gpio@fffff400 {
|
||||||
|
compatible = "atmel,at91rm9200-gpio";
|
||||||
|
reg = <0xfffff400 0x100>;
|
||||||
|
interrupts = <2 4>;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
gpio-controller;
|
||||||
|
};
|
||||||
|
|
||||||
|
pioB: gpio@fffff600 {
|
||||||
|
compatible = "atmel,at91rm9200-gpio";
|
||||||
|
reg = <0xfffff600 0x100>;
|
||||||
|
interrupts = <2 4>;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
gpio-controller;
|
||||||
|
};
|
||||||
|
|
||||||
|
pioC: gpio@fffff800 {
|
||||||
|
compatible = "atmel,at91rm9200-gpio";
|
||||||
|
reg = <0xfffff800 0x100>;
|
||||||
|
interrupts = <3 4>;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
gpio-controller;
|
||||||
|
};
|
||||||
|
|
||||||
|
pioD: gpio@fffffa00 {
|
||||||
|
compatible = "atmel,at91rm9200-gpio";
|
||||||
|
reg = <0xfffffa00 0x100>;
|
||||||
|
interrupts = <3 4>;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
gpio-controller;
|
||||||
|
};
|
||||||
|
|
||||||
|
dbgu: serial@fffff200 {
|
||||||
|
compatible = "atmel,at91sam9260-usart";
|
||||||
|
reg = <0xfffff200 0x200>;
|
||||||
|
interrupts = <1 4>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
usart0: serial@f801c000 {
|
||||||
|
compatible = "atmel,at91sam9260-usart";
|
||||||
|
reg = <0xf801c000 0x200>;
|
||||||
|
interrupts = <5 4>;
|
||||||
|
atmel,use-dma-rx;
|
||||||
|
atmel,use-dma-tx;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
usart1: serial@f8020000 {
|
||||||
|
compatible = "atmel,at91sam9260-usart";
|
||||||
|
reg = <0xf8020000 0x200>;
|
||||||
|
interrupts = <6 4>;
|
||||||
|
atmel,use-dma-rx;
|
||||||
|
atmel,use-dma-tx;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
usart2: serial@f8024000 {
|
||||||
|
compatible = "atmel,at91sam9260-usart";
|
||||||
|
reg = <0xf8024000 0x200>;
|
||||||
|
interrupts = <7 4>;
|
||||||
|
atmel,use-dma-rx;
|
||||||
|
atmel,use-dma-tx;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
macb0: ethernet@f802c000 {
|
||||||
|
compatible = "cdns,at32ap7000-macb", "cdns,macb";
|
||||||
|
reg = <0xf802c000 0x100>;
|
||||||
|
interrupts = <24 4>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
macb1: ethernet@f8030000 {
|
||||||
|
compatible = "cdns,at32ap7000-macb", "cdns,macb";
|
||||||
|
reg = <0xf8030000 0x100>;
|
||||||
|
interrupts = <27 4>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,14 @@
|
||||||
|
/*
|
||||||
|
* at91sam9x5cm.dtsi - Device Tree Include file for AT91SAM9x5 CPU Module
|
||||||
|
*
|
||||||
|
* Copyright (C) 2012 Atmel,
|
||||||
|
* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||||
|
*
|
||||||
|
* Licensed under GPLv2 or later.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/ {
|
||||||
|
memory@20000000 {
|
||||||
|
reg = <0x20000000 0x8000000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -1,108 +0,0 @@
|
||||||
CONFIG_EXPERIMENTAL=y
|
|
||||||
# CONFIG_LOCALVERSION_AUTO is not set
|
|
||||||
# CONFIG_SWAP is not set
|
|
||||||
CONFIG_SYSVIPC=y
|
|
||||||
CONFIG_LOG_BUF_SHIFT=14
|
|
||||||
CONFIG_BLK_DEV_INITRD=y
|
|
||||||
CONFIG_SLAB=y
|
|
||||||
CONFIG_MODULES=y
|
|
||||||
CONFIG_MODULE_UNLOAD=y
|
|
||||||
# CONFIG_BLK_DEV_BSG is not set
|
|
||||||
# CONFIG_IOSCHED_DEADLINE is not set
|
|
||||||
# CONFIG_IOSCHED_CFQ is not set
|
|
||||||
CONFIG_ARCH_AT91=y
|
|
||||||
CONFIG_ARCH_AT91CAP9=y
|
|
||||||
CONFIG_MACH_AT91CAP9ADK=y
|
|
||||||
CONFIG_MTD_AT91_DATAFLASH_CARD=y
|
|
||||||
CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
|
|
||||||
# CONFIG_ARM_THUMB is not set
|
|
||||||
CONFIG_AEABI=y
|
|
||||||
CONFIG_LEDS=y
|
|
||||||
CONFIG_LEDS_CPU=y
|
|
||||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
|
||||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
|
||||||
CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/ram0 rw"
|
|
||||||
CONFIG_FPE_NWFPE=y
|
|
||||||
CONFIG_NET=y
|
|
||||||
CONFIG_PACKET=y
|
|
||||||
CONFIG_UNIX=y
|
|
||||||
CONFIG_INET=y
|
|
||||||
CONFIG_IP_PNP=y
|
|
||||||
CONFIG_IP_PNP_BOOTP=y
|
|
||||||
CONFIG_IP_PNP_RARP=y
|
|
||||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
|
||||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
|
||||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
|
||||||
# CONFIG_INET_LRO is not set
|
|
||||||
# CONFIG_INET_DIAG is not set
|
|
||||||
# CONFIG_IPV6 is not set
|
|
||||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
|
||||||
CONFIG_MTD=y
|
|
||||||
CONFIG_MTD_CMDLINE_PARTS=y
|
|
||||||
CONFIG_MTD_CHAR=y
|
|
||||||
CONFIG_MTD_BLOCK=y
|
|
||||||
CONFIG_MTD_CFI=y
|
|
||||||
CONFIG_MTD_JEDECPROBE=y
|
|
||||||
CONFIG_MTD_CFI_AMDSTD=y
|
|
||||||
CONFIG_MTD_PHYSMAP=y
|
|
||||||
CONFIG_MTD_DATAFLASH=y
|
|
||||||
CONFIG_MTD_NAND=y
|
|
||||||
CONFIG_MTD_NAND_ATMEL=y
|
|
||||||
CONFIG_BLK_DEV_LOOP=y
|
|
||||||
CONFIG_BLK_DEV_RAM=y
|
|
||||||
CONFIG_BLK_DEV_RAM_SIZE=8192
|
|
||||||
CONFIG_SCSI=y
|
|
||||||
CONFIG_BLK_DEV_SD=y
|
|
||||||
CONFIG_SCSI_MULTI_LUN=y
|
|
||||||
CONFIG_NETDEVICES=y
|
|
||||||
CONFIG_MII=y
|
|
||||||
CONFIG_MACB=y
|
|
||||||
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
|
|
||||||
CONFIG_INPUT_EVDEV=y
|
|
||||||
# CONFIG_INPUT_KEYBOARD is not set
|
|
||||||
# CONFIG_INPUT_MOUSE is not set
|
|
||||||
CONFIG_INPUT_TOUCHSCREEN=y
|
|
||||||
CONFIG_TOUCHSCREEN_ADS7846=y
|
|
||||||
# CONFIG_SERIO is not set
|
|
||||||
CONFIG_SERIAL_ATMEL=y
|
|
||||||
CONFIG_SERIAL_ATMEL_CONSOLE=y
|
|
||||||
CONFIG_HW_RANDOM=y
|
|
||||||
CONFIG_I2C=y
|
|
||||||
CONFIG_I2C_CHARDEV=y
|
|
||||||
CONFIG_SPI=y
|
|
||||||
CONFIG_SPI_ATMEL=y
|
|
||||||
# CONFIG_HWMON is not set
|
|
||||||
CONFIG_WATCHDOG=y
|
|
||||||
CONFIG_WATCHDOG_NOWAYOUT=y
|
|
||||||
CONFIG_FB=y
|
|
||||||
CONFIG_FB_ATMEL=y
|
|
||||||
CONFIG_LOGO=y
|
|
||||||
# CONFIG_LOGO_LINUX_MONO is not set
|
|
||||||
# CONFIG_LOGO_LINUX_CLUT224 is not set
|
|
||||||
# CONFIG_USB_HID is not set
|
|
||||||
CONFIG_USB=y
|
|
||||||
CONFIG_USB_DEVICEFS=y
|
|
||||||
CONFIG_USB_MON=y
|
|
||||||
CONFIG_USB_OHCI_HCD=y
|
|
||||||
CONFIG_USB_STORAGE=y
|
|
||||||
CONFIG_USB_GADGET=y
|
|
||||||
CONFIG_USB_ETH=m
|
|
||||||
CONFIG_USB_FILE_STORAGE=m
|
|
||||||
CONFIG_MMC=y
|
|
||||||
CONFIG_MMC_AT91=m
|
|
||||||
CONFIG_RTC_CLASS=y
|
|
||||||
CONFIG_RTC_DRV_AT91SAM9=y
|
|
||||||
CONFIG_EXT2_FS=y
|
|
||||||
CONFIG_VFAT_FS=y
|
|
||||||
CONFIG_TMPFS=y
|
|
||||||
CONFIG_JFFS2_FS=y
|
|
||||||
CONFIG_CRAMFS=y
|
|
||||||
CONFIG_NFS_FS=y
|
|
||||||
CONFIG_ROOT_NFS=y
|
|
||||||
CONFIG_NLS_CODEPAGE_437=y
|
|
||||||
CONFIG_NLS_CODEPAGE_850=y
|
|
||||||
CONFIG_NLS_ISO8859_1=y
|
|
||||||
CONFIG_DEBUG_FS=y
|
|
||||||
CONFIG_DEBUG_KERNEL=y
|
|
||||||
CONFIG_DEBUG_INFO=y
|
|
||||||
CONFIG_DEBUG_USER=y
|
|
||||||
|
|
@ -102,13 +102,13 @@ config ARCH_AT91SAM9G45
|
||||||
select HAVE_AT91_DBGU1
|
select HAVE_AT91_DBGU1
|
||||||
select AT91_SAM9G45_RESET
|
select AT91_SAM9G45_RESET
|
||||||
|
|
||||||
config ARCH_AT91CAP9
|
config ARCH_AT91SAM9X5
|
||||||
bool "AT91CAP9"
|
bool "AT91SAM9x5 family"
|
||||||
select CPU_ARM926T
|
select CPU_ARM926T
|
||||||
select GENERIC_CLOCKEVENTS
|
select GENERIC_CLOCKEVENTS
|
||||||
select HAVE_FB_ATMEL
|
select HAVE_FB_ATMEL
|
||||||
select HAVE_NET_MACB
|
select HAVE_NET_MACB
|
||||||
select HAVE_AT91_DBGU1
|
select HAVE_AT91_DBGU0
|
||||||
select AT91_SAM9G45_RESET
|
select AT91_SAM9G45_RESET
|
||||||
|
|
||||||
config ARCH_AT91X40
|
config ARCH_AT91X40
|
||||||
|
|
@ -447,21 +447,6 @@ endif
|
||||||
|
|
||||||
# ----------------------------------------------------------
|
# ----------------------------------------------------------
|
||||||
|
|
||||||
if ARCH_AT91CAP9
|
|
||||||
|
|
||||||
comment "AT91CAP9 Board Type"
|
|
||||||
|
|
||||||
config MACH_AT91CAP9ADK
|
|
||||||
bool "Atmel AT91CAP9A-DK Evaluation Kit"
|
|
||||||
select HAVE_AT91_DATAFLASH_CARD
|
|
||||||
help
|
|
||||||
Select this if you are using Atmel's AT91CAP9A-DK Evaluation Kit.
|
|
||||||
<http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4138>
|
|
||||||
|
|
||||||
endif
|
|
||||||
|
|
||||||
# ----------------------------------------------------------
|
|
||||||
|
|
||||||
if ARCH_AT91X40
|
if ARCH_AT91X40
|
||||||
|
|
||||||
comment "AT91X40 Board Type"
|
comment "AT91X40 Board Type"
|
||||||
|
|
@ -544,7 +529,7 @@ config AT91_EARLY_DBGU0
|
||||||
depends on HAVE_AT91_DBGU0
|
depends on HAVE_AT91_DBGU0
|
||||||
|
|
||||||
config AT91_EARLY_DBGU1
|
config AT91_EARLY_DBGU1
|
||||||
bool "DBGU on 9263, 9g45 and cap9"
|
bool "DBGU on 9263 and 9g45"
|
||||||
depends on HAVE_AT91_DBGU1
|
depends on HAVE_AT91_DBGU1
|
||||||
|
|
||||||
config AT91_EARLY_USART0
|
config AT91_EARLY_USART0
|
||||||
|
|
|
||||||
|
|
@ -20,7 +20,7 @@ obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_d
|
||||||
obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
|
obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
|
||||||
obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
|
obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
|
||||||
obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
|
obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
|
||||||
obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
|
obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5.o at91sam926x_time.o
|
||||||
obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
|
obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
|
||||||
|
|
||||||
# AT91RM9200 board-specific support
|
# AT91RM9200 board-specific support
|
||||||
|
|
@ -81,9 +81,6 @@ obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
|
||||||
# AT91SAM board with device-tree
|
# AT91SAM board with device-tree
|
||||||
obj-$(CONFIG_MACH_AT91SAM_DT) += board-dt.o
|
obj-$(CONFIG_MACH_AT91SAM_DT) += board-dt.o
|
||||||
|
|
||||||
# AT91CAP9 board-specific support
|
|
||||||
obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o
|
|
||||||
|
|
||||||
# AT91X40 board-specific support
|
# AT91X40 board-specific support
|
||||||
obj-$(CONFIG_MACH_AT91EB01) += board-eb01.o
|
obj-$(CONFIG_MACH_AT91EB01) += board-eb01.o
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -3,11 +3,7 @@
|
||||||
# PARAMS_PHYS must be within 4MB of ZRELADDR
|
# PARAMS_PHYS must be within 4MB of ZRELADDR
|
||||||
# INITRD_PHYS must be in RAM
|
# INITRD_PHYS must be in RAM
|
||||||
|
|
||||||
ifeq ($(CONFIG_ARCH_AT91CAP9),y)
|
ifeq ($(CONFIG_ARCH_AT91SAM9G45),y)
|
||||||
zreladdr-y += 0x70008000
|
|
||||||
params_phys-y := 0x70000100
|
|
||||||
initrd_phys-y := 0x70410000
|
|
||||||
else ifeq ($(CONFIG_ARCH_AT91SAM9G45),y)
|
|
||||||
zreladdr-y += 0x70008000
|
zreladdr-y += 0x70008000
|
||||||
params_phys-y := 0x70000100
|
params_phys-y := 0x70000100
|
||||||
initrd_phys-y := 0x70410000
|
initrd_phys-y := 0x70410000
|
||||||
|
|
|
||||||
|
|
@ -1,404 +0,0 @@
|
||||||
/*
|
|
||||||
* arch/arm/mach-at91/at91cap9.c
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
|
|
||||||
* Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
|
|
||||||
* Copyright (C) 2007 Atmel Corporation.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; either version 2 of the License, or
|
|
||||||
* (at your option) any later version.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <linux/module.h>
|
|
||||||
|
|
||||||
#include <asm/proc-fns.h>
|
|
||||||
#include <asm/irq.h>
|
|
||||||
#include <asm/mach/arch.h>
|
|
||||||
#include <asm/mach/map.h>
|
|
||||||
|
|
||||||
#include <mach/cpu.h>
|
|
||||||
#include <mach/at91cap9.h>
|
|
||||||
#include <mach/at91_pmc.h>
|
|
||||||
|
|
||||||
#include "soc.h"
|
|
||||||
#include "generic.h"
|
|
||||||
#include "clock.h"
|
|
||||||
#include "sam9_smc.h"
|
|
||||||
|
|
||||||
/* --------------------------------------------------------------------
|
|
||||||
* Clocks
|
|
||||||
* -------------------------------------------------------------------- */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* The peripheral clocks.
|
|
||||||
*/
|
|
||||||
static struct clk pioABCD_clk = {
|
|
||||||
.name = "pioABCD_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_PIOABCD,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk mpb0_clk = {
|
|
||||||
.name = "mpb0_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_MPB0,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk mpb1_clk = {
|
|
||||||
.name = "mpb1_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_MPB1,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk mpb2_clk = {
|
|
||||||
.name = "mpb2_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_MPB2,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk mpb3_clk = {
|
|
||||||
.name = "mpb3_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_MPB3,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk mpb4_clk = {
|
|
||||||
.name = "mpb4_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_MPB4,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk usart0_clk = {
|
|
||||||
.name = "usart0_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_US0,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk usart1_clk = {
|
|
||||||
.name = "usart1_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_US1,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk usart2_clk = {
|
|
||||||
.name = "usart2_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_US2,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk mmc0_clk = {
|
|
||||||
.name = "mci0_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_MCI0,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk mmc1_clk = {
|
|
||||||
.name = "mci1_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_MCI1,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk can_clk = {
|
|
||||||
.name = "can_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_CAN,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk twi_clk = {
|
|
||||||
.name = "twi_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_TWI,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk spi0_clk = {
|
|
||||||
.name = "spi0_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_SPI0,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk spi1_clk = {
|
|
||||||
.name = "spi1_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_SPI1,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk ssc0_clk = {
|
|
||||||
.name = "ssc0_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_SSC0,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk ssc1_clk = {
|
|
||||||
.name = "ssc1_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_SSC1,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk ac97_clk = {
|
|
||||||
.name = "ac97_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_AC97C,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk tcb_clk = {
|
|
||||||
.name = "tcb_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_TCB,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk pwm_clk = {
|
|
||||||
.name = "pwm_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_PWMC,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk macb_clk = {
|
|
||||||
.name = "pclk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_EMAC,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk aestdes_clk = {
|
|
||||||
.name = "aestdes_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_AESTDES,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk adc_clk = {
|
|
||||||
.name = "adc_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_ADC,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk isi_clk = {
|
|
||||||
.name = "isi_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_ISI,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk lcdc_clk = {
|
|
||||||
.name = "lcdc_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_LCDC,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk dma_clk = {
|
|
||||||
.name = "dma_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_DMA,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk udphs_clk = {
|
|
||||||
.name = "udphs_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_UDPHS,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
static struct clk ohci_clk = {
|
|
||||||
.name = "ohci_clk",
|
|
||||||
.pmc_mask = 1 << AT91CAP9_ID_UHP,
|
|
||||||
.type = CLK_TYPE_PERIPHERAL,
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct clk *periph_clocks[] __initdata = {
|
|
||||||
&pioABCD_clk,
|
|
||||||
&mpb0_clk,
|
|
||||||
&mpb1_clk,
|
|
||||||
&mpb2_clk,
|
|
||||||
&mpb3_clk,
|
|
||||||
&mpb4_clk,
|
|
||||||
&usart0_clk,
|
|
||||||
&usart1_clk,
|
|
||||||
&usart2_clk,
|
|
||||||
&mmc0_clk,
|
|
||||||
&mmc1_clk,
|
|
||||||
&can_clk,
|
|
||||||
&twi_clk,
|
|
||||||
&spi0_clk,
|
|
||||||
&spi1_clk,
|
|
||||||
&ssc0_clk,
|
|
||||||
&ssc1_clk,
|
|
||||||
&ac97_clk,
|
|
||||||
&tcb_clk,
|
|
||||||
&pwm_clk,
|
|
||||||
&macb_clk,
|
|
||||||
&aestdes_clk,
|
|
||||||
&adc_clk,
|
|
||||||
&isi_clk,
|
|
||||||
&lcdc_clk,
|
|
||||||
&dma_clk,
|
|
||||||
&udphs_clk,
|
|
||||||
&ohci_clk,
|
|
||||||
// irq0 .. irq1
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct clk_lookup periph_clocks_lookups[] = {
|
|
||||||
/* One additional fake clock for macb_hclk */
|
|
||||||
CLKDEV_CON_ID("hclk", &macb_clk),
|
|
||||||
CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
|
|
||||||
CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
|
|
||||||
CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
|
|
||||||
CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
|
|
||||||
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
|
|
||||||
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
|
|
||||||
CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
|
|
||||||
CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
|
|
||||||
CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
|
|
||||||
/* fake hclk clock */
|
|
||||||
CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
|
|
||||||
CLKDEV_CON_ID("pioA", &pioABCD_clk),
|
|
||||||
CLKDEV_CON_ID("pioB", &pioABCD_clk),
|
|
||||||
CLKDEV_CON_ID("pioC", &pioABCD_clk),
|
|
||||||
CLKDEV_CON_ID("pioD", &pioABCD_clk),
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct clk_lookup usart_clocks_lookups[] = {
|
|
||||||
CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
|
|
||||||
CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
|
|
||||||
CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
|
|
||||||
CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* The four programmable clocks.
|
|
||||||
* You must configure pin multiplexing to bring these signals out.
|
|
||||||
*/
|
|
||||||
static struct clk pck0 = {
|
|
||||||
.name = "pck0",
|
|
||||||
.pmc_mask = AT91_PMC_PCK0,
|
|
||||||
.type = CLK_TYPE_PROGRAMMABLE,
|
|
||||||
.id = 0,
|
|
||||||
};
|
|
||||||
static struct clk pck1 = {
|
|
||||||
.name = "pck1",
|
|
||||||
.pmc_mask = AT91_PMC_PCK1,
|
|
||||||
.type = CLK_TYPE_PROGRAMMABLE,
|
|
||||||
.id = 1,
|
|
||||||
};
|
|
||||||
static struct clk pck2 = {
|
|
||||||
.name = "pck2",
|
|
||||||
.pmc_mask = AT91_PMC_PCK2,
|
|
||||||
.type = CLK_TYPE_PROGRAMMABLE,
|
|
||||||
.id = 2,
|
|
||||||
};
|
|
||||||
static struct clk pck3 = {
|
|
||||||
.name = "pck3",
|
|
||||||
.pmc_mask = AT91_PMC_PCK3,
|
|
||||||
.type = CLK_TYPE_PROGRAMMABLE,
|
|
||||||
.id = 3,
|
|
||||||
};
|
|
||||||
|
|
||||||
static void __init at91cap9_register_clocks(void)
|
|
||||||
{
|
|
||||||
int i;
|
|
||||||
|
|
||||||
for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
|
|
||||||
clk_register(periph_clocks[i]);
|
|
||||||
|
|
||||||
clkdev_add_table(periph_clocks_lookups,
|
|
||||||
ARRAY_SIZE(periph_clocks_lookups));
|
|
||||||
clkdev_add_table(usart_clocks_lookups,
|
|
||||||
ARRAY_SIZE(usart_clocks_lookups));
|
|
||||||
|
|
||||||
clk_register(&pck0);
|
|
||||||
clk_register(&pck1);
|
|
||||||
clk_register(&pck2);
|
|
||||||
clk_register(&pck3);
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct clk_lookup console_clock_lookup;
|
|
||||||
|
|
||||||
void __init at91cap9_set_console_clock(int id)
|
|
||||||
{
|
|
||||||
if (id >= ARRAY_SIZE(usart_clocks_lookups))
|
|
||||||
return;
|
|
||||||
|
|
||||||
console_clock_lookup.con_id = "usart";
|
|
||||||
console_clock_lookup.clk = usart_clocks_lookups[id].clk;
|
|
||||||
clkdev_add(&console_clock_lookup);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* --------------------------------------------------------------------
|
|
||||||
* GPIO
|
|
||||||
* -------------------------------------------------------------------- */
|
|
||||||
|
|
||||||
static struct at91_gpio_bank at91cap9_gpio[] __initdata = {
|
|
||||||
{
|
|
||||||
.id = AT91CAP9_ID_PIOABCD,
|
|
||||||
.regbase = AT91CAP9_BASE_PIOA,
|
|
||||||
}, {
|
|
||||||
.id = AT91CAP9_ID_PIOABCD,
|
|
||||||
.regbase = AT91CAP9_BASE_PIOB,
|
|
||||||
}, {
|
|
||||||
.id = AT91CAP9_ID_PIOABCD,
|
|
||||||
.regbase = AT91CAP9_BASE_PIOC,
|
|
||||||
}, {
|
|
||||||
.id = AT91CAP9_ID_PIOABCD,
|
|
||||||
.regbase = AT91CAP9_BASE_PIOD,
|
|
||||||
}
|
|
||||||
};
|
|
||||||
|
|
||||||
static void at91cap9_idle(void)
|
|
||||||
{
|
|
||||||
at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
|
|
||||||
cpu_do_idle();
|
|
||||||
}
|
|
||||||
|
|
||||||
/* --------------------------------------------------------------------
|
|
||||||
* AT91CAP9 processor initialization
|
|
||||||
* -------------------------------------------------------------------- */
|
|
||||||
|
|
||||||
static void __init at91cap9_map_io(void)
|
|
||||||
{
|
|
||||||
at91_init_sram(0, AT91CAP9_SRAM_BASE, AT91CAP9_SRAM_SIZE);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void __init at91cap9_ioremap_registers(void)
|
|
||||||
{
|
|
||||||
at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC);
|
|
||||||
at91_ioremap_rstc(AT91CAP9_BASE_RSTC);
|
|
||||||
at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT);
|
|
||||||
at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void __init at91cap9_initialize(void)
|
|
||||||
{
|
|
||||||
arm_pm_idle = at91cap9_idle;
|
|
||||||
arm_pm_restart = at91sam9g45_restart;
|
|
||||||
at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
|
|
||||||
|
|
||||||
/* Register GPIO subsystem */
|
|
||||||
at91_gpio_init(at91cap9_gpio, 4);
|
|
||||||
|
|
||||||
/* Remember the silicon revision */
|
|
||||||
if (cpu_is_at91cap9_revB())
|
|
||||||
system_rev = 0xB;
|
|
||||||
else if (cpu_is_at91cap9_revC())
|
|
||||||
system_rev = 0xC;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* --------------------------------------------------------------------
|
|
||||||
* Interrupt initialization
|
|
||||||
* -------------------------------------------------------------------- */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* The default interrupt priority levels (0 = lowest, 7 = highest).
|
|
||||||
*/
|
|
||||||
static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = {
|
|
||||||
7, /* Advanced Interrupt Controller (FIQ) */
|
|
||||||
7, /* System Peripherals */
|
|
||||||
1, /* Parallel IO Controller A, B, C and D */
|
|
||||||
0, /* MP Block Peripheral 0 */
|
|
||||||
0, /* MP Block Peripheral 1 */
|
|
||||||
0, /* MP Block Peripheral 2 */
|
|
||||||
0, /* MP Block Peripheral 3 */
|
|
||||||
0, /* MP Block Peripheral 4 */
|
|
||||||
5, /* USART 0 */
|
|
||||||
5, /* USART 1 */
|
|
||||||
5, /* USART 2 */
|
|
||||||
0, /* Multimedia Card Interface 0 */
|
|
||||||
0, /* Multimedia Card Interface 1 */
|
|
||||||
3, /* CAN */
|
|
||||||
6, /* Two-Wire Interface */
|
|
||||||
5, /* Serial Peripheral Interface 0 */
|
|
||||||
5, /* Serial Peripheral Interface 1 */
|
|
||||||
4, /* Serial Synchronous Controller 0 */
|
|
||||||
4, /* Serial Synchronous Controller 1 */
|
|
||||||
5, /* AC97 Controller */
|
|
||||||
0, /* Timer Counter 0, 1 and 2 */
|
|
||||||
0, /* Pulse Width Modulation Controller */
|
|
||||||
3, /* Ethernet */
|
|
||||||
0, /* Advanced Encryption Standard, Triple DES*/
|
|
||||||
0, /* Analog-to-Digital Converter */
|
|
||||||
0, /* Image Sensor Interface */
|
|
||||||
3, /* LCD Controller */
|
|
||||||
0, /* DMA Controller */
|
|
||||||
2, /* USB Device Port */
|
|
||||||
2, /* USB Host port */
|
|
||||||
0, /* Advanced Interrupt Controller (IRQ0) */
|
|
||||||
0, /* Advanced Interrupt Controller (IRQ1) */
|
|
||||||
};
|
|
||||||
|
|
||||||
struct at91_init_soc __initdata at91cap9_soc = {
|
|
||||||
.map_io = at91cap9_map_io,
|
|
||||||
.default_irq_priority = at91cap9_default_irq_priority,
|
|
||||||
.ioremap_registers = at91cap9_ioremap_registers,
|
|
||||||
.register_clocks = at91cap9_register_clocks,
|
|
||||||
.init = at91cap9_initialize,
|
|
||||||
};
|
|
||||||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -0,0 +1,373 @@
|
||||||
|
/*
|
||||||
|
* Chip-specific setup code for the AT91SAM9x5 family
|
||||||
|
*
|
||||||
|
* Copyright (C) 2010-2012 Atmel Corporation.
|
||||||
|
*
|
||||||
|
* Licensed under GPLv2 or later.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/module.h>
|
||||||
|
#include <linux/dma-mapping.h>
|
||||||
|
|
||||||
|
#include <asm/irq.h>
|
||||||
|
#include <asm/mach/arch.h>
|
||||||
|
#include <asm/mach/map.h>
|
||||||
|
#include <mach/at91sam9x5.h>
|
||||||
|
#include <mach/at91_pmc.h>
|
||||||
|
#include <mach/cpu.h>
|
||||||
|
#include <mach/board.h>
|
||||||
|
|
||||||
|
#include "soc.h"
|
||||||
|
#include "generic.h"
|
||||||
|
#include "clock.h"
|
||||||
|
#include "sam9_smc.h"
|
||||||
|
|
||||||
|
/* --------------------------------------------------------------------
|
||||||
|
* Clocks
|
||||||
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The peripheral clocks.
|
||||||
|
*/
|
||||||
|
static struct clk pioAB_clk = {
|
||||||
|
.name = "pioAB_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_PIOAB,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk pioCD_clk = {
|
||||||
|
.name = "pioCD_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_PIOCD,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk smd_clk = {
|
||||||
|
.name = "smd_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_SMD,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk usart0_clk = {
|
||||||
|
.name = "usart0_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_USART0,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk usart1_clk = {
|
||||||
|
.name = "usart1_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_USART1,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk usart2_clk = {
|
||||||
|
.name = "usart2_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_USART2,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
/* USART3 clock - Only for sam9g25/sam9x25 */
|
||||||
|
static struct clk usart3_clk = {
|
||||||
|
.name = "usart3_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_USART3,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk twi0_clk = {
|
||||||
|
.name = "twi0_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_TWI0,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk twi1_clk = {
|
||||||
|
.name = "twi1_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_TWI1,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk twi2_clk = {
|
||||||
|
.name = "twi2_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_TWI2,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk mmc0_clk = {
|
||||||
|
.name = "mci0_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_MCI0,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk spi0_clk = {
|
||||||
|
.name = "spi0_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_SPI0,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk spi1_clk = {
|
||||||
|
.name = "spi1_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_SPI1,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk uart0_clk = {
|
||||||
|
.name = "uart0_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_UART0,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk uart1_clk = {
|
||||||
|
.name = "uart1_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_UART1,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk tcb0_clk = {
|
||||||
|
.name = "tcb0_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_TCB,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk pwm_clk = {
|
||||||
|
.name = "pwm_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_PWM,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk adc_clk = {
|
||||||
|
.name = "adc_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_ADC,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk dma0_clk = {
|
||||||
|
.name = "dma0_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_DMA0,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk dma1_clk = {
|
||||||
|
.name = "dma1_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_DMA1,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk uhphs_clk = {
|
||||||
|
.name = "uhphs_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_UHPHS,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk udphs_clk = {
|
||||||
|
.name = "udphs_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_UDPHS,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
/* emac0 clock - Only for sam9g25/sam9x25/sam9g35/sam9x35 */
|
||||||
|
static struct clk macb0_clk = {
|
||||||
|
.name = "pclk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_EMAC0,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
/* lcd clock - Only for sam9g15/sam9g35/sam9x35 */
|
||||||
|
static struct clk lcdc_clk = {
|
||||||
|
.name = "lcdc_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_LCDC,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
/* isi clock - Only for sam9g25 */
|
||||||
|
static struct clk isi_clk = {
|
||||||
|
.name = "isi_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_ISI,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk mmc1_clk = {
|
||||||
|
.name = "mci1_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_MCI1,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
/* emac1 clock - Only for sam9x25 */
|
||||||
|
static struct clk macb1_clk = {
|
||||||
|
.name = "pclk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_EMAC1,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
static struct clk ssc_clk = {
|
||||||
|
.name = "ssc_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_SSC,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
/* can0 clock - Only for sam9x35 */
|
||||||
|
static struct clk can0_clk = {
|
||||||
|
.name = "can0_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_CAN0,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
/* can1 clock - Only for sam9x35 */
|
||||||
|
static struct clk can1_clk = {
|
||||||
|
.name = "can1_clk",
|
||||||
|
.pmc_mask = 1 << AT91SAM9X5_ID_CAN1,
|
||||||
|
.type = CLK_TYPE_PERIPHERAL,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct clk *periph_clocks[] __initdata = {
|
||||||
|
&pioAB_clk,
|
||||||
|
&pioCD_clk,
|
||||||
|
&smd_clk,
|
||||||
|
&usart0_clk,
|
||||||
|
&usart1_clk,
|
||||||
|
&usart2_clk,
|
||||||
|
&twi0_clk,
|
||||||
|
&twi1_clk,
|
||||||
|
&twi2_clk,
|
||||||
|
&mmc0_clk,
|
||||||
|
&spi0_clk,
|
||||||
|
&spi1_clk,
|
||||||
|
&uart0_clk,
|
||||||
|
&uart1_clk,
|
||||||
|
&tcb0_clk,
|
||||||
|
&pwm_clk,
|
||||||
|
&adc_clk,
|
||||||
|
&dma0_clk,
|
||||||
|
&dma1_clk,
|
||||||
|
&uhphs_clk,
|
||||||
|
&udphs_clk,
|
||||||
|
&mmc1_clk,
|
||||||
|
&ssc_clk,
|
||||||
|
// irq0
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct clk_lookup periph_clocks_lookups[] = {
|
||||||
|
/* lookup table for DT entries */
|
||||||
|
CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
|
||||||
|
CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
|
||||||
|
CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
|
||||||
|
CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
|
||||||
|
CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
|
||||||
|
CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb0_clk),
|
||||||
|
CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
|
||||||
|
CLKDEV_CON_ID("pioA", &pioAB_clk),
|
||||||
|
CLKDEV_CON_ID("pioB", &pioAB_clk),
|
||||||
|
CLKDEV_CON_ID("pioC", &pioCD_clk),
|
||||||
|
CLKDEV_CON_ID("pioD", &pioCD_clk),
|
||||||
|
/* additional fake clock for macb_hclk */
|
||||||
|
CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk),
|
||||||
|
CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk),
|
||||||
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The two programmable clocks.
|
||||||
|
* You must configure pin multiplexing to bring these signals out.
|
||||||
|
*/
|
||||||
|
static struct clk pck0 = {
|
||||||
|
.name = "pck0",
|
||||||
|
.pmc_mask = AT91_PMC_PCK0,
|
||||||
|
.type = CLK_TYPE_PROGRAMMABLE,
|
||||||
|
.id = 0,
|
||||||
|
};
|
||||||
|
static struct clk pck1 = {
|
||||||
|
.name = "pck1",
|
||||||
|
.pmc_mask = AT91_PMC_PCK1,
|
||||||
|
.type = CLK_TYPE_PROGRAMMABLE,
|
||||||
|
.id = 1,
|
||||||
|
};
|
||||||
|
|
||||||
|
static void __init at91sam9x5_register_clocks(void)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
|
||||||
|
clk_register(periph_clocks[i]);
|
||||||
|
|
||||||
|
clkdev_add_table(periph_clocks_lookups,
|
||||||
|
ARRAY_SIZE(periph_clocks_lookups));
|
||||||
|
|
||||||
|
if (cpu_is_at91sam9g25()
|
||||||
|
|| cpu_is_at91sam9x25())
|
||||||
|
clk_register(&usart3_clk);
|
||||||
|
|
||||||
|
if (cpu_is_at91sam9g25()
|
||||||
|
|| cpu_is_at91sam9x25()
|
||||||
|
|| cpu_is_at91sam9g35()
|
||||||
|
|| cpu_is_at91sam9x35())
|
||||||
|
clk_register(&macb0_clk);
|
||||||
|
|
||||||
|
if (cpu_is_at91sam9g15()
|
||||||
|
|| cpu_is_at91sam9g35()
|
||||||
|
|| cpu_is_at91sam9x35())
|
||||||
|
clk_register(&lcdc_clk);
|
||||||
|
|
||||||
|
if (cpu_is_at91sam9g25())
|
||||||
|
clk_register(&isi_clk);
|
||||||
|
|
||||||
|
if (cpu_is_at91sam9x25())
|
||||||
|
clk_register(&macb1_clk);
|
||||||
|
|
||||||
|
if (cpu_is_at91sam9x25()
|
||||||
|
|| cpu_is_at91sam9x35()) {
|
||||||
|
clk_register(&can0_clk);
|
||||||
|
clk_register(&can1_clk);
|
||||||
|
}
|
||||||
|
|
||||||
|
clk_register(&pck0);
|
||||||
|
clk_register(&pck1);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* --------------------------------------------------------------------
|
||||||
|
* AT91SAM9x5 processor initialization
|
||||||
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
|
static void __init at91sam9x5_map_io(void)
|
||||||
|
{
|
||||||
|
at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void __init at91sam9x5_ioremap_registers(void)
|
||||||
|
{
|
||||||
|
if (of_at91sam926x_pit_init() < 0)
|
||||||
|
panic("Impossible to find PIT\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
void __init at91sam9x5_initialize(void)
|
||||||
|
{
|
||||||
|
arm_pm_restart = at91sam9g45_restart;
|
||||||
|
at91_extern_irq = (1 << AT91SAM9X5_ID_IRQ0);
|
||||||
|
|
||||||
|
/* Register GPIO subsystem (using DT) */
|
||||||
|
at91_gpio_init(NULL, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* --------------------------------------------------------------------
|
||||||
|
* AT91SAM9x5 devices (temporary before modification of code)
|
||||||
|
* -------------------------------------------------------------------- */
|
||||||
|
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
|
||||||
|
void __init at91_set_serial_console(unsigned portnr) {}
|
||||||
|
struct platform_device *atmel_default_console_device = NULL;
|
||||||
|
|
||||||
|
void __init at91_add_device_nand(struct atmel_nand_data *data) {}
|
||||||
|
|
||||||
|
/* --------------------------------------------------------------------
|
||||||
|
* Interrupt initialization
|
||||||
|
* -------------------------------------------------------------------- */
|
||||||
|
/*
|
||||||
|
* The default interrupt priority levels (0 = lowest, 7 = highest).
|
||||||
|
*/
|
||||||
|
static unsigned int at91sam9x5_default_irq_priority[NR_AIC_IRQS] __initdata = {
|
||||||
|
7, /* Advanced Interrupt Controller (FIQ) */
|
||||||
|
7, /* System Peripherals */
|
||||||
|
1, /* Parallel IO Controller A and B */
|
||||||
|
1, /* Parallel IO Controller C and D */
|
||||||
|
4, /* Soft Modem */
|
||||||
|
5, /* USART 0 */
|
||||||
|
5, /* USART 1 */
|
||||||
|
5, /* USART 2 */
|
||||||
|
5, /* USART 3 */
|
||||||
|
6, /* Two-Wire Interface 0 */
|
||||||
|
6, /* Two-Wire Interface 1 */
|
||||||
|
6, /* Two-Wire Interface 2 */
|
||||||
|
0, /* Multimedia Card Interface 0 */
|
||||||
|
5, /* Serial Peripheral Interface 0 */
|
||||||
|
5, /* Serial Peripheral Interface 1 */
|
||||||
|
5, /* UART 0 */
|
||||||
|
5, /* UART 1 */
|
||||||
|
0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */
|
||||||
|
0, /* Pulse Width Modulation Controller */
|
||||||
|
0, /* ADC Controller */
|
||||||
|
0, /* DMA Controller 0 */
|
||||||
|
0, /* DMA Controller 1 */
|
||||||
|
2, /* USB Host High Speed port */
|
||||||
|
2, /* USB Device High speed port */
|
||||||
|
3, /* Ethernet MAC 0 */
|
||||||
|
3, /* LDC Controller or Image Sensor Interface */
|
||||||
|
0, /* Multimedia Card Interface 1 */
|
||||||
|
3, /* Ethernet MAC 1 */
|
||||||
|
4, /* Synchronous Serial Interface */
|
||||||
|
4, /* CAN Controller 0 */
|
||||||
|
4, /* CAN Controller 1 */
|
||||||
|
0, /* Advanced Interrupt Controller (IRQ0) */
|
||||||
|
};
|
||||||
|
|
||||||
|
struct at91_init_soc __initdata at91sam9x5_soc = {
|
||||||
|
.map_io = at91sam9x5_map_io,
|
||||||
|
.default_irq_priority = at91sam9x5_default_irq_priority,
|
||||||
|
.ioremap_registers = at91sam9x5_ioremap_registers,
|
||||||
|
.register_clocks = at91sam9x5_register_clocks,
|
||||||
|
.init = at91sam9x5_initialize,
|
||||||
|
};
|
||||||
|
|
@ -1,396 +0,0 @@
|
||||||
/*
|
|
||||||
* linux/arch/arm/mach-at91/board-cap9adk.c
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
|
|
||||||
* Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
|
|
||||||
* Copyright (C) 2005 SAN People
|
|
||||||
* Copyright (C) 2007 Atmel Corporation.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; either version 2 of the License, or
|
|
||||||
* (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License
|
|
||||||
* along with this program; if not, write to the Free Software
|
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <linux/types.h>
|
|
||||||
#include <linux/gpio.h>
|
|
||||||
#include <linux/init.h>
|
|
||||||
#include <linux/mm.h>
|
|
||||||
#include <linux/module.h>
|
|
||||||
#include <linux/platform_device.h>
|
|
||||||
#include <linux/spi/spi.h>
|
|
||||||
#include <linux/spi/ads7846.h>
|
|
||||||
#include <linux/fb.h>
|
|
||||||
#include <linux/mtd/physmap.h>
|
|
||||||
|
|
||||||
#include <video/atmel_lcdc.h>
|
|
||||||
|
|
||||||
#include <mach/hardware.h>
|
|
||||||
#include <asm/setup.h>
|
|
||||||
#include <asm/mach-types.h>
|
|
||||||
|
|
||||||
#include <asm/mach/arch.h>
|
|
||||||
#include <asm/mach/map.h>
|
|
||||||
|
|
||||||
#include <mach/board.h>
|
|
||||||
#include <mach/at91cap9_matrix.h>
|
|
||||||
#include <mach/at91sam9_smc.h>
|
|
||||||
#include <mach/system_rev.h>
|
|
||||||
|
|
||||||
#include "sam9_smc.h"
|
|
||||||
#include "generic.h"
|
|
||||||
|
|
||||||
|
|
||||||
static void __init cap9adk_init_early(void)
|
|
||||||
{
|
|
||||||
/* Initialize processor: 12 MHz crystal */
|
|
||||||
at91_initialize(12000000);
|
|
||||||
|
|
||||||
/* Setup the LEDs: USER1 and USER2 LED for cpu/timer... */
|
|
||||||
at91_init_leds(AT91_PIN_PA10, AT91_PIN_PA11);
|
|
||||||
/* ... POWER LED always on */
|
|
||||||
at91_set_gpio_output(AT91_PIN_PC29, 1);
|
|
||||||
|
|
||||||
/* Setup the serial ports and console */
|
|
||||||
at91_register_uart(0, 0, 0); /* DBGU = ttyS0 */
|
|
||||||
at91_set_serial_console(0);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* USB Host port
|
|
||||||
*/
|
|
||||||
static struct at91_usbh_data __initdata cap9adk_usbh_data = {
|
|
||||||
.ports = 2,
|
|
||||||
.vbus_pin = {-EINVAL, -EINVAL},
|
|
||||||
.overcurrent_pin= {-EINVAL, -EINVAL},
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* USB HS Device port
|
|
||||||
*/
|
|
||||||
static struct usba_platform_data __initdata cap9adk_usba_udc_data = {
|
|
||||||
.vbus_pin = AT91_PIN_PB31,
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* ADS7846 Touchscreen
|
|
||||||
*/
|
|
||||||
#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
|
|
||||||
static int ads7843_pendown_state(void)
|
|
||||||
{
|
|
||||||
return !at91_get_gpio_value(AT91_PIN_PC4); /* Touchscreen PENIRQ */
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct ads7846_platform_data ads_info = {
|
|
||||||
.model = 7843,
|
|
||||||
.x_min = 150,
|
|
||||||
.x_max = 3830,
|
|
||||||
.y_min = 190,
|
|
||||||
.y_max = 3830,
|
|
||||||
.vref_delay_usecs = 100,
|
|
||||||
.x_plate_ohms = 450,
|
|
||||||
.y_plate_ohms = 250,
|
|
||||||
.pressure_max = 15000,
|
|
||||||
.debounce_max = 1,
|
|
||||||
.debounce_rep = 0,
|
|
||||||
.debounce_tol = (~0),
|
|
||||||
.get_pendown_state = ads7843_pendown_state,
|
|
||||||
};
|
|
||||||
|
|
||||||
static void __init cap9adk_add_device_ts(void)
|
|
||||||
{
|
|
||||||
at91_set_gpio_input(AT91_PIN_PC4, 1); /* Touchscreen PENIRQ */
|
|
||||||
at91_set_gpio_input(AT91_PIN_PC5, 1); /* Touchscreen BUSY */
|
|
||||||
}
|
|
||||||
#else
|
|
||||||
static void __init cap9adk_add_device_ts(void) {}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SPI devices.
|
|
||||||
*/
|
|
||||||
static struct spi_board_info cap9adk_spi_devices[] = {
|
|
||||||
#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
|
|
||||||
{ /* DataFlash card */
|
|
||||||
.modalias = "mtd_dataflash",
|
|
||||||
.chip_select = 0,
|
|
||||||
.max_speed_hz = 15 * 1000 * 1000,
|
|
||||||
.bus_num = 0,
|
|
||||||
},
|
|
||||||
#endif
|
|
||||||
#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
|
|
||||||
{
|
|
||||||
.modalias = "ads7846",
|
|
||||||
.chip_select = 3, /* can be 2 or 3, depending on J2 jumper */
|
|
||||||
.max_speed_hz = 125000 * 26, /* (max sample rate @ 3V) * (cmd + data + overhead) */
|
|
||||||
.bus_num = 0,
|
|
||||||
.platform_data = &ads_info,
|
|
||||||
.irq = AT91_PIN_PC4,
|
|
||||||
},
|
|
||||||
#endif
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* MCI (SD/MMC)
|
|
||||||
*/
|
|
||||||
static struct at91_mmc_data __initdata cap9adk_mmc_data = {
|
|
||||||
.wire4 = 1,
|
|
||||||
.det_pin = -EINVAL,
|
|
||||||
.wp_pin = -EINVAL,
|
|
||||||
.vcc_pin = -EINVAL,
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* MACB Ethernet device
|
|
||||||
*/
|
|
||||||
static struct macb_platform_data __initdata cap9adk_macb_data = {
|
|
||||||
.phy_irq_pin = -EINVAL,
|
|
||||||
.is_rmii = 1,
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* NAND flash
|
|
||||||
*/
|
|
||||||
static struct mtd_partition __initdata cap9adk_nand_partitions[] = {
|
|
||||||
{
|
|
||||||
.name = "NAND partition",
|
|
||||||
.offset = 0,
|
|
||||||
.size = MTDPART_SIZ_FULL,
|
|
||||||
},
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct atmel_nand_data __initdata cap9adk_nand_data = {
|
|
||||||
.ale = 21,
|
|
||||||
.cle = 22,
|
|
||||||
.det_pin = -EINVAL,
|
|
||||||
.rdy_pin = -EINVAL,
|
|
||||||
.enable_pin = AT91_PIN_PD15,
|
|
||||||
.parts = cap9adk_nand_partitions,
|
|
||||||
.num_parts = ARRAY_SIZE(cap9adk_nand_partitions),
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct sam9_smc_config __initdata cap9adk_nand_smc_config = {
|
|
||||||
.ncs_read_setup = 1,
|
|
||||||
.nrd_setup = 2,
|
|
||||||
.ncs_write_setup = 1,
|
|
||||||
.nwe_setup = 2,
|
|
||||||
|
|
||||||
.ncs_read_pulse = 6,
|
|
||||||
.nrd_pulse = 4,
|
|
||||||
.ncs_write_pulse = 6,
|
|
||||||
.nwe_pulse = 4,
|
|
||||||
|
|
||||||
.read_cycle = 8,
|
|
||||||
.write_cycle = 8,
|
|
||||||
|
|
||||||
.mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
|
|
||||||
.tdf_cycles = 1,
|
|
||||||
};
|
|
||||||
|
|
||||||
static void __init cap9adk_add_device_nand(void)
|
|
||||||
{
|
|
||||||
unsigned long csa;
|
|
||||||
|
|
||||||
csa = at91_sys_read(AT91_MATRIX_EBICSA);
|
|
||||||
at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
|
|
||||||
|
|
||||||
cap9adk_nand_data.bus_width_16 = board_have_nand_16bit();
|
|
||||||
/* setup bus-width (8 or 16) */
|
|
||||||
if (cap9adk_nand_data.bus_width_16)
|
|
||||||
cap9adk_nand_smc_config.mode |= AT91_SMC_DBW_16;
|
|
||||||
else
|
|
||||||
cap9adk_nand_smc_config.mode |= AT91_SMC_DBW_8;
|
|
||||||
|
|
||||||
/* configure chip-select 3 (NAND) */
|
|
||||||
sam9_smc_configure(0, 3, &cap9adk_nand_smc_config);
|
|
||||||
|
|
||||||
at91_add_device_nand(&cap9adk_nand_data);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* NOR flash
|
|
||||||
*/
|
|
||||||
static struct mtd_partition cap9adk_nor_partitions[] = {
|
|
||||||
{
|
|
||||||
.name = "NOR partition",
|
|
||||||
.offset = 0,
|
|
||||||
.size = MTDPART_SIZ_FULL,
|
|
||||||
},
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct physmap_flash_data cap9adk_nor_data = {
|
|
||||||
.width = 2,
|
|
||||||
.parts = cap9adk_nor_partitions,
|
|
||||||
.nr_parts = ARRAY_SIZE(cap9adk_nor_partitions),
|
|
||||||
};
|
|
||||||
|
|
||||||
#define NOR_BASE AT91_CHIPSELECT_0
|
|
||||||
#define NOR_SIZE SZ_8M
|
|
||||||
|
|
||||||
static struct resource nor_flash_resources[] = {
|
|
||||||
{
|
|
||||||
.start = NOR_BASE,
|
|
||||||
.end = NOR_BASE + NOR_SIZE - 1,
|
|
||||||
.flags = IORESOURCE_MEM,
|
|
||||||
}
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct platform_device cap9adk_nor_flash = {
|
|
||||||
.name = "physmap-flash",
|
|
||||||
.id = 0,
|
|
||||||
.dev = {
|
|
||||||
.platform_data = &cap9adk_nor_data,
|
|
||||||
},
|
|
||||||
.resource = nor_flash_resources,
|
|
||||||
.num_resources = ARRAY_SIZE(nor_flash_resources),
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct sam9_smc_config __initdata cap9adk_nor_smc_config = {
|
|
||||||
.ncs_read_setup = 2,
|
|
||||||
.nrd_setup = 4,
|
|
||||||
.ncs_write_setup = 2,
|
|
||||||
.nwe_setup = 4,
|
|
||||||
|
|
||||||
.ncs_read_pulse = 10,
|
|
||||||
.nrd_pulse = 8,
|
|
||||||
.ncs_write_pulse = 10,
|
|
||||||
.nwe_pulse = 8,
|
|
||||||
|
|
||||||
.read_cycle = 16,
|
|
||||||
.write_cycle = 16,
|
|
||||||
|
|
||||||
.mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16,
|
|
||||||
.tdf_cycles = 1,
|
|
||||||
};
|
|
||||||
|
|
||||||
static __init void cap9adk_add_device_nor(void)
|
|
||||||
{
|
|
||||||
unsigned long csa;
|
|
||||||
|
|
||||||
csa = at91_sys_read(AT91_MATRIX_EBICSA);
|
|
||||||
at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
|
|
||||||
|
|
||||||
/* configure chip-select 0 (NOR) */
|
|
||||||
sam9_smc_configure(0, 0, &cap9adk_nor_smc_config);
|
|
||||||
|
|
||||||
platform_device_register(&cap9adk_nor_flash);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* LCD Controller
|
|
||||||
*/
|
|
||||||
#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
|
|
||||||
static struct fb_videomode at91_tft_vga_modes[] = {
|
|
||||||
{
|
|
||||||
.name = "TX09D50VM1CCA @ 60",
|
|
||||||
.refresh = 60,
|
|
||||||
.xres = 240, .yres = 320,
|
|
||||||
.pixclock = KHZ2PICOS(4965),
|
|
||||||
|
|
||||||
.left_margin = 1, .right_margin = 33,
|
|
||||||
.upper_margin = 1, .lower_margin = 0,
|
|
||||||
.hsync_len = 5, .vsync_len = 1,
|
|
||||||
|
|
||||||
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
|
|
||||||
.vmode = FB_VMODE_NONINTERLACED,
|
|
||||||
},
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct fb_monspecs at91fb_default_monspecs = {
|
|
||||||
.manufacturer = "HIT",
|
|
||||||
.monitor = "TX09D70VM1CCA",
|
|
||||||
|
|
||||||
.modedb = at91_tft_vga_modes,
|
|
||||||
.modedb_len = ARRAY_SIZE(at91_tft_vga_modes),
|
|
||||||
.hfmin = 15000,
|
|
||||||
.hfmax = 64000,
|
|
||||||
.vfmin = 50,
|
|
||||||
.vfmax = 150,
|
|
||||||
};
|
|
||||||
|
|
||||||
#define AT91CAP9_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
|
|
||||||
| ATMEL_LCDC_DISTYPE_TFT \
|
|
||||||
| ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
|
|
||||||
|
|
||||||
static void at91_lcdc_power_control(int on)
|
|
||||||
{
|
|
||||||
if (on)
|
|
||||||
at91_set_gpio_value(AT91_PIN_PC0, 0); /* power up */
|
|
||||||
else
|
|
||||||
at91_set_gpio_value(AT91_PIN_PC0, 1); /* power down */
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Driver datas */
|
|
||||||
static struct atmel_lcdfb_info __initdata cap9adk_lcdc_data = {
|
|
||||||
.default_bpp = 16,
|
|
||||||
.default_dmacon = ATMEL_LCDC_DMAEN,
|
|
||||||
.default_lcdcon2 = AT91CAP9_DEFAULT_LCDCON2,
|
|
||||||
.default_monspecs = &at91fb_default_monspecs,
|
|
||||||
.atmel_lcdfb_power_control = at91_lcdc_power_control,
|
|
||||||
.guard_time = 1,
|
|
||||||
};
|
|
||||||
|
|
||||||
#else
|
|
||||||
static struct atmel_lcdfb_info __initdata cap9adk_lcdc_data;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* AC97
|
|
||||||
*/
|
|
||||||
static struct ac97c_platform_data cap9adk_ac97_data = {
|
|
||||||
.reset_pin = -EINVAL,
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
static void __init cap9adk_board_init(void)
|
|
||||||
{
|
|
||||||
/* Serial */
|
|
||||||
at91_add_device_serial();
|
|
||||||
/* USB Host */
|
|
||||||
at91_add_device_usbh(&cap9adk_usbh_data);
|
|
||||||
/* USB HS */
|
|
||||||
at91_add_device_usba(&cap9adk_usba_udc_data);
|
|
||||||
/* SPI */
|
|
||||||
at91_add_device_spi(cap9adk_spi_devices, ARRAY_SIZE(cap9adk_spi_devices));
|
|
||||||
/* Touchscreen */
|
|
||||||
cap9adk_add_device_ts();
|
|
||||||
/* MMC */
|
|
||||||
at91_add_device_mmc(1, &cap9adk_mmc_data);
|
|
||||||
/* Ethernet */
|
|
||||||
at91_add_device_eth(&cap9adk_macb_data);
|
|
||||||
/* NAND */
|
|
||||||
cap9adk_add_device_nand();
|
|
||||||
/* NOR Flash */
|
|
||||||
cap9adk_add_device_nor();
|
|
||||||
/* I2C */
|
|
||||||
at91_add_device_i2c(NULL, 0);
|
|
||||||
/* LCD Controller */
|
|
||||||
at91_add_device_lcdc(&cap9adk_lcdc_data);
|
|
||||||
/* AC97 */
|
|
||||||
at91_add_device_ac97(&cap9adk_ac97_data);
|
|
||||||
}
|
|
||||||
|
|
||||||
MACHINE_START(AT91CAP9ADK, "Atmel AT91CAP9A-DK")
|
|
||||||
/* Maintainer: Stelian Pop <stelian.pop@leadtechdesign.com> */
|
|
||||||
.timer = &at91sam926x_timer,
|
|
||||||
.map_io = at91_map_io,
|
|
||||||
.init_early = cap9adk_init_early,
|
|
||||||
.init_irq = at91_init_irq_default,
|
|
||||||
.init_machine = cap9adk_board_init,
|
|
||||||
MACHINE_END
|
|
||||||
|
|
@ -109,6 +109,7 @@ static void __init at91_dt_device_init(void)
|
||||||
|
|
||||||
static const char *at91_dt_board_compat[] __initdata = {
|
static const char *at91_dt_board_compat[] __initdata = {
|
||||||
"atmel,at91sam9m10g45ek",
|
"atmel,at91sam9m10g45ek",
|
||||||
|
"atmel,at91sam9x5ek",
|
||||||
"calao,usb-a9g20",
|
"calao,usb-a9g20",
|
||||||
NULL
|
NULL
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -47,26 +47,38 @@
|
||||||
/*
|
/*
|
||||||
* Chips have some kind of clocks : group them by functionality
|
* Chips have some kind of clocks : group them by functionality
|
||||||
*/
|
*/
|
||||||
#define cpu_has_utmi() ( cpu_is_at91cap9() \
|
#define cpu_has_utmi() ( cpu_is_at91sam9rl() \
|
||||||
|| cpu_is_at91sam9rl() \
|
|| cpu_is_at91sam9g45() \
|
||||||
|| cpu_is_at91sam9g45())
|
|| cpu_is_at91sam9x5())
|
||||||
|
|
||||||
#define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \
|
#define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \
|
||||||
|| cpu_is_at91sam9g45())
|
|| cpu_is_at91sam9g45() \
|
||||||
|
|| cpu_is_at91sam9x5())
|
||||||
|
|
||||||
#define cpu_has_300M_plla() (cpu_is_at91sam9g10())
|
#define cpu_has_300M_plla() (cpu_is_at91sam9g10())
|
||||||
|
|
||||||
#define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
|
#define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
|
||||||
|| cpu_is_at91sam9g45()))
|
|| cpu_is_at91sam9g45() \
|
||||||
|
|| cpu_is_at91sam9x5()))
|
||||||
|
|
||||||
#define cpu_has_upll() (cpu_is_at91sam9g45())
|
#define cpu_has_upll() (cpu_is_at91sam9g45() \
|
||||||
|
|| cpu_is_at91sam9x5())
|
||||||
|
|
||||||
/* USB host HS & FS */
|
/* USB host HS & FS */
|
||||||
#define cpu_has_uhp() (!cpu_is_at91sam9rl())
|
#define cpu_has_uhp() (!cpu_is_at91sam9rl())
|
||||||
|
|
||||||
/* USB device FS only */
|
/* USB device FS only */
|
||||||
#define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \
|
#define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \
|
||||||
|| cpu_is_at91sam9g45()))
|
|| cpu_is_at91sam9g45() \
|
||||||
|
|| cpu_is_at91sam9x5()))
|
||||||
|
|
||||||
|
#define cpu_has_plladiv2() (cpu_is_at91sam9g45() \
|
||||||
|
|| cpu_is_at91sam9x5())
|
||||||
|
|
||||||
|
#define cpu_has_mdiv3() (cpu_is_at91sam9g45() \
|
||||||
|
|| cpu_is_at91sam9x5())
|
||||||
|
|
||||||
|
#define cpu_has_alt_prescaler() (cpu_is_at91sam9x5())
|
||||||
|
|
||||||
static LIST_HEAD(clocks);
|
static LIST_HEAD(clocks);
|
||||||
static DEFINE_SPINLOCK(clk_lock);
|
static DEFINE_SPINLOCK(clk_lock);
|
||||||
|
|
@ -139,13 +151,6 @@ static void pmc_uckr_mode(struct clk *clk, int is_on)
|
||||||
{
|
{
|
||||||
unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
|
unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
|
||||||
|
|
||||||
if (cpu_is_at91sam9g45()) {
|
|
||||||
if (is_on)
|
|
||||||
uckr |= AT91_PMC_BIASEN;
|
|
||||||
else
|
|
||||||
uckr &= ~AT91_PMC_BIASEN;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (is_on) {
|
if (is_on) {
|
||||||
is_on = AT91_PMC_LOCKU;
|
is_on = AT91_PMC_LOCKU;
|
||||||
at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
|
at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
|
||||||
|
|
@ -210,11 +215,24 @@ static struct clk __init *at91_css_to_clk(unsigned long css)
|
||||||
return &utmi_clk;
|
return &utmi_clk;
|
||||||
else if (cpu_has_pllb())
|
else if (cpu_has_pllb())
|
||||||
return &pllb;
|
return &pllb;
|
||||||
|
break;
|
||||||
|
/* alternate PMC: can use master clock */
|
||||||
|
case AT91_PMC_CSS_MASTER:
|
||||||
|
return &mck;
|
||||||
}
|
}
|
||||||
|
|
||||||
return NULL;
|
return NULL;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static int pmc_prescaler_divider(u32 reg)
|
||||||
|
{
|
||||||
|
if (cpu_has_alt_prescaler()) {
|
||||||
|
return 1 << ((reg & AT91_PMC_ALT_PRES) >> PMC_ALT_PRES_OFFSET);
|
||||||
|
} else {
|
||||||
|
return 1 << ((reg & AT91_PMC_PRES) >> PMC_PRES_OFFSET);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
static void __clk_enable(struct clk *clk)
|
static void __clk_enable(struct clk *clk)
|
||||||
{
|
{
|
||||||
if (clk->parent)
|
if (clk->parent)
|
||||||
|
|
@ -316,12 +334,22 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
|
||||||
{
|
{
|
||||||
unsigned long flags;
|
unsigned long flags;
|
||||||
unsigned prescale;
|
unsigned prescale;
|
||||||
|
unsigned long prescale_offset, css_mask;
|
||||||
unsigned long actual;
|
unsigned long actual;
|
||||||
|
|
||||||
if (!clk_is_programmable(clk))
|
if (!clk_is_programmable(clk))
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
if (clk->users)
|
if (clk->users)
|
||||||
return -EBUSY;
|
return -EBUSY;
|
||||||
|
|
||||||
|
if (cpu_has_alt_prescaler()) {
|
||||||
|
prescale_offset = PMC_ALT_PRES_OFFSET;
|
||||||
|
css_mask = AT91_PMC_ALT_PCKR_CSS;
|
||||||
|
} else {
|
||||||
|
prescale_offset = PMC_PRES_OFFSET;
|
||||||
|
css_mask = AT91_PMC_CSS;
|
||||||
|
}
|
||||||
|
|
||||||
spin_lock_irqsave(&clk_lock, flags);
|
spin_lock_irqsave(&clk_lock, flags);
|
||||||
|
|
||||||
actual = clk->parent->rate_hz;
|
actual = clk->parent->rate_hz;
|
||||||
|
|
@ -330,8 +358,8 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
|
||||||
u32 pckr;
|
u32 pckr;
|
||||||
|
|
||||||
pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
|
pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
|
||||||
pckr &= AT91_PMC_CSS; /* clock selection */
|
pckr &= css_mask; /* keep clock selection */
|
||||||
pckr |= prescale << 2;
|
pckr |= prescale << prescale_offset;
|
||||||
at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
|
at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
|
||||||
clk->rate_hz = actual;
|
clk->rate_hz = actual;
|
||||||
break;
|
break;
|
||||||
|
|
@ -378,11 +406,17 @@ static void __init init_programmable_clock(struct clk *clk)
|
||||||
{
|
{
|
||||||
struct clk *parent;
|
struct clk *parent;
|
||||||
u32 pckr;
|
u32 pckr;
|
||||||
|
unsigned int css_mask;
|
||||||
|
|
||||||
|
if (cpu_has_alt_prescaler())
|
||||||
|
css_mask = AT91_PMC_ALT_PCKR_CSS;
|
||||||
|
else
|
||||||
|
css_mask = AT91_PMC_CSS;
|
||||||
|
|
||||||
pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
|
pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
|
||||||
parent = at91_css_to_clk(pckr & AT91_PMC_CSS);
|
parent = at91_css_to_clk(pckr & css_mask);
|
||||||
clk->parent = parent;
|
clk->parent = parent;
|
||||||
clk->rate_hz = parent->rate_hz / (1 << ((pckr & AT91_PMC_PRES) >> 2));
|
clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr);
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
|
#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
|
||||||
|
|
@ -602,8 +636,6 @@ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
|
||||||
cpu_is_at91sam9g10()) {
|
cpu_is_at91sam9g10()) {
|
||||||
uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
|
uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
|
||||||
udpck.pmc_mask = AT91SAM926x_PMC_UDP;
|
udpck.pmc_mask = AT91SAM926x_PMC_UDP;
|
||||||
} else if (cpu_is_at91cap9()) {
|
|
||||||
uhpck.pmc_mask = AT91CAP9_PMC_UHP;
|
|
||||||
}
|
}
|
||||||
at91_sys_write(AT91_CKGR_PLLBR, 0);
|
at91_sys_write(AT91_CKGR_PLLBR, 0);
|
||||||
|
|
||||||
|
|
@ -666,7 +698,7 @@ int __init at91_clock_init(unsigned long main_clock)
|
||||||
if (pll_overclock)
|
if (pll_overclock)
|
||||||
pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
|
pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
|
||||||
|
|
||||||
if (cpu_is_at91sam9g45()) {
|
if (cpu_has_plladiv2()) {
|
||||||
mckr = at91_sys_read(AT91_PMC_MCKR);
|
mckr = at91_sys_read(AT91_PMC_MCKR);
|
||||||
plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */
|
plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */
|
||||||
}
|
}
|
||||||
|
|
@ -688,6 +720,10 @@ int __init at91_clock_init(unsigned long main_clock)
|
||||||
* (obtain the USB High Speed 480 MHz when input is 12 MHz)
|
* (obtain the USB High Speed 480 MHz when input is 12 MHz)
|
||||||
*/
|
*/
|
||||||
utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
|
utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
|
||||||
|
|
||||||
|
/* UTMI bias and PLL are managed at the same time */
|
||||||
|
if (cpu_has_upll())
|
||||||
|
utmi_clk.pmc_mask |= AT91_PMC_BIASEN;
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
@ -706,7 +742,7 @@ int __init at91_clock_init(unsigned long main_clock)
|
||||||
mckr = at91_sys_read(AT91_PMC_MCKR);
|
mckr = at91_sys_read(AT91_PMC_MCKR);
|
||||||
mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
|
mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
|
||||||
freq = mck.parent->rate_hz;
|
freq = mck.parent->rate_hz;
|
||||||
freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */
|
freq /= pmc_prescaler_divider(mckr); /* prescale */
|
||||||
if (cpu_is_at91rm9200()) {
|
if (cpu_is_at91rm9200()) {
|
||||||
mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
|
mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
|
||||||
} else if (cpu_is_at91sam9g20()) {
|
} else if (cpu_is_at91sam9g20()) {
|
||||||
|
|
@ -714,13 +750,19 @@ int __init at91_clock_init(unsigned long main_clock)
|
||||||
freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
|
freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
|
||||||
if (mckr & AT91_PMC_PDIV)
|
if (mckr & AT91_PMC_PDIV)
|
||||||
freq /= 2; /* processor clock division */
|
freq /= 2; /* processor clock division */
|
||||||
} else if (cpu_is_at91sam9g45()) {
|
} else if (cpu_has_mdiv3()) {
|
||||||
mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
|
mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
|
||||||
freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
|
freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
|
||||||
} else {
|
} else {
|
||||||
mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
|
mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (cpu_has_alt_prescaler()) {
|
||||||
|
/* Programmable clocks can use MCK */
|
||||||
|
mck.type |= CLK_TYPE_PRIMARY;
|
||||||
|
mck.id = 4;
|
||||||
|
}
|
||||||
|
|
||||||
/* Register the PMC's standard clocks */
|
/* Register the PMC's standard clocks */
|
||||||
for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
|
for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
|
||||||
at91_clk_add(standard_pmc_clocks[i]);
|
at91_clk_add(standard_pmc_clocks[i]);
|
||||||
|
|
|
||||||
|
|
@ -45,7 +45,6 @@ extern void __init at91sam9261_set_console_clock(int id);
|
||||||
extern void __init at91sam9263_set_console_clock(int id);
|
extern void __init at91sam9263_set_console_clock(int id);
|
||||||
extern void __init at91sam9rl_set_console_clock(int id);
|
extern void __init at91sam9rl_set_console_clock(int id);
|
||||||
extern void __init at91sam9g45_set_console_clock(int id);
|
extern void __init at91sam9g45_set_console_clock(int id);
|
||||||
extern void __init at91cap9_set_console_clock(int id);
|
|
||||||
#ifdef CONFIG_AT91_PMC_UNIT
|
#ifdef CONFIG_AT91_PMC_UNIT
|
||||||
extern int __init at91_clock_init(unsigned long main_clock);
|
extern int __init at91_clock_init(unsigned long main_clock);
|
||||||
#else
|
#else
|
||||||
|
|
|
||||||
|
|
@ -23,10 +23,8 @@
|
||||||
#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
|
#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
|
||||||
#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
|
#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
|
||||||
#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
|
#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
|
||||||
#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [CAP9 revC & some SAM9 only] */
|
|
||||||
#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
|
#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
|
||||||
#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
|
#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
|
||||||
#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */
|
|
||||||
#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
|
#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
|
||||||
#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
|
#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
|
||||||
#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
|
#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
|
||||||
|
|
@ -40,16 +38,20 @@
|
||||||
#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
|
#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
|
||||||
#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
|
#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
|
||||||
|
|
||||||
#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [some SAM9, CAP9] */
|
#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [some SAM9] */
|
||||||
#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
|
#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
|
||||||
#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
|
#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
|
||||||
#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
|
#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
|
||||||
#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */
|
#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */
|
||||||
|
|
||||||
#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
|
#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
|
||||||
#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
|
#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
|
||||||
#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */
|
#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */
|
||||||
#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
|
#define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */
|
||||||
|
#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
|
||||||
|
#define AT91_PMC_KEY (0x37 << 16) /* MOR Writing Key */
|
||||||
|
#define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */
|
||||||
|
#define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */
|
||||||
|
|
||||||
#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
|
#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
|
||||||
#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
|
#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
|
||||||
|
|
@ -74,20 +76,30 @@
|
||||||
#define AT91_PMC_CSS_PLLA (2 << 0)
|
#define AT91_PMC_CSS_PLLA (2 << 0)
|
||||||
#define AT91_PMC_CSS_PLLB (3 << 0)
|
#define AT91_PMC_CSS_PLLB (3 << 0)
|
||||||
#define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */
|
#define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */
|
||||||
#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */
|
#define PMC_PRES_OFFSET 2
|
||||||
#define AT91_PMC_PRES_1 (0 << 2)
|
#define AT91_PMC_PRES (7 << PMC_PRES_OFFSET) /* Master Clock Prescaler */
|
||||||
#define AT91_PMC_PRES_2 (1 << 2)
|
#define AT91_PMC_PRES_1 (0 << PMC_PRES_OFFSET)
|
||||||
#define AT91_PMC_PRES_4 (2 << 2)
|
#define AT91_PMC_PRES_2 (1 << PMC_PRES_OFFSET)
|
||||||
#define AT91_PMC_PRES_8 (3 << 2)
|
#define AT91_PMC_PRES_4 (2 << PMC_PRES_OFFSET)
|
||||||
#define AT91_PMC_PRES_16 (4 << 2)
|
#define AT91_PMC_PRES_8 (3 << PMC_PRES_OFFSET)
|
||||||
#define AT91_PMC_PRES_32 (5 << 2)
|
#define AT91_PMC_PRES_16 (4 << PMC_PRES_OFFSET)
|
||||||
#define AT91_PMC_PRES_64 (6 << 2)
|
#define AT91_PMC_PRES_32 (5 << PMC_PRES_OFFSET)
|
||||||
|
#define AT91_PMC_PRES_64 (6 << PMC_PRES_OFFSET)
|
||||||
|
#define PMC_ALT_PRES_OFFSET 4
|
||||||
|
#define AT91_PMC_ALT_PRES (7 << PMC_ALT_PRES_OFFSET) /* Master Clock Prescaler [alternate location] */
|
||||||
|
#define AT91_PMC_ALT_PRES_1 (0 << PMC_ALT_PRES_OFFSET)
|
||||||
|
#define AT91_PMC_ALT_PRES_2 (1 << PMC_ALT_PRES_OFFSET)
|
||||||
|
#define AT91_PMC_ALT_PRES_4 (2 << PMC_ALT_PRES_OFFSET)
|
||||||
|
#define AT91_PMC_ALT_PRES_8 (3 << PMC_ALT_PRES_OFFSET)
|
||||||
|
#define AT91_PMC_ALT_PRES_16 (4 << PMC_ALT_PRES_OFFSET)
|
||||||
|
#define AT91_PMC_ALT_PRES_32 (5 << PMC_ALT_PRES_OFFSET)
|
||||||
|
#define AT91_PMC_ALT_PRES_64 (6 << PMC_ALT_PRES_OFFSET)
|
||||||
#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
|
#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
|
||||||
#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */
|
#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */
|
||||||
#define AT91RM9200_PMC_MDIV_2 (1 << 8)
|
#define AT91RM9200_PMC_MDIV_2 (1 << 8)
|
||||||
#define AT91RM9200_PMC_MDIV_3 (2 << 8)
|
#define AT91RM9200_PMC_MDIV_3 (2 << 8)
|
||||||
#define AT91RM9200_PMC_MDIV_4 (3 << 8)
|
#define AT91RM9200_PMC_MDIV_4 (3 << 8)
|
||||||
#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */
|
#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */
|
||||||
#define AT91SAM9_PMC_MDIV_2 (1 << 8)
|
#define AT91SAM9_PMC_MDIV_2 (1 << 8)
|
||||||
#define AT91SAM9_PMC_MDIV_4 (2 << 8)
|
#define AT91SAM9_PMC_MDIV_4 (2 << 8)
|
||||||
#define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */
|
#define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */
|
||||||
|
|
@ -105,7 +117,14 @@
|
||||||
#define AT91_PMC_USBS_UPLL (1 << 0)
|
#define AT91_PMC_USBS_UPLL (1 << 0)
|
||||||
#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */
|
#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */
|
||||||
|
|
||||||
|
#define AT91_PMC_SMD (AT91_PMC + 0x3c) /* Soft Modem Clock Register [some SAM9 only] */
|
||||||
|
#define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */
|
||||||
|
#define AT91_PMC_SMD_DIV (0x1f << 8) /* SMD input clock divider */
|
||||||
|
#define AT91_PMC_SMDDIV(n) (((n) << 8) & AT91_PMC_SMD_DIV)
|
||||||
|
|
||||||
#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */
|
#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */
|
||||||
|
#define AT91_PMC_ALT_PCKR_CSS (0x7 << 0) /* Programmable Clock Source Selection [alternate length] */
|
||||||
|
#define AT91_PMC_CSS_MASTER (4 << 0) /* [some SAM9 only] */
|
||||||
#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */
|
#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */
|
||||||
#define AT91_PMC_CSSMCK_CSS (0 << 8)
|
#define AT91_PMC_CSSMCK_CSS (0 << 8)
|
||||||
#define AT91_PMC_CSSMCK_MCK (1 << 8)
|
#define AT91_PMC_CSSMCK_MCK (1 << 8)
|
||||||
|
|
@ -117,17 +136,30 @@
|
||||||
#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
|
#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
|
||||||
#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
|
#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
|
||||||
#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
|
#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
|
||||||
#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9, AT91CAP9 only] */
|
#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9] */
|
||||||
#define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */
|
|
||||||
#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
|
#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
|
||||||
#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
|
#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
|
||||||
#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
|
#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
|
||||||
#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
|
#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
|
||||||
|
#define AT91_PMC_MOSCSELS (1 << 16) /* Main Oscillator Selection [some SAM9] */
|
||||||
|
#define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */
|
||||||
|
#define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */
|
||||||
#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
|
#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
|
||||||
|
|
||||||
#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */
|
#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Write Protect Mode Register [some SAM9] */
|
||||||
#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */
|
#define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */
|
||||||
|
#define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */
|
||||||
|
#define AT91_PMC_PROTKEY (0x504d43 << 8) /* Activation Code */
|
||||||
|
|
||||||
#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */
|
#define AT91_PMC_WPSR (AT91_PMC + 0xe8) /* Write Protect Status Register [some SAM9] */
|
||||||
|
#define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */
|
||||||
|
#define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */
|
||||||
|
|
||||||
|
#define AT91_PMC_PCR (AT91_PMC + 0x10c) /* Peripheral Control Register [some SAM9] */
|
||||||
|
#define AT91_PMC_PCR_PID (0x3f << 0) /* Peripheral ID */
|
||||||
|
#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command */
|
||||||
|
#define AT91_PMC_PCR_DIV (0x3 << 16) /* Divisor Value */
|
||||||
|
#define AT91_PMC_PCRDIV(n) (((n) << 16) & AT91_PMC_PCR_DIV)
|
||||||
|
#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,122 +0,0 @@
|
||||||
/*
|
|
||||||
* arch/arm/mach-at91/include/mach/at91cap9.h
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
|
|
||||||
* Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
|
|
||||||
* Copyright (C) 2007 Atmel Corporation.
|
|
||||||
*
|
|
||||||
* Common definitions.
|
|
||||||
* Based on AT91CAP9 datasheet revision B (Preliminary).
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; either version 2 of the License, or
|
|
||||||
* (at your option) any later version.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef AT91CAP9_H
|
|
||||||
#define AT91CAP9_H
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Peripheral identifiers/interrupts.
|
|
||||||
*/
|
|
||||||
#define AT91CAP9_ID_PIOABCD 2 /* Parallel IO Controller A, B, C and D */
|
|
||||||
#define AT91CAP9_ID_MPB0 3 /* MP Block Peripheral 0 */
|
|
||||||
#define AT91CAP9_ID_MPB1 4 /* MP Block Peripheral 1 */
|
|
||||||
#define AT91CAP9_ID_MPB2 5 /* MP Block Peripheral 2 */
|
|
||||||
#define AT91CAP9_ID_MPB3 6 /* MP Block Peripheral 3 */
|
|
||||||
#define AT91CAP9_ID_MPB4 7 /* MP Block Peripheral 4 */
|
|
||||||
#define AT91CAP9_ID_US0 8 /* USART 0 */
|
|
||||||
#define AT91CAP9_ID_US1 9 /* USART 1 */
|
|
||||||
#define AT91CAP9_ID_US2 10 /* USART 2 */
|
|
||||||
#define AT91CAP9_ID_MCI0 11 /* Multimedia Card Interface 0 */
|
|
||||||
#define AT91CAP9_ID_MCI1 12 /* Multimedia Card Interface 1 */
|
|
||||||
#define AT91CAP9_ID_CAN 13 /* CAN */
|
|
||||||
#define AT91CAP9_ID_TWI 14 /* Two-Wire Interface */
|
|
||||||
#define AT91CAP9_ID_SPI0 15 /* Serial Peripheral Interface 0 */
|
|
||||||
#define AT91CAP9_ID_SPI1 16 /* Serial Peripheral Interface 0 */
|
|
||||||
#define AT91CAP9_ID_SSC0 17 /* Serial Synchronous Controller 0 */
|
|
||||||
#define AT91CAP9_ID_SSC1 18 /* Serial Synchronous Controller 1 */
|
|
||||||
#define AT91CAP9_ID_AC97C 19 /* AC97 Controller */
|
|
||||||
#define AT91CAP9_ID_TCB 20 /* Timer Counter 0, 1 and 2 */
|
|
||||||
#define AT91CAP9_ID_PWMC 21 /* Pulse Width Modulation Controller */
|
|
||||||
#define AT91CAP9_ID_EMAC 22 /* Ethernet */
|
|
||||||
#define AT91CAP9_ID_AESTDES 23 /* Advanced Encryption Standard, Triple DES */
|
|
||||||
#define AT91CAP9_ID_ADC 24 /* Analog-to-Digital Converter */
|
|
||||||
#define AT91CAP9_ID_ISI 25 /* Image Sensor Interface */
|
|
||||||
#define AT91CAP9_ID_LCDC 26 /* LCD Controller */
|
|
||||||
#define AT91CAP9_ID_DMA 27 /* DMA Controller */
|
|
||||||
#define AT91CAP9_ID_UDPHS 28 /* USB High Speed Device Port */
|
|
||||||
#define AT91CAP9_ID_UHP 29 /* USB Host Port */
|
|
||||||
#define AT91CAP9_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
|
|
||||||
#define AT91CAP9_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* User Peripheral physical base addresses.
|
|
||||||
*/
|
|
||||||
#define AT91CAP9_BASE_UDPHS 0xfff78000
|
|
||||||
#define AT91CAP9_BASE_TCB0 0xfff7c000
|
|
||||||
#define AT91CAP9_BASE_TC0 0xfff7c000
|
|
||||||
#define AT91CAP9_BASE_TC1 0xfff7c040
|
|
||||||
#define AT91CAP9_BASE_TC2 0xfff7c080
|
|
||||||
#define AT91CAP9_BASE_MCI0 0xfff80000
|
|
||||||
#define AT91CAP9_BASE_MCI1 0xfff84000
|
|
||||||
#define AT91CAP9_BASE_TWI 0xfff88000
|
|
||||||
#define AT91CAP9_BASE_US0 0xfff8c000
|
|
||||||
#define AT91CAP9_BASE_US1 0xfff90000
|
|
||||||
#define AT91CAP9_BASE_US2 0xfff94000
|
|
||||||
#define AT91CAP9_BASE_SSC0 0xfff98000
|
|
||||||
#define AT91CAP9_BASE_SSC1 0xfff9c000
|
|
||||||
#define AT91CAP9_BASE_AC97C 0xfffa0000
|
|
||||||
#define AT91CAP9_BASE_SPI0 0xfffa4000
|
|
||||||
#define AT91CAP9_BASE_SPI1 0xfffa8000
|
|
||||||
#define AT91CAP9_BASE_CAN 0xfffac000
|
|
||||||
#define AT91CAP9_BASE_PWMC 0xfffb8000
|
|
||||||
#define AT91CAP9_BASE_EMAC 0xfffbc000
|
|
||||||
#define AT91CAP9_BASE_ADC 0xfffc0000
|
|
||||||
#define AT91CAP9_BASE_ISI 0xfffc4000
|
|
||||||
|
|
||||||
/*
|
|
||||||
* System Peripherals (offset from AT91_BASE_SYS)
|
|
||||||
*/
|
|
||||||
#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS)
|
|
||||||
#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
|
|
||||||
#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
|
|
||||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
|
||||||
#define AT91_GPBR (cpu_is_at91cap9_revB() ? \
|
|
||||||
(0xfffffd50 - AT91_BASE_SYS) : \
|
|
||||||
(0xfffffd60 - AT91_BASE_SYS))
|
|
||||||
|
|
||||||
#define AT91CAP9_BASE_ECC 0xffffe200
|
|
||||||
#define AT91CAP9_BASE_DMA 0xffffec00
|
|
||||||
#define AT91CAP9_BASE_SMC 0xffffe800
|
|
||||||
#define AT91CAP9_BASE_DBGU AT91_BASE_DBGU1
|
|
||||||
#define AT91CAP9_BASE_PIOA 0xfffff200
|
|
||||||
#define AT91CAP9_BASE_PIOB 0xfffff400
|
|
||||||
#define AT91CAP9_BASE_PIOC 0xfffff600
|
|
||||||
#define AT91CAP9_BASE_PIOD 0xfffff800
|
|
||||||
#define AT91CAP9_BASE_RSTC 0xfffffd00
|
|
||||||
#define AT91CAP9_BASE_SHDWC 0xfffffd10
|
|
||||||
#define AT91CAP9_BASE_RTT 0xfffffd20
|
|
||||||
#define AT91CAP9_BASE_PIT 0xfffffd30
|
|
||||||
#define AT91CAP9_BASE_WDT 0xfffffd40
|
|
||||||
|
|
||||||
#define AT91_USART0 AT91CAP9_BASE_US0
|
|
||||||
#define AT91_USART1 AT91CAP9_BASE_US1
|
|
||||||
#define AT91_USART2 AT91CAP9_BASE_US2
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Internal Memory.
|
|
||||||
*/
|
|
||||||
#define AT91CAP9_SRAM_BASE 0x00100000 /* Internal SRAM base address */
|
|
||||||
#define AT91CAP9_SRAM_SIZE (32 * SZ_1K) /* Internal SRAM size (32Kb) */
|
|
||||||
|
|
||||||
#define AT91CAP9_ROM_BASE 0x00400000 /* Internal ROM base address */
|
|
||||||
#define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */
|
|
||||||
|
|
||||||
#define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */
|
|
||||||
#define AT91CAP9_UDPHS_FIFO 0x00600000 /* USB High Speed Device Port */
|
|
||||||
#define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,137 +0,0 @@
|
||||||
/*
|
|
||||||
* arch/arm/mach-at91/include/mach/at91cap9_matrix.h
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
|
|
||||||
* Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
|
|
||||||
* Copyright (C) 2006 Atmel Corporation.
|
|
||||||
*
|
|
||||||
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
|
|
||||||
* Based on AT91CAP9 datasheet revision B (Preliminary).
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; either version 2 of the License, or
|
|
||||||
* (at your option) any later version.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef AT91CAP9_MATRIX_H
|
|
||||||
#define AT91CAP9_MATRIX_H
|
|
||||||
|
|
||||||
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
|
|
||||||
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
|
|
||||||
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
|
|
||||||
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
|
|
||||||
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
|
|
||||||
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
|
|
||||||
#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
|
|
||||||
#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
|
|
||||||
#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
|
|
||||||
#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */
|
|
||||||
#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */
|
|
||||||
#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */
|
|
||||||
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
|
|
||||||
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
|
|
||||||
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
|
|
||||||
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
|
|
||||||
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
|
|
||||||
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
|
|
||||||
|
|
||||||
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
|
|
||||||
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
|
|
||||||
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
|
|
||||||
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
|
|
||||||
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
|
|
||||||
#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
|
|
||||||
#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
|
|
||||||
#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
|
|
||||||
#define AT91_MATRIX_SCFG8 (AT91_MATRIX + 0x60) /* Slave Configuration Register 8 */
|
|
||||||
#define AT91_MATRIX_SCFG9 (AT91_MATRIX + 0x64) /* Slave Configuration Register 9 */
|
|
||||||
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
|
||||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
|
||||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
|
||||||
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
|
|
||||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
|
|
||||||
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
|
|
||||||
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
|
|
||||||
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
|
|
||||||
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
|
|
||||||
|
|
||||||
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
|
|
||||||
#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
|
|
||||||
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
|
|
||||||
#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
|
|
||||||
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
|
|
||||||
#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
|
|
||||||
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
|
|
||||||
#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
|
|
||||||
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
|
|
||||||
#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
|
|
||||||
#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
|
|
||||||
#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
|
|
||||||
#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
|
|
||||||
#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
|
|
||||||
#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
|
|
||||||
#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
|
|
||||||
#define AT91_MATRIX_PRAS8 (AT91_MATRIX + 0xC0) /* Priority Register A for Slave 8 */
|
|
||||||
#define AT91_MATRIX_PRBS8 (AT91_MATRIX + 0xC4) /* Priority Register B for Slave 8 */
|
|
||||||
#define AT91_MATRIX_PRAS9 (AT91_MATRIX + 0xC8) /* Priority Register A for Slave 9 */
|
|
||||||
#define AT91_MATRIX_PRBS9 (AT91_MATRIX + 0xCC) /* Priority Register B for Slave 9 */
|
|
||||||
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
|
|
||||||
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
|
|
||||||
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
|
|
||||||
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
|
|
||||||
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
|
|
||||||
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
|
|
||||||
#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
|
|
||||||
#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
|
|
||||||
#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
|
|
||||||
#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
|
|
||||||
#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
|
|
||||||
#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
|
|
||||||
|
|
||||||
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
|
|
||||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
|
||||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
|
||||||
#define AT91_MATRIX_RCB2 (1 << 2)
|
|
||||||
#define AT91_MATRIX_RCB3 (1 << 3)
|
|
||||||
#define AT91_MATRIX_RCB4 (1 << 4)
|
|
||||||
#define AT91_MATRIX_RCB5 (1 << 5)
|
|
||||||
#define AT91_MATRIX_RCB6 (1 << 6)
|
|
||||||
#define AT91_MATRIX_RCB7 (1 << 7)
|
|
||||||
#define AT91_MATRIX_RCB8 (1 << 8)
|
|
||||||
#define AT91_MATRIX_RCB9 (1 << 9)
|
|
||||||
#define AT91_MATRIX_RCB10 (1 << 10)
|
|
||||||
#define AT91_MATRIX_RCB11 (1 << 11)
|
|
||||||
|
|
||||||
#define AT91_MPBS0_SFR (AT91_MATRIX + 0x114) /* MPBlock Slave 0 Special Function Register */
|
|
||||||
#define AT91_MPBS1_SFR (AT91_MATRIX + 0x11C) /* MPBlock Slave 1 Special Function Register */
|
|
||||||
|
|
||||||
#define AT91_MATRIX_UDPHS (AT91_MATRIX + 0x118) /* USBHS Special Function Register [AT91CAP9 only] */
|
|
||||||
#define AT91_MATRIX_SELECT_UDPHS (0 << 31) /* select High Speed UDP */
|
|
||||||
#define AT91_MATRIX_SELECT_UDP (1 << 31) /* select standard UDP */
|
|
||||||
#define AT91_MATRIX_UDPHS_BYPASS_LOCK (1 << 30) /* bypass lock bit */
|
|
||||||
|
|
||||||
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */
|
|
||||||
#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
|
||||||
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
|
|
||||||
#define AT91_MATRIX_EBI_CS1A_BCRAMC (1 << 1)
|
|
||||||
#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
|
||||||
#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
|
|
||||||
#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
|
|
||||||
#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */
|
|
||||||
#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
|
|
||||||
#define AT91_MATRIX_EBI_CS4A_SMC_CF1 (1 << 4)
|
|
||||||
#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */
|
|
||||||
#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
|
|
||||||
#define AT91_MATRIX_EBI_CS5A_SMC_CF2 (1 << 5)
|
|
||||||
#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
|
||||||
#define AT91_MATRIX_EBI_DQSPDC (1 << 9) /* Data Qualifier Strobe Pull-Down Configuration */
|
|
||||||
#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
|
||||||
#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
|
|
||||||
#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
|
|
||||||
|
|
||||||
#define AT91_MPBS2_SFR (AT91_MATRIX + 0x12C) /* MPBlock Slave 2 Special Function Register */
|
|
||||||
#define AT91_MPBS3_SFR (AT91_MATRIX + 0x130) /* MPBlock Slave 3 Special Function Register */
|
|
||||||
#define AT91_APB_SFR (AT91_MATRIX + 0x134) /* APB Bridge Special Function Register */
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
@ -59,7 +59,6 @@
|
||||||
#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
|
#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
|
||||||
#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
|
#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
|
||||||
#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
|
#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
|
||||||
#define AT91CAP9_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */
|
|
||||||
#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
|
#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
|
||||||
#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
|
#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
|
||||||
|
|
||||||
|
|
@ -76,7 +75,6 @@
|
||||||
#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */
|
#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */
|
||||||
|
|
||||||
#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */
|
#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */
|
||||||
#define AT91CAP9_DDRSDRC_LPR 0x18 /* Low Power Register */
|
|
||||||
#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
|
#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
|
||||||
#define AT91_DDRSDRC_LPCB_DISABLE 0
|
#define AT91_DDRSDRC_LPCB_DISABLE 0
|
||||||
#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
|
#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
|
||||||
|
|
@ -94,11 +92,9 @@
|
||||||
#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */
|
#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */
|
||||||
|
|
||||||
#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */
|
#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */
|
||||||
#define AT91CAP9_DDRSDRC_MDR 0x1C /* Memory Device Register */
|
|
||||||
#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
|
#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
|
||||||
#define AT91_DDRSDRC_MD_SDR 0
|
#define AT91_DDRSDRC_MD_SDR 0
|
||||||
#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
|
#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
|
||||||
#define AT91CAP9_DDRSDRC_MD_DDR 2
|
|
||||||
#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
|
#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
|
||||||
#define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */
|
#define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */
|
||||||
#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */
|
#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */
|
||||||
|
|
@ -106,16 +102,10 @@
|
||||||
#define AT91_DDRSDRC_DBW_16BITS (1 << 4)
|
#define AT91_DDRSDRC_DBW_16BITS (1 << 4)
|
||||||
|
|
||||||
#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */
|
#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */
|
||||||
#define AT91CAP9_DDRSDRC_DLL 0x20 /* DLL Information Register */
|
|
||||||
#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
|
#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
|
||||||
#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
|
#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
|
||||||
#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
|
#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
|
||||||
#define AT91CAP9_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */
|
|
||||||
#define AT91CAP9_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */
|
|
||||||
#define AT91CAP9_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */
|
|
||||||
#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
|
#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
|
||||||
#define AT91CAP9_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */
|
|
||||||
#define AT91CAP9_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */
|
|
||||||
|
|
||||||
#define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */
|
#define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */
|
||||||
#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */
|
#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,80 @@
|
||||||
|
/*
|
||||||
|
* Chip-specific header file for the AT91SAM9x5 family
|
||||||
|
*
|
||||||
|
* Copyright (C) 2009-2012 Atmel Corporation.
|
||||||
|
*
|
||||||
|
* Common definitions.
|
||||||
|
* Based on AT91SAM9x5 datasheet.
|
||||||
|
*
|
||||||
|
* Licensed under GPLv2 or later.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef AT91SAM9X5_H
|
||||||
|
#define AT91SAM9X5_H
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Peripheral identifiers/interrupts.
|
||||||
|
*/
|
||||||
|
#define AT91SAM9X5_ID_PIOAB 2 /* Parallel I/O Controller A and B */
|
||||||
|
#define AT91SAM9X5_ID_PIOCD 3 /* Parallel I/O Controller C and D */
|
||||||
|
#define AT91SAM9X5_ID_SMD 4 /* SMD Soft Modem (SMD) */
|
||||||
|
#define AT91SAM9X5_ID_USART0 5 /* USART 0 */
|
||||||
|
#define AT91SAM9X5_ID_USART1 6 /* USART 1 */
|
||||||
|
#define AT91SAM9X5_ID_USART2 7 /* USART 2 */
|
||||||
|
#define AT91SAM9X5_ID_USART3 8 /* USART 3 */
|
||||||
|
#define AT91SAM9X5_ID_TWI0 9 /* Two-Wire Interface 0 */
|
||||||
|
#define AT91SAM9X5_ID_TWI1 10 /* Two-Wire Interface 1 */
|
||||||
|
#define AT91SAM9X5_ID_TWI2 11 /* Two-Wire Interface 2 */
|
||||||
|
#define AT91SAM9X5_ID_MCI0 12 /* High Speed Multimedia Card Interface 0 */
|
||||||
|
#define AT91SAM9X5_ID_SPI0 13 /* Serial Peripheral Interface 0 */
|
||||||
|
#define AT91SAM9X5_ID_SPI1 14 /* Serial Peripheral Interface 1 */
|
||||||
|
#define AT91SAM9X5_ID_UART0 15 /* UART 0 */
|
||||||
|
#define AT91SAM9X5_ID_UART1 16 /* UART 1 */
|
||||||
|
#define AT91SAM9X5_ID_TCB 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
|
||||||
|
#define AT91SAM9X5_ID_PWM 18 /* Pulse Width Modulation Controller */
|
||||||
|
#define AT91SAM9X5_ID_ADC 19 /* ADC Controller */
|
||||||
|
#define AT91SAM9X5_ID_DMA0 20 /* DMA Controller 0 */
|
||||||
|
#define AT91SAM9X5_ID_DMA1 21 /* DMA Controller 1 */
|
||||||
|
#define AT91SAM9X5_ID_UHPHS 22 /* USB Host High Speed */
|
||||||
|
#define AT91SAM9X5_ID_UDPHS 23 /* USB Device High Speed */
|
||||||
|
#define AT91SAM9X5_ID_EMAC0 24 /* Ethernet MAC0 */
|
||||||
|
#define AT91SAM9X5_ID_LCDC 25 /* LCD Controller */
|
||||||
|
#define AT91SAM9X5_ID_ISI 25 /* Image Sensor Interface */
|
||||||
|
#define AT91SAM9X5_ID_MCI1 26 /* High Speed Multimedia Card Interface 1 */
|
||||||
|
#define AT91SAM9X5_ID_EMAC1 27 /* Ethernet MAC1 */
|
||||||
|
#define AT91SAM9X5_ID_SSC 28 /* Synchronous Serial Controller */
|
||||||
|
#define AT91SAM9X5_ID_CAN0 29 /* CAN Controller 0 */
|
||||||
|
#define AT91SAM9X5_ID_CAN1 30 /* CAN Controller 1 */
|
||||||
|
#define AT91SAM9X5_ID_IRQ0 31 /* Advanced Interrupt Controller */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* User Peripheral physical base addresses.
|
||||||
|
*/
|
||||||
|
#define AT91SAM9X5_BASE_USART0 0xf801c000
|
||||||
|
#define AT91SAM9X5_BASE_USART1 0xf8020000
|
||||||
|
#define AT91SAM9X5_BASE_USART2 0xf8024000
|
||||||
|
|
||||||
|
/*
|
||||||
|
* System Peripherals (offset from AT91_BASE_SYS)
|
||||||
|
*/
|
||||||
|
#define AT91_DDRSDRC0 (0xffffe800 - AT91_BASE_SYS)
|
||||||
|
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Base addresses for early serial code (uncompress.h)
|
||||||
|
*/
|
||||||
|
#define AT91_DBGU AT91_BASE_DBGU0
|
||||||
|
#define AT91_USART0 AT91SAM9X5_BASE_USART0
|
||||||
|
#define AT91_USART1 AT91SAM9X5_BASE_USART1
|
||||||
|
#define AT91_USART2 AT91SAM9X5_BASE_USART2
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Internal Memory.
|
||||||
|
*/
|
||||||
|
#define AT91SAM9X5_SRAM_BASE 0x00300000 /* Internal SRAM base address */
|
||||||
|
#define AT91SAM9X5_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */
|
||||||
|
|
||||||
|
#define AT91SAM9X5_ROM_BASE 0x00400000 /* Internal ROM base address */
|
||||||
|
#define AT91SAM9X5_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,53 @@
|
||||||
|
/*
|
||||||
|
* Matrix-centric header file for the AT91SAM9x5 family
|
||||||
|
*
|
||||||
|
* Copyright (C) 2009-2012 Atmel Corporation.
|
||||||
|
*
|
||||||
|
* Only EBI related registers.
|
||||||
|
* Write Protect register definitions may be useful.
|
||||||
|
*
|
||||||
|
* Licensed under GPLv2 or later.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef AT91SAM9X5_MATRIX_H
|
||||||
|
#define AT91SAM9X5_MATRIX_H
|
||||||
|
|
||||||
|
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */
|
||||||
|
#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||||
|
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
|
||||||
|
#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
|
||||||
|
#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||||
|
#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
|
||||||
|
#define AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3)
|
||||||
|
#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||||
|
#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
|
||||||
|
#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
|
||||||
|
#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
||||||
|
#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
|
||||||
|
#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
|
||||||
|
#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
|
||||||
|
#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
|
||||||
|
#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
|
||||||
|
#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
|
||||||
|
#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
|
||||||
|
#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
|
||||||
|
#define AT91_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */
|
||||||
|
#define AT91_MATRIX_NFD0_ON_D0 (0 << 24)
|
||||||
|
#define AT91_MATRIX_NFD0_ON_D16 (1 << 24)
|
||||||
|
#define AT91_MATRIX_DDR_MP_EN (1 << 25) /* DDR Multi-port Enable */
|
||||||
|
#define AT91_MATRIX_MP_OFF (0 << 25)
|
||||||
|
#define AT91_MATRIX_MP_ON (1 << 25)
|
||||||
|
|
||||||
|
#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
|
||||||
|
#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
|
||||||
|
#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
|
||||||
|
#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
|
||||||
|
#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
|
||||||
|
|
||||||
|
#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
|
||||||
|
#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
|
||||||
|
#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
|
||||||
|
#define AT91_MATRIX_WPSR_WPV (1 << 0)
|
||||||
|
#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -25,7 +25,6 @@
|
||||||
#define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */
|
#define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */
|
||||||
#define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */
|
#define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */
|
||||||
#define ARCH_ID_AT91SAM9X5 0x819a05a0
|
#define ARCH_ID_AT91SAM9X5 0x819a05a0
|
||||||
#define ARCH_ID_AT91CAP9 0x039A03A0
|
|
||||||
|
|
||||||
#define ARCH_ID_AT91SAM9XE128 0x329973a0
|
#define ARCH_ID_AT91SAM9XE128 0x329973a0
|
||||||
#define ARCH_ID_AT91SAM9XE256 0x329a93a0
|
#define ARCH_ID_AT91SAM9XE256 0x329a93a0
|
||||||
|
|
@ -51,10 +50,6 @@
|
||||||
#define ARCH_FAMILY_AT91SAM9 0x01900000
|
#define ARCH_FAMILY_AT91SAM9 0x01900000
|
||||||
#define ARCH_FAMILY_AT91SAM9XE 0x02900000
|
#define ARCH_FAMILY_AT91SAM9XE 0x02900000
|
||||||
|
|
||||||
/* PMC revision */
|
|
||||||
#define ARCH_REVISION_CAP9_B 0x399
|
|
||||||
#define ARCH_REVISION_CAP9_C 0x601
|
|
||||||
|
|
||||||
/* RM9200 type */
|
/* RM9200 type */
|
||||||
#define ARCH_REVISON_9200_BGA (0 << 0)
|
#define ARCH_REVISON_9200_BGA (0 << 0)
|
||||||
#define ARCH_REVISON_9200_PQFP (1 << 0)
|
#define ARCH_REVISON_9200_PQFP (1 << 0)
|
||||||
|
|
@ -63,9 +58,6 @@ enum at91_soc_type {
|
||||||
/* 920T */
|
/* 920T */
|
||||||
AT91_SOC_RM9200,
|
AT91_SOC_RM9200,
|
||||||
|
|
||||||
/* CAP */
|
|
||||||
AT91_SOC_CAP9,
|
|
||||||
|
|
||||||
/* SAM92xx */
|
/* SAM92xx */
|
||||||
AT91_SOC_SAM9260, AT91_SOC_SAM9261, AT91_SOC_SAM9263,
|
AT91_SOC_SAM9260, AT91_SOC_SAM9261, AT91_SOC_SAM9263,
|
||||||
|
|
||||||
|
|
@ -86,9 +78,6 @@ enum at91_soc_subtype {
|
||||||
/* RM9200 */
|
/* RM9200 */
|
||||||
AT91_SOC_RM9200_BGA, AT91_SOC_RM9200_PQFP,
|
AT91_SOC_RM9200_BGA, AT91_SOC_RM9200_PQFP,
|
||||||
|
|
||||||
/* CAP9 */
|
|
||||||
AT91_SOC_CAP9_REV_B, AT91_SOC_CAP9_REV_C,
|
|
||||||
|
|
||||||
/* SAM9260 */
|
/* SAM9260 */
|
||||||
AT91_SOC_SAM9XE,
|
AT91_SOC_SAM9XE,
|
||||||
|
|
||||||
|
|
@ -195,16 +184,6 @@ static inline int at91_soc_is_detected(void)
|
||||||
#define cpu_is_at91sam9x25() (0)
|
#define cpu_is_at91sam9x25() (0)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_AT91CAP9
|
|
||||||
#define cpu_is_at91cap9() (at91_soc_initdata.type == AT91_SOC_CAP9)
|
|
||||||
#define cpu_is_at91cap9_revB() (at91_soc_initdata.subtype == AT91_SOC_CAP9_REV_B)
|
|
||||||
#define cpu_is_at91cap9_revC() (at91_soc_initdata.subtype == AT91_SOC_CAP9_REV_C)
|
|
||||||
#else
|
|
||||||
#define cpu_is_at91cap9() (0)
|
|
||||||
#define cpu_is_at91cap9_revB() (0)
|
|
||||||
#define cpu_is_at91cap9_revC() (0)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Since this is ARM, we will never run on any AVR32 CPU. But these
|
* Since this is ARM, we will never run on any AVR32 CPU. But these
|
||||||
* definitions may reduce clutter in common drivers.
|
* definitions may reduce clutter in common drivers.
|
||||||
|
|
|
||||||
|
|
@ -19,7 +19,7 @@
|
||||||
/* DBGU base */
|
/* DBGU base */
|
||||||
/* rm9200, 9260/9g20, 9261/9g10, 9rl */
|
/* rm9200, 9260/9g20, 9261/9g10, 9rl */
|
||||||
#define AT91_BASE_DBGU0 0xfffff200
|
#define AT91_BASE_DBGU0 0xfffff200
|
||||||
/* 9263, 9g45, cap9 */
|
/* 9263, 9g45 */
|
||||||
#define AT91_BASE_DBGU1 0xffffee00
|
#define AT91_BASE_DBGU1 0xffffee00
|
||||||
|
|
||||||
#if defined(CONFIG_ARCH_AT91RM9200)
|
#if defined(CONFIG_ARCH_AT91RM9200)
|
||||||
|
|
@ -34,8 +34,8 @@
|
||||||
#include <mach/at91sam9rl.h>
|
#include <mach/at91sam9rl.h>
|
||||||
#elif defined(CONFIG_ARCH_AT91SAM9G45)
|
#elif defined(CONFIG_ARCH_AT91SAM9G45)
|
||||||
#include <mach/at91sam9g45.h>
|
#include <mach/at91sam9g45.h>
|
||||||
#elif defined(CONFIG_ARCH_AT91CAP9)
|
#elif defined(CONFIG_ARCH_AT91SAM9X5)
|
||||||
#include <mach/at91cap9.h>
|
#include <mach/at91sam9x5.h>
|
||||||
#elif defined(CONFIG_ARCH_AT91X40)
|
#elif defined(CONFIG_ARCH_AT91X40)
|
||||||
#include <mach/at91x40.h>
|
#include <mach/at91x40.h>
|
||||||
#else
|
#else
|
||||||
|
|
|
||||||
|
|
@ -150,11 +150,6 @@ static int at91_pm_verify_clocks(void)
|
||||||
pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
|
pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
} else if (cpu_is_at91cap9()) {
|
|
||||||
if ((scsr & AT91CAP9_PMC_UHP) != 0) {
|
|
||||||
pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
|
#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
|
||||||
|
|
|
||||||
|
|
@ -24,24 +24,6 @@ static inline u32 sdram_selfrefresh_enable(void)
|
||||||
#define wait_for_interrupt_enable() asm volatile ("mcr p15, 0, %0, c7, c0, 4" \
|
#define wait_for_interrupt_enable() asm volatile ("mcr p15, 0, %0, c7, c0, 4" \
|
||||||
: : "r" (0))
|
: : "r" (0))
|
||||||
|
|
||||||
#elif defined(CONFIG_ARCH_AT91CAP9)
|
|
||||||
#include <mach/at91sam9_ddrsdr.h>
|
|
||||||
|
|
||||||
|
|
||||||
static inline u32 sdram_selfrefresh_enable(void)
|
|
||||||
{
|
|
||||||
u32 saved_lpr, lpr;
|
|
||||||
|
|
||||||
saved_lpr = at91_ramc_read(0, AT91CAP9_DDRSDRC_LPR);
|
|
||||||
|
|
||||||
lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
|
|
||||||
at91_ramc_write(0, AT91CAP9_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
|
|
||||||
return saved_lpr;
|
|
||||||
}
|
|
||||||
|
|
||||||
#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91CAP9_DDRSDRC_LPR, saved_lpr)
|
|
||||||
#define wait_for_interrupt_enable() cpu_do_idle()
|
|
||||||
|
|
||||||
#elif defined(CONFIG_ARCH_AT91SAM9G45)
|
#elif defined(CONFIG_ARCH_AT91SAM9G45)
|
||||||
#include <mach/at91sam9_ddrsdr.h>
|
#include <mach/at91sam9_ddrsdr.h>
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -18,8 +18,7 @@
|
||||||
|
|
||||||
#if defined(CONFIG_ARCH_AT91RM9200)
|
#if defined(CONFIG_ARCH_AT91RM9200)
|
||||||
#include <mach/at91rm9200_mc.h>
|
#include <mach/at91rm9200_mc.h>
|
||||||
#elif defined(CONFIG_ARCH_AT91CAP9) \
|
#elif defined(CONFIG_ARCH_AT91SAM9G45)
|
||||||
|| defined(CONFIG_ARCH_AT91SAM9G45)
|
|
||||||
#include <mach/at91sam9_ddrsdr.h>
|
#include <mach/at91sam9_ddrsdr.h>
|
||||||
#else
|
#else
|
||||||
#include <mach/at91sam9_sdramc.h>
|
#include <mach/at91sam9_sdramc.h>
|
||||||
|
|
@ -130,8 +129,7 @@ ENTRY(at91_slow_clock)
|
||||||
/* Put SDRAM in self-refresh mode */
|
/* Put SDRAM in self-refresh mode */
|
||||||
mov r3, #1
|
mov r3, #1
|
||||||
str r3, [r2, #AT91_SDRAMC_SRR]
|
str r3, [r2, #AT91_SDRAMC_SRR]
|
||||||
#elif defined(CONFIG_ARCH_AT91CAP9) \
|
#elif defined(CONFIG_ARCH_AT91SAM9G45)
|
||||||
|| defined(CONFIG_ARCH_AT91SAM9G45)
|
|
||||||
|
|
||||||
/* prepare for DDRAM self-refresh mode */
|
/* prepare for DDRAM self-refresh mode */
|
||||||
ldr r3, [r2, #AT91_DDRSDRC_LPR]
|
ldr r3, [r2, #AT91_DDRSDRC_LPR]
|
||||||
|
|
@ -263,8 +261,7 @@ ENTRY(at91_slow_clock)
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_AT91RM9200
|
#ifdef CONFIG_ARCH_AT91RM9200
|
||||||
/* Do nothing - self-refresh is automatically disabled. */
|
/* Do nothing - self-refresh is automatically disabled. */
|
||||||
#elif defined(CONFIG_ARCH_AT91CAP9) \
|
#elif defined(CONFIG_ARCH_AT91SAM9G45)
|
||||||
|| defined(CONFIG_ARCH_AT91SAM9G45)
|
|
||||||
/* Restore LPR on AT91 with DDRAM */
|
/* Restore LPR on AT91 with DDRAM */
|
||||||
ldr r3, .saved_sam9_lpr
|
ldr r3, .saved_sam9_lpr
|
||||||
str r3, [r2, #AT91_DDRSDRC_LPR]
|
str r3, [r2, #AT91_DDRSDRC_LPR]
|
||||||
|
|
@ -305,8 +302,7 @@ ENTRY(at91_slow_clock)
|
||||||
#ifdef CONFIG_ARCH_AT91RM9200
|
#ifdef CONFIG_ARCH_AT91RM9200
|
||||||
.at91_va_base_sdramc:
|
.at91_va_base_sdramc:
|
||||||
.word AT91_VA_BASE_SYS
|
.word AT91_VA_BASE_SYS
|
||||||
#elif defined(CONFIG_ARCH_AT91CAP9) \
|
#elif defined(CONFIG_ARCH_AT91SAM9G45)
|
||||||
|| defined(CONFIG_ARCH_AT91SAM9G45)
|
|
||||||
.at91_va_base_sdramc:
|
.at91_va_base_sdramc:
|
||||||
.word AT91_VA_BASE_SYS + AT91_DDRSDRC0
|
.word AT91_VA_BASE_SYS + AT91_DDRSDRC0
|
||||||
#else
|
#else
|
||||||
|
|
|
||||||
|
|
@ -86,20 +86,6 @@ static void __init soc_detect(u32 dbgu_base)
|
||||||
socid = cidr & ~AT91_CIDR_VERSION;
|
socid = cidr & ~AT91_CIDR_VERSION;
|
||||||
|
|
||||||
switch (socid) {
|
switch (socid) {
|
||||||
case ARCH_ID_AT91CAP9: {
|
|
||||||
#ifdef CONFIG_AT91_PMC_UNIT
|
|
||||||
u32 pmc_ver = at91_sys_read(AT91_PMC_VER);
|
|
||||||
|
|
||||||
if (pmc_ver == ARCH_REVISION_CAP9_B)
|
|
||||||
at91_soc_initdata.subtype = AT91_SOC_CAP9_REV_B;
|
|
||||||
else if (pmc_ver == ARCH_REVISION_CAP9_C)
|
|
||||||
at91_soc_initdata.subtype = AT91_SOC_CAP9_REV_C;
|
|
||||||
#endif
|
|
||||||
at91_soc_initdata.type = AT91_SOC_CAP9;
|
|
||||||
at91_boot_soc = at91cap9_soc;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
case ARCH_ID_AT91RM9200:
|
case ARCH_ID_AT91RM9200:
|
||||||
at91_soc_initdata.type = AT91_SOC_RM9200;
|
at91_soc_initdata.type = AT91_SOC_RM9200;
|
||||||
at91_boot_soc = at91rm9200_soc;
|
at91_boot_soc = at91rm9200_soc;
|
||||||
|
|
@ -200,7 +186,6 @@ static void __init soc_detect(u32 dbgu_base)
|
||||||
|
|
||||||
static const char *soc_name[] = {
|
static const char *soc_name[] = {
|
||||||
[AT91_SOC_RM9200] = "at91rm9200",
|
[AT91_SOC_RM9200] = "at91rm9200",
|
||||||
[AT91_SOC_CAP9] = "at91cap9",
|
|
||||||
[AT91_SOC_SAM9260] = "at91sam9260",
|
[AT91_SOC_SAM9260] = "at91sam9260",
|
||||||
[AT91_SOC_SAM9261] = "at91sam9261",
|
[AT91_SOC_SAM9261] = "at91sam9261",
|
||||||
[AT91_SOC_SAM9263] = "at91sam9263",
|
[AT91_SOC_SAM9263] = "at91sam9263",
|
||||||
|
|
@ -221,8 +206,6 @@ EXPORT_SYMBOL(at91_get_soc_type);
|
||||||
static const char *soc_subtype_name[] = {
|
static const char *soc_subtype_name[] = {
|
||||||
[AT91_SOC_RM9200_BGA] = "at91rm9200 BGA",
|
[AT91_SOC_RM9200_BGA] = "at91rm9200 BGA",
|
||||||
[AT91_SOC_RM9200_PQFP] = "at91rm9200 PQFP",
|
[AT91_SOC_RM9200_PQFP] = "at91rm9200 PQFP",
|
||||||
[AT91_SOC_CAP9_REV_B] = "at91cap9 revB",
|
|
||||||
[AT91_SOC_CAP9_REV_C] = "at91cap9 revC",
|
|
||||||
[AT91_SOC_SAM9XE] = "at91sam9xe",
|
[AT91_SOC_SAM9XE] = "at91sam9xe",
|
||||||
[AT91_SOC_SAM9G45ES] = "at91sam9g45es",
|
[AT91_SOC_SAM9G45ES] = "at91sam9g45es",
|
||||||
[AT91_SOC_SAM9M10] = "at91sam9m10",
|
[AT91_SOC_SAM9M10] = "at91sam9m10",
|
||||||
|
|
|
||||||
|
|
@ -13,7 +13,6 @@ struct at91_init_soc {
|
||||||
};
|
};
|
||||||
|
|
||||||
extern struct at91_init_soc at91_boot_soc;
|
extern struct at91_init_soc at91_boot_soc;
|
||||||
extern struct at91_init_soc at91cap9_soc;
|
|
||||||
extern struct at91_init_soc at91rm9200_soc;
|
extern struct at91_init_soc at91rm9200_soc;
|
||||||
extern struct at91_init_soc at91sam9260_soc;
|
extern struct at91_init_soc at91sam9260_soc;
|
||||||
extern struct at91_init_soc at91sam9261_soc;
|
extern struct at91_init_soc at91sam9261_soc;
|
||||||
|
|
@ -27,10 +26,6 @@ static inline int at91_soc_is_enabled(void)
|
||||||
return at91_boot_soc.init != NULL;
|
return at91_boot_soc.init != NULL;
|
||||||
}
|
}
|
||||||
|
|
||||||
#if !defined(CONFIG_ARCH_AT91CAP9)
|
|
||||||
#define at91cap9_soc at91_boot_soc
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(CONFIG_ARCH_AT91RM9200)
|
#if !defined(CONFIG_ARCH_AT91RM9200)
|
||||||
#define at91rm9200_soc at91_boot_soc
|
#define at91rm9200_soc at91_boot_soc
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -30,9 +30,6 @@
|
||||||
#define cpu_is_at91sam9261() (0)
|
#define cpu_is_at91sam9261() (0)
|
||||||
#define cpu_is_at91sam9263() (0)
|
#define cpu_is_at91sam9263() (0)
|
||||||
#define cpu_is_at91sam9rl() (0)
|
#define cpu_is_at91sam9rl() (0)
|
||||||
#define cpu_is_at91cap9() (0)
|
|
||||||
#define cpu_is_at91cap9_revB() (0)
|
|
||||||
#define cpu_is_at91cap9_revC() (0)
|
|
||||||
#define cpu_is_at91sam9g10() (0)
|
#define cpu_is_at91sam9g10() (0)
|
||||||
#define cpu_is_at91sam9g20() (0)
|
#define cpu_is_at91sam9g20() (0)
|
||||||
#define cpu_is_at91sam9g45() (0)
|
#define cpu_is_at91sam9g45() (0)
|
||||||
|
|
|
||||||
|
|
@ -86,7 +86,6 @@ static inline int at91mci_is_mci1rev2xx(void)
|
||||||
{
|
{
|
||||||
return ( cpu_is_at91sam9260()
|
return ( cpu_is_at91sam9260()
|
||||||
|| cpu_is_at91sam9263()
|
|| cpu_is_at91sam9263()
|
||||||
|| cpu_is_at91cap9()
|
|
||||||
|| cpu_is_at91sam9rl()
|
|| cpu_is_at91sam9rl()
|
||||||
|| cpu_is_at91sam9g10()
|
|| cpu_is_at91sam9g10()
|
||||||
|| cpu_is_at91sam9g20()
|
|| cpu_is_at91sam9g20()
|
||||||
|
|
|
||||||
|
|
@ -137,7 +137,7 @@ choice
|
||||||
|
|
||||||
config USB_AT91
|
config USB_AT91
|
||||||
tristate "Atmel AT91 USB Device Port"
|
tristate "Atmel AT91 USB Device Port"
|
||||||
depends on ARCH_AT91 && !ARCH_AT91SAM9RL && !ARCH_AT91CAP9 && !ARCH_AT91SAM9G45
|
depends on ARCH_AT91 && !ARCH_AT91SAM9RL && !ARCH_AT91SAM9G45
|
||||||
help
|
help
|
||||||
Many Atmel AT91 processors (such as the AT91RM2000) have a
|
Many Atmel AT91 processors (such as the AT91RM2000) have a
|
||||||
full speed USB Device Port with support for five configurable
|
full speed USB Device Port with support for five configurable
|
||||||
|
|
@ -150,7 +150,7 @@ config USB_AT91
|
||||||
config USB_ATMEL_USBA
|
config USB_ATMEL_USBA
|
||||||
tristate "Atmel USBA"
|
tristate "Atmel USBA"
|
||||||
select USB_GADGET_DUALSPEED
|
select USB_GADGET_DUALSPEED
|
||||||
depends on AVR32 || ARCH_AT91CAP9 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G45
|
depends on AVR32 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G45
|
||||||
help
|
help
|
||||||
USBA is the integrated high-speed USB Device controller on
|
USBA is the integrated high-speed USB Device controller on
|
||||||
the AT32AP700x, some AT91SAM9 and AT91CAP9 processors from Atmel.
|
the AT32AP700x, some AT91SAM9 and AT91CAP9 processors from Atmel.
|
||||||
|
|
|
||||||
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