mtd: st_spi_fsm: Move runtime configurable msg sequences into device's struct
Until now the dynamically configurable message sequences for read, write and enable 32bit addressing have been global. Brian makes a good point why this should not be the case. If there are ever two FSM's located on the same platform, we could be potentially introducing a race condition on "needlessly shared data". Suggested-by: Brian Norris <computersforpeace@gmail.com> Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This commit is contained in:
Lee Jones
Brian Norris
Родитель
cd7cac9ec3
Коммит
e6b1bb4e18
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@ -273,6 +273,19 @@
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#define CFG_ERASESEC_TOGGLE_32BIT_ADDR 0x00000008
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#define CFG_S25FL_CHECK_ERROR_FLAGS 0x00000010
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struct stfsm_seq {
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uint32_t data_size;
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uint32_t addr1;
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uint32_t addr2;
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uint32_t addr_cfg;
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uint32_t seq_opc[5];
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uint32_t mode;
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uint32_t dummy;
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uint32_t status;
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uint8_t seq[16];
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uint32_t seq_cfg;
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} __packed __aligned(4);
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struct stfsm {
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struct device *dev;
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void __iomem *base;
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@ -286,20 +299,11 @@ struct stfsm {
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bool booted_from_spi;
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bool reset_signal;
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bool reset_por;
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};
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struct stfsm_seq {
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uint32_t data_size;
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uint32_t addr1;
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uint32_t addr2;
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uint32_t addr_cfg;
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uint32_t seq_opc[5];
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uint32_t mode;
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uint32_t dummy;
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uint32_t status;
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uint8_t seq[16];
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uint32_t seq_cfg;
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} __packed __aligned(4);
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struct stfsm_seq stfsm_seq_read;
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struct stfsm_seq stfsm_seq_write;
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struct stfsm_seq stfsm_seq_en_32bit_addr;
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};
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/* Parameters to configure a READ or WRITE FSM sequence */
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struct seq_rw_config {
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@ -587,10 +591,6 @@ static struct seq_rw_config stfsm_s25fl_write4_configs[] = {
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*/
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#define W25Q_STATUS_QE (0x1 << 9)
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static struct stfsm_seq stfsm_seq_read; /* Dynamically populated */
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static struct stfsm_seq stfsm_seq_write; /* Dynamically populated */
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static struct stfsm_seq stfsm_seq_en_32bit_addr;/* Dynamically populated */
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static struct stfsm_seq stfsm_seq_read_jedec = {
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.data_size = TRANSFER_SIZE(8),
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.seq_opc[0] = (SEQ_OPC_PADS_1 |
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@ -826,7 +826,7 @@ static int stfsm_write_fifo(struct stfsm *fsm,
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static int stfsm_enter_32bit_addr(struct stfsm *fsm, int enter)
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{
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struct stfsm_seq *seq = &stfsm_seq_en_32bit_addr;
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struct stfsm_seq *seq = &fsm->stfsm_seq_en_32bit_addr;
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uint32_t cmd = enter ? FLASH_CMD_EN4B_ADDR : FLASH_CMD_EX4B_ADDR;
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seq->seq_opc[0] = (SEQ_OPC_PADS_1 |
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@ -1101,7 +1101,7 @@ static int stfsm_prepare_rwe_seqs_default(struct stfsm *fsm)
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int ret;
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/* Configure 'READ' sequence */
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ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_read,
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ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read,
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default_read_configs);
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if (ret) {
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dev_err(fsm->dev,
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@ -1111,7 +1111,7 @@ static int stfsm_prepare_rwe_seqs_default(struct stfsm *fsm)
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}
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/* Configure 'WRITE' sequence */
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ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_write,
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ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_write,
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default_write_configs);
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if (ret) {
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dev_err(fsm->dev,
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@ -1146,7 +1146,7 @@ static int stfsm_mx25_config(struct stfsm *fsm)
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*/
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if (flags & FLASH_FLAG_32BIT_ADDR) {
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/* Configure 'enter_32bitaddr' FSM sequence */
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stfsm_mx25_en_32bit_addr_seq(&stfsm_seq_en_32bit_addr);
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stfsm_mx25_en_32bit_addr_seq(&fsm->stfsm_seq_en_32bit_addr);
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soc_reset = stfsm_can_handle_soc_reset(fsm);
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if (soc_reset || !fsm->booted_from_spi) {
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@ -1169,7 +1169,7 @@ static int stfsm_mx25_config(struct stfsm *fsm)
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}
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/* For QUAD mode, set 'QE' STATUS bit */
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data_pads = ((stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1;
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data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1;
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if (data_pads == 4) {
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stfsm_read_status(fsm, FLASH_CMD_RDSR, &sta);
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sta |= MX25_STATUS_QE;
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@ -1188,10 +1188,10 @@ static int stfsm_n25q_config(struct stfsm *fsm)
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/* Configure 'READ' sequence */
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if (flags & FLASH_FLAG_32BIT_ADDR)
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ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_read,
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ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read,
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n25q_read4_configs);
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else
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ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_read,
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ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read,
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n25q_read3_configs);
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if (ret) {
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dev_err(fsm->dev,
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@ -1201,7 +1201,7 @@ static int stfsm_n25q_config(struct stfsm *fsm)
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}
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/* Configure 'WRITE' sequence (default configs) */
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ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_write,
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ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_write,
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default_write_configs);
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if (ret) {
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dev_err(fsm->dev,
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@ -1215,7 +1215,7 @@ static int stfsm_n25q_config(struct stfsm *fsm)
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/* Configure 32-bit address support */
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if (flags & FLASH_FLAG_32BIT_ADDR) {
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stfsm_n25q_en_32bit_addr_seq(&stfsm_seq_en_32bit_addr);
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stfsm_n25q_en_32bit_addr_seq(&fsm->stfsm_seq_en_32bit_addr);
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soc_reset = stfsm_can_handle_soc_reset(fsm);
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if (soc_reset || !fsm->booted_from_spi) {
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@ -1374,12 +1374,12 @@ static int stfsm_s25fl_config(struct stfsm *fsm)
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* Prepare Read/Write/Erase sequences according to S25FLxxx
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* 32-bit address command set
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*/
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ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_read,
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ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read,
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stfsm_s25fl_read4_configs);
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if (ret)
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return ret;
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ret = stfsm_search_prepare_rw_seq(fsm, &stfsm_seq_write,
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ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_write,
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stfsm_s25fl_write4_configs);
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if (ret)
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return ret;
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@ -1415,7 +1415,7 @@ static int stfsm_s25fl_config(struct stfsm *fsm)
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}
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/* Check status of 'QE' bit */
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data_pads = ((stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1;
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data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1;
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stfsm_read_status(fsm, FLASH_CMD_RDSR2, &cr1);
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if (data_pads == 4) {
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if (!(cr1 & STFSM_S25FL_CONFIG_QE)) {
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@ -1465,7 +1465,7 @@ static int stfsm_w25q_config(struct stfsm *fsm)
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return ret;
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/* If using QUAD mode, set QE STATUS bit */
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data_pads = ((stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1;
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data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1;
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if (data_pads == 4) {
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stfsm_read_status(fsm, FLASH_CMD_RDSR, &sta1);
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stfsm_read_status(fsm, FLASH_CMD_RDSR2, &sta2);
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@ -1485,7 +1485,7 @@ static int stfsm_w25q_config(struct stfsm *fsm)
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static int stfsm_read(struct stfsm *fsm, uint8_t *buf, uint32_t size,
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uint32_t offset)
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{
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struct stfsm_seq *seq = &stfsm_seq_read;
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struct stfsm_seq *seq = &fsm->stfsm_seq_read;
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uint32_t data_pads;
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uint32_t read_mask;
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uint32_t size_ub;
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@ -1546,7 +1546,7 @@ static int stfsm_read(struct stfsm *fsm, uint8_t *buf, uint32_t size,
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static int stfsm_write(struct stfsm *fsm, const uint8_t *const buf,
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const uint32_t size, const uint32_t offset)
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{
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struct stfsm_seq *seq = &stfsm_seq_write;
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struct stfsm_seq *seq = &fsm->stfsm_seq_write;
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uint32_t data_pads;
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uint32_t write_mask;
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uint32_t size_ub;
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