[Blackfin] arch: Functional power management support: Add support for cpu frequency scaling
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
Michael Hennerich
Bryan Wu
Родитель
fe44193c55
Коммит
e6c91b64dd
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@ -16,11 +16,35 @@
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#include <linux/irq.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/cpufreq.h>
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#include <asm/blackfin.h>
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#include <asm/time.h>
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#ifdef CONFIG_CYCLES_CLOCKSOURCE
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/* Accelerators for sched_clock()
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* convert from cycles(64bits) => nanoseconds (64bits)
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* basic equation:
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* ns = cycles / (freq / ns_per_sec)
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* ns = cycles * (ns_per_sec / freq)
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* ns = cycles * (10^9 / (cpu_khz * 10^3))
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* ns = cycles * (10^6 / cpu_khz)
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*
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* Then we use scaling math (suggested by george@mvista.com) to get:
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* ns = cycles * (10^6 * SC / cpu_khz) / SC
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* ns = cycles * cyc2ns_scale / SC
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*
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* And since SC is a constant power of two, we can convert the div
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* into a shift.
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*
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* We can use khz divisor instead of mhz to keep a better precision, since
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* cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
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* (mathieu.desnoyers@polymtl.ca)
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*
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* -johnstul@us.ibm.com "math is hard, lets go shopping!"
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*/
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static unsigned long cyc2ns_scale;
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#define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
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@ -82,8 +106,9 @@ static void bfin_timer_set_mode(enum clock_event_mode mode,
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{
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC: {
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unsigned long tcount = ((get_cclk() / (HZ * 1)) - 1);
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unsigned long tcount = ((get_cclk() / (HZ * TIME_SCALE)) - 1);
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bfin_write_TCNTL(TMPWR);
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bfin_write_TSCALE(TIME_SCALE - 1);
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CSYNC();
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bfin_write_TPERIOD(tcount);
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bfin_write_TCOUNT(tcount);
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@ -92,6 +117,7 @@ static void bfin_timer_set_mode(enum clock_event_mode mode,
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break;
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}
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case CLOCK_EVT_MODE_ONESHOT:
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bfin_write_TSCALE(0);
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bfin_write_TCOUNT(0);
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bfin_write_TCNTL(TMPWR | TMREN);
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CSYNC();
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@ -115,7 +141,7 @@ static void __init bfin_timer_init(void)
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/*
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* the TSCALE prescaler counter.
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*/
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bfin_write_TSCALE(0);
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bfin_write_TSCALE(TIME_SCALE - 1);
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bfin_write_TPERIOD(0);
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bfin_write_TCOUNT(0);
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@ -6,9 +6,10 @@
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* Created:
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* Description: This file contains the bfin-specific time handling details.
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* Most of the stuff is located in the machine specific files.
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* FIXME: (This file is subject for removal)
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*
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* Modified:
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* Copyright 2004-2006 Analog Devices Inc.
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* Copyright 2004-2008 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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@ -35,6 +36,7 @@
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#include <linux/irq.h>
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#include <asm/blackfin.h>
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#include <asm/time.h>
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/* This is an NTP setting */
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#define TICK_SIZE (tick_nsec / 1000)
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@ -47,21 +49,6 @@ static struct irqaction bfin_timer_irq = {
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.flags = IRQF_DISABLED
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};
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/*
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* The way that the Blackfin core timer works is:
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* - CCLK is divided by a programmable 8-bit pre-scaler (TSCALE)
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* - Every time TSCALE ticks, a 32bit is counted down (TCOUNT)
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*
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* If you take the fastest clock (1ns, or 1GHz to make the math work easier)
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* 10ms is 10,000,000 clock ticks, which fits easy into a 32-bit counter
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* (32 bit counter is 4,294,967,296ns or 4.2 seconds) so, we don't need
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* to use TSCALE, and program it to zero (which is pass CCLK through).
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* If you feel like using it, try to keep HZ * TIMESCALE to some
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* value that divides easy (like power of 2).
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*/
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#define TIME_SCALE 1
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static void
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time_sched_init(irq_handler_t timer_routine)
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{
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@ -7,3 +7,4 @@ obj-y := \
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interrupt.o lock.o irqpanic.o arch_checks.o ints-priority.o
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obj-$(CONFIG_PM) += pm.o dpmc.o
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obj-$(CONFIG_CPU_FREQ) += cpufreq.o
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@ -0,0 +1,194 @@
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/*
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* File: arch/blackfin/mach-common/cpufreq.c
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* Based on:
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* Author:
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*
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* Created:
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* Description: Blackfin core clock scaling
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*
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* Modified:
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* Copyright 2004-2008 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/cpufreq.h>
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#include <linux/fs.h>
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#include <asm/blackfin.h>
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#include <asm/time.h>
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/* this is the table of CCLK frequencies, in Hz */
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/* .index is the entry in the auxillary dpm_state_table[] */
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static struct cpufreq_frequency_table bfin_freq_table[] = {
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{
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.frequency = CPUFREQ_TABLE_END,
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.index = 0,
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},
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{
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.frequency = CPUFREQ_TABLE_END,
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.index = 1,
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},
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{
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.frequency = CPUFREQ_TABLE_END,
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.index = 2,
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},
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{
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.frequency = CPUFREQ_TABLE_END,
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.index = 0,
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},
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};
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static struct bfin_dpm_state {
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unsigned int csel; /* system clock divider */
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unsigned int tscale; /* change the divider on the core timer interrupt */
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} dpm_state_table[3];
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/**************************************************************************/
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static unsigned int bfin_getfreq(unsigned int cpu)
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{
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/* The driver only support single cpu */
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if (cpu != 0)
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return -1;
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return get_cclk();
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}
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static int bfin_target(struct cpufreq_policy *policy,
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unsigned int target_freq, unsigned int relation)
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{
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unsigned int index, plldiv, tscale;
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unsigned long flags, cclk_hz;
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struct cpufreq_freqs freqs;
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if (cpufreq_frequency_table_target(policy, bfin_freq_table,
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target_freq, relation, &index))
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return -EINVAL;
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cclk_hz = bfin_freq_table[index].frequency;
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freqs.old = bfin_getfreq(0);
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freqs.new = cclk_hz;
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freqs.cpu = 0;
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pr_debug("cpufreq: changing cclk to %lu; target = %u, oldfreq = %u\n",
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cclk_hz, target_freq, freqs.old);
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cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
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local_irq_save(flags);
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plldiv = (bfin_read_PLL_DIV() & SSEL) | dpm_state_table[index].csel;
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tscale = dpm_state_table[index].tscale;
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bfin_write_PLL_DIV(plldiv);
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/* we have to adjust the core timer, because it is using cclk */
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bfin_write_TSCALE(tscale);
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SSYNC();
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local_irq_restore(flags);
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cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
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return 0;
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}
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static int bfin_verify_speed(struct cpufreq_policy *policy)
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{
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return cpufreq_frequency_table_verify(policy, bfin_freq_table);
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}
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static int __init __bfin_cpu_init(struct cpufreq_policy *policy)
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{
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unsigned long cclk, sclk, csel, min_cclk;
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int index;
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#ifdef CONFIG_CYCLES_CLOCKSOURCE
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/*
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* Clocksource CYCLES is still CONTINUOUS but not longer MONOTONIC in case we enable
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* CPU frequency scaling, since CYCLES runs off Core Clock.
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*/
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printk(KERN_WARNING "CPU frequency scaling not supported: Clocksource not suitable\n"
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return -ENODEV;
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#endif
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if (policy->cpu != 0)
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return -EINVAL;
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cclk = get_cclk();
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sclk = get_sclk();
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#if ANOMALY_05000273
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min_cclk = sclk * 2;
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#else
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min_cclk = sclk;
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#endif
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csel = ((bfin_read_PLL_DIV() & CSEL) >> 4);
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for (index = 0; (cclk >> index) >= min_cclk && csel <= 3; index++, csel++) {
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bfin_freq_table[index].frequency = cclk >> index;
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dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */
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dpm_state_table[index].tscale = (TIME_SCALE / (1 << csel)) - 1;
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pr_debug("cpufreq: freq:%d csel:%d tscale:%d\n",
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bfin_freq_table[index].frequency,
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dpm_state_table[index].csel,
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dpm_state_table[index].tscale);
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}
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policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
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policy->cpuinfo.transition_latency = (bfin_read_PLL_LOCKCNT() / (sclk / 1000000)) * 1000;
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/*Now ,only support one cpu */
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policy->cur = cclk;
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cpufreq_frequency_table_get_attr(bfin_freq_table, policy->cpu);
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return cpufreq_frequency_table_cpuinfo(policy, bfin_freq_table);
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}
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static struct freq_attr *bfin_freq_attr[] = {
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&cpufreq_freq_attr_scaling_available_freqs,
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NULL,
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};
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static struct cpufreq_driver bfin_driver = {
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.verify = bfin_verify_speed,
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.target = bfin_target,
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.get = bfin_getfreq,
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.init = __bfin_cpu_init,
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.name = "bfin cpufreq",
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.owner = THIS_MODULE,
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.attr = bfin_freq_attr,
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};
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static int __init bfin_cpu_init(void)
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{
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return cpufreq_register_driver(&bfin_driver);
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}
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static void __exit bfin_cpu_exit(void)
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{
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cpufreq_unregister_driver(&bfin_driver);
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}
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MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
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MODULE_DESCRIPTION("cpufreq driver for Blackfin");
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MODULE_LICENSE("GPL");
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module_init(bfin_cpu_init);
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module_exit(bfin_cpu_exit);
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@ -0,0 +1,36 @@
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/*
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* asm-blackfin/time.h:
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*
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* Copyright 2004-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#ifndef _ASM_BLACKFIN_TIME_H
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#define _ASM_BLACKFIN_TIME_H
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/*
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* The way that the Blackfin core timer works is:
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* - CCLK is divided by a programmable 8-bit pre-scaler (TSCALE)
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* - Every time TSCALE ticks, a 32bit is counted down (TCOUNT)
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*
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* If you take the fastest clock (1ns, or 1GHz to make the math work easier)
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* 10ms is 10,000,000 clock ticks, which fits easy into a 32-bit counter
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* (32 bit counter is 4,294,967,296ns or 4.2 seconds) so, we don't need
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* to use TSCALE, and program it to zero (which is pass CCLK through).
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* If you feel like using it, try to keep HZ * TIMESCALE to some
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* value that divides easy (like power of 2).
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*/
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#ifndef CONFIG_CPU_FREQ
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#define TIME_SCALE 1
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#else
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/*
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* Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 .
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* Whenever we change the Core Clock frequency changes we immediately
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* adjust the Core Timer Presale Register. This way we don't lose time.
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*/
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#define TIME_SCALE 4
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#endif
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#endif
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