OMAP: DSS2: DISPC: remove finegrained clk enables/disables
dispc.c enables and disables clocks in almost every function to make sure the clocks are enabled when the function is called. This is rather unoptimal way to handle the problem. With pm_runtime other components have to call dispc_runtime_get() to enable dispc clocks before calling any other dispc functions. Thus the finegrained clk enables/disables can be removed. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
Tomi Valkeinen
Родитель
aea4eb9590
Коммит
e6d80f950a
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@ -610,8 +610,6 @@ void dispc_go(enum omap_channel channel)
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int bit;
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bool enable_bit, go_bit;
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dispc_runtime_get();
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if (channel == OMAP_DSS_CHANNEL_LCD ||
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channel == OMAP_DSS_CHANNEL_LCD2)
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bit = 0; /* LCDENABLE */
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@ -625,7 +623,7 @@ void dispc_go(enum omap_channel channel)
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enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
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if (!enable_bit)
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goto end;
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return;
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if (channel == OMAP_DSS_CHANNEL_LCD ||
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channel == OMAP_DSS_CHANNEL_LCD2)
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@ -640,7 +638,7 @@ void dispc_go(enum omap_channel channel)
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if (go_bit) {
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DSSERR("GO bit not down for channel %d\n", channel);
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goto end;
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return;
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}
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DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
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@ -650,8 +648,6 @@ void dispc_go(enum omap_channel channel)
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REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
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else
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REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
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end:
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dispc_runtime_put();
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}
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static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
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@ -1025,7 +1021,7 @@ static void _dispc_set_color_mode(enum omap_plane plane,
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REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
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}
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static void _dispc_set_channel_out(enum omap_plane plane,
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void dispc_set_channel_out(enum omap_plane plane,
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enum omap_channel channel)
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{
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int shift;
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@ -1077,8 +1073,6 @@ static void dispc_set_burst_size(enum omap_plane plane,
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{
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int shift;
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dispc_runtime_get();
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switch (plane) {
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case OMAP_DSS_GFX:
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shift = 6;
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@ -1093,8 +1087,6 @@ static void dispc_set_burst_size(enum omap_plane plane,
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}
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REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
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dispc_runtime_put();
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}
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static void dispc_configure_burst_sizes(void)
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@ -1182,9 +1174,7 @@ void dispc_enable_replication(enum omap_plane plane, bool enable)
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else
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bit = 10;
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dispc_runtime_get();
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REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
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dispc_runtime_put();
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}
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void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
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@ -1192,9 +1182,7 @@ void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
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u32 val;
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BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
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val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
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dispc_runtime_get();
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dispc_write_reg(DISPC_SIZE_MGR(channel), val);
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dispc_runtime_put();
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}
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void dispc_set_digit_size(u16 width, u16 height)
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@ -1202,9 +1190,7 @@ void dispc_set_digit_size(u16 width, u16 height)
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u32 val;
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BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
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val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
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dispc_runtime_get();
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dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val);
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dispc_runtime_put();
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}
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static void dispc_read_plane_fifo_sizes(void)
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@ -1216,8 +1202,6 @@ static void dispc_read_plane_fifo_sizes(void)
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unit = dss_feat_get_buffer_size_unit();
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dispc_runtime_get();
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dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
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for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
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@ -1225,8 +1209,6 @@ static void dispc_read_plane_fifo_sizes(void)
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size *= unit;
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dispc.fifo_size[plane] = size;
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}
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dispc_runtime_put();
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}
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u32 dispc_get_plane_fifo_size(enum omap_plane plane)
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@ -1250,8 +1232,6 @@ void dispc_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
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dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
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dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
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dispc_runtime_get();
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DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
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plane,
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REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
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@ -1263,18 +1243,12 @@ void dispc_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
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dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
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FLD_VAL(high, hi_start, hi_end) |
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FLD_VAL(low, lo_start, lo_end));
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dispc_runtime_put();
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}
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void dispc_enable_fifomerge(bool enable)
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{
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dispc_runtime_get();
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DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
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REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
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dispc_runtime_put();
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}
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static void _dispc_set_fir(enum omap_plane plane,
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@ -1894,14 +1868,7 @@ static unsigned long calc_fclk(enum omap_channel channel, u16 width,
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return dispc_pclk_rate(channel) * vf * hf;
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}
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void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out)
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{
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dispc_runtime_get();
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_dispc_set_channel_out(plane, channel_out);
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dispc_runtime_put();
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}
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static int _dispc_setup_plane(enum omap_plane plane,
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int dispc_setup_plane(enum omap_plane plane,
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u32 paddr, u16 screen_width,
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u16 pos_x, u16 pos_y,
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u16 width, u16 height,
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@ -1909,7 +1876,7 @@ static int _dispc_setup_plane(enum omap_plane plane,
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enum omap_color_mode color_mode,
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bool ilace,
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enum omap_dss_rotation_type rotation_type,
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u8 rotation, int mirror,
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u8 rotation, bool mirror,
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u8 global_alpha, u8 pre_mult_alpha,
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enum omap_channel channel, u32 puv_addr)
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{
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@ -1923,6 +1890,14 @@ static int _dispc_setup_plane(enum omap_plane plane,
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u16 frame_height = height;
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unsigned int field_offset = 0;
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DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
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"%dx%d, ilace %d, cmode %x, rot %d, mir %d chan %d\n",
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plane, paddr, screen_width, pos_x, pos_y,
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width, height,
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out_width, out_height,
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ilace, color_mode,
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rotation, mirror, channel);
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if (paddr == 0)
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return -EINVAL;
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@ -2068,9 +2043,13 @@ static int _dispc_setup_plane(enum omap_plane plane,
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return 0;
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}
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static void _dispc_enable_plane(enum omap_plane plane, bool enable)
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int dispc_enable_plane(enum omap_plane plane, bool enable)
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{
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DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
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REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
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return 0;
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}
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static void dispc_disable_isr(void *data, u32 mask)
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@ -2094,8 +2073,6 @@ static void dispc_enable_lcd_out(enum omap_channel channel, bool enable)
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int r;
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u32 irq;
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dispc_runtime_get();
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/* When we disable LCD output, we need to wait until frame is done.
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* Otherwise the DSS is still working, and turning off the clocks
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* prevents DSS from going to OFF mode */
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@ -2129,8 +2106,6 @@ static void dispc_enable_lcd_out(enum omap_channel channel, bool enable)
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if (r)
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DSSERR("failed to unregister FRAMEDONE isr\n");
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}
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dispc_runtime_put();
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}
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static void _enable_digit_out(bool enable)
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@ -2143,12 +2118,8 @@ static void dispc_enable_digit_out(bool enable)
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struct completion frame_done_completion;
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int r;
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dispc_runtime_get();
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if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
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dispc_runtime_put();
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if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
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return;
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}
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if (enable) {
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unsigned long flags;
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@ -2200,8 +2171,6 @@ static void dispc_enable_digit_out(bool enable)
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_omap_dispc_set_irqs();
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spin_unlock_irqrestore(&dispc.irq_lock, flags);
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}
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dispc_runtime_put();
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}
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bool dispc_is_channel_enabled(enum omap_channel channel)
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@ -2232,9 +2201,7 @@ void dispc_lcd_enable_signal_polarity(bool act_high)
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if (!dss_has_feature(FEAT_LCDENABLEPOL))
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return;
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dispc_runtime_get();
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REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
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dispc_runtime_put();
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}
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void dispc_lcd_enable_signal(bool enable)
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@ -2242,9 +2209,7 @@ void dispc_lcd_enable_signal(bool enable)
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if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
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return;
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dispc_runtime_get();
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REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
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dispc_runtime_put();
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}
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void dispc_pck_free_enable(bool enable)
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@ -2252,19 +2217,15 @@ void dispc_pck_free_enable(bool enable)
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if (!dss_has_feature(FEAT_PCKFREEENABLE))
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return;
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dispc_runtime_get();
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REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
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dispc_runtime_put();
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}
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void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable)
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{
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dispc_runtime_get();
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if (channel == OMAP_DSS_CHANNEL_LCD2)
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REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
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else
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REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
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dispc_runtime_put();
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}
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@ -2287,27 +2248,21 @@ void dispc_set_lcd_display_type(enum omap_channel channel,
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return;
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}
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dispc_runtime_get();
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if (channel == OMAP_DSS_CHANNEL_LCD2)
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REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
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else
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REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
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dispc_runtime_put();
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}
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void dispc_set_loadmode(enum omap_dss_load_mode mode)
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{
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dispc_runtime_get();
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REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
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dispc_runtime_put();
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}
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void dispc_set_default_color(enum omap_channel channel, u32 color)
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{
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dispc_runtime_get();
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dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
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dispc_runtime_put();
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}
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u32 dispc_get_default_color(enum omap_channel channel)
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@ -2318,9 +2273,7 @@ u32 dispc_get_default_color(enum omap_channel channel)
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channel != OMAP_DSS_CHANNEL_LCD &&
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channel != OMAP_DSS_CHANNEL_LCD2);
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dispc_runtime_get();
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l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
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dispc_runtime_put();
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return l;
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}
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@ -2329,7 +2282,6 @@ void dispc_set_trans_key(enum omap_channel ch,
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enum omap_dss_trans_key_type type,
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u32 trans_key)
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{
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dispc_runtime_get();
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if (ch == OMAP_DSS_CHANNEL_LCD)
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REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
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else if (ch == OMAP_DSS_CHANNEL_DIGIT)
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@ -2338,14 +2290,12 @@ void dispc_set_trans_key(enum omap_channel ch,
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REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
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dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
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dispc_runtime_put();
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}
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void dispc_get_trans_key(enum omap_channel ch,
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enum omap_dss_trans_key_type *type,
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u32 *trans_key)
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{
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dispc_runtime_get();
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if (type) {
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if (ch == OMAP_DSS_CHANNEL_LCD)
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*type = REG_GET(DISPC_CONFIG, 11, 11);
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@ -2359,33 +2309,28 @@ void dispc_get_trans_key(enum omap_channel ch,
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if (trans_key)
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*trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
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dispc_runtime_put();
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}
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void dispc_enable_trans_key(enum omap_channel ch, bool enable)
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{
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dispc_runtime_get();
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if (ch == OMAP_DSS_CHANNEL_LCD)
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REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
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else if (ch == OMAP_DSS_CHANNEL_DIGIT)
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REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
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else /* OMAP_DSS_CHANNEL_LCD2 */
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REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
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dispc_runtime_put();
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}
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void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
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{
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if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
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return;
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dispc_runtime_get();
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if (ch == OMAP_DSS_CHANNEL_LCD)
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REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
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else if (ch == OMAP_DSS_CHANNEL_DIGIT)
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REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
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else /* OMAP_DSS_CHANNEL_LCD2 */
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REG_FLD_MOD(DISPC_CONFIG2, enable, 18, 18);
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dispc_runtime_put();
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}
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bool dispc_alpha_blending_enabled(enum omap_channel ch)
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{
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@ -2394,7 +2339,6 @@ bool dispc_alpha_blending_enabled(enum omap_channel ch)
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if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
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return false;
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dispc_runtime_get();
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if (ch == OMAP_DSS_CHANNEL_LCD)
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enabled = REG_GET(DISPC_CONFIG, 18, 18);
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else if (ch == OMAP_DSS_CHANNEL_DIGIT)
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@ -2403,7 +2347,6 @@ bool dispc_alpha_blending_enabled(enum omap_channel ch)
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enabled = REG_GET(DISPC_CONFIG2, 18, 18);
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else
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BUG();
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dispc_runtime_put();
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return enabled;
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}
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@ -2413,7 +2356,6 @@ bool dispc_trans_key_enabled(enum omap_channel ch)
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{
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bool enabled;
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dispc_runtime_get();
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if (ch == OMAP_DSS_CHANNEL_LCD)
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enabled = REG_GET(DISPC_CONFIG, 10, 10);
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else if (ch == OMAP_DSS_CHANNEL_DIGIT)
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@ -2422,7 +2364,6 @@ bool dispc_trans_key_enabled(enum omap_channel ch)
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enabled = REG_GET(DISPC_CONFIG2, 10, 10);
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else
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BUG();
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dispc_runtime_put();
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return enabled;
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}
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@ -2450,12 +2391,10 @@ void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
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return;
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}
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dispc_runtime_get();
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if (channel == OMAP_DSS_CHANNEL_LCD2)
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REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
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else
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REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
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dispc_runtime_put();
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}
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void dispc_set_parallel_interface_mode(enum omap_channel channel,
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@ -2487,8 +2426,6 @@ void dispc_set_parallel_interface_mode(enum omap_channel channel,
|
|||
return;
|
||||
}
|
||||
|
||||
dispc_runtime_get();
|
||||
|
||||
if (channel == OMAP_DSS_CHANNEL_LCD2) {
|
||||
l = dispc_read_reg(DISPC_CONTROL2);
|
||||
l = FLD_MOD(l, stallmode, 11, 11);
|
||||
|
|
@ -2500,8 +2437,6 @@ void dispc_set_parallel_interface_mode(enum omap_channel channel,
|
|||
l = FLD_MOD(l, gpout1, 16, 16);
|
||||
dispc_write_reg(DISPC_CONTROL, l);
|
||||
}
|
||||
|
||||
dispc_runtime_put();
|
||||
}
|
||||
|
||||
static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
|
||||
|
|
@ -2554,10 +2489,8 @@ static void _dispc_set_lcd_timings(enum omap_channel channel, int hsw,
|
|||
FLD_VAL(vbp, 31, 20);
|
||||
}
|
||||
|
||||
dispc_runtime_get();
|
||||
dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
|
||||
dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
|
||||
dispc_runtime_put();
|
||||
}
|
||||
|
||||
/* change name to mode? */
|
||||
|
|
@ -2600,10 +2533,8 @@ static void dispc_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
|
|||
BUG_ON(lck_div < 1);
|
||||
BUG_ON(pck_div < 2);
|
||||
|
||||
dispc_runtime_get();
|
||||
dispc_write_reg(DISPC_DIVISORo(channel),
|
||||
FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
|
||||
dispc_runtime_put();
|
||||
}
|
||||
|
||||
static void dispc_get_lcd_divisor(enum omap_channel channel, int *lck_div,
|
||||
|
|
@ -3063,9 +2994,7 @@ static void _dispc_set_pol_freq(enum omap_channel channel, bool onoff, bool rf,
|
|||
l |= FLD_VAL(acbi, 11, 8);
|
||||
l |= FLD_VAL(acb, 7, 0);
|
||||
|
||||
dispc_runtime_get();
|
||||
dispc_write_reg(DISPC_POL_FREQ(channel), l);
|
||||
dispc_runtime_put();
|
||||
}
|
||||
|
||||
void dispc_set_pol_freq(enum omap_channel channel,
|
||||
|
|
@ -3186,15 +3115,11 @@ static void _omap_dispc_set_irqs(void)
|
|||
mask |= isr_data->mask;
|
||||
}
|
||||
|
||||
dispc_runtime_get();
|
||||
|
||||
old_mask = dispc_read_reg(DISPC_IRQENABLE);
|
||||
/* clear the irqstatus for newly enabled irqs */
|
||||
dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
|
||||
|
||||
dispc_write_reg(DISPC_IRQENABLE, mask);
|
||||
|
||||
dispc_runtime_put();
|
||||
}
|
||||
|
||||
int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
|
||||
|
|
@ -3730,58 +3655,6 @@ static void _omap_dispc_initial_config(void)
|
|||
dispc_configure_burst_sizes();
|
||||
}
|
||||
|
||||
int dispc_enable_plane(enum omap_plane plane, bool enable)
|
||||
{
|
||||
DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
|
||||
|
||||
dispc_runtime_get();
|
||||
_dispc_enable_plane(plane, enable);
|
||||
dispc_runtime_put();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dispc_setup_plane(enum omap_plane plane,
|
||||
u32 paddr, u16 screen_width,
|
||||
u16 pos_x, u16 pos_y,
|
||||
u16 width, u16 height,
|
||||
u16 out_width, u16 out_height,
|
||||
enum omap_color_mode color_mode,
|
||||
bool ilace,
|
||||
enum omap_dss_rotation_type rotation_type,
|
||||
u8 rotation, bool mirror, u8 global_alpha,
|
||||
u8 pre_mult_alpha, enum omap_channel channel,
|
||||
u32 puv_addr)
|
||||
{
|
||||
int r = 0;
|
||||
|
||||
DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d, %d, %dx%d -> "
|
||||
"%dx%d, ilace %d, cmode %x, rot %d, mir %d chan %d\n",
|
||||
plane, paddr, screen_width, pos_x, pos_y,
|
||||
width, height,
|
||||
out_width, out_height,
|
||||
ilace, color_mode,
|
||||
rotation, mirror, channel);
|
||||
|
||||
dispc_runtime_get();
|
||||
|
||||
r = _dispc_setup_plane(plane,
|
||||
paddr, screen_width,
|
||||
pos_x, pos_y,
|
||||
width, height,
|
||||
out_width, out_height,
|
||||
color_mode, ilace,
|
||||
rotation_type,
|
||||
rotation, mirror,
|
||||
global_alpha,
|
||||
pre_mult_alpha,
|
||||
channel, puv_addr);
|
||||
|
||||
dispc_runtime_put();
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
/* DISPC HW IP initialisation */
|
||||
static int omap_dispchw_probe(struct platform_device *pdev)
|
||||
{
|
||||
|
|
|
|||
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