RDMA/rtrs-srv: Fix stack-out-of-bounds
BUG: KASAN: stack-out-of-bounds in _mlx4_ib_post_send+0x1bd2/0x2770 [mlx4_ib]
Read of size 4 at addr ffff8880d5a7f980 by task kworker/0:1H/565
CPU: 0 PID: 565 Comm: kworker/0:1H Tainted: G O 5.4.84-storage #5.4.84-1+feature+linux+5.4.y+dbg+20201216.1319+b6b887b~deb10
Hardware name: Supermicro H8QG6/H8QG6, BIOS 3.00 09/04/2012
Workqueue: ib-comp-wq ib_cq_poll_work [ib_core]
Call Trace:
dump_stack+0x96/0xe0
print_address_description.constprop.4+0x1f/0x300
? irq_work_claim+0x2e/0x50
__kasan_report.cold.8+0x78/0x92
? _mlx4_ib_post_send+0x1bd2/0x2770 [mlx4_ib]
kasan_report+0x10/0x20
_mlx4_ib_post_send+0x1bd2/0x2770 [mlx4_ib]
? check_chain_key+0x1d7/0x2e0
? _mlx4_ib_post_recv+0x630/0x630 [mlx4_ib]
? lockdep_hardirqs_on+0x1a8/0x290
? stack_depot_save+0x218/0x56e
? do_profile_hits.isra.6.cold.13+0x1d/0x1d
? check_chain_key+0x1d7/0x2e0
? save_stack+0x4d/0x80
? save_stack+0x19/0x80
? __kasan_slab_free+0x125/0x170
? kfree+0xe7/0x3b0
rdma_write_sg+0x5b0/0x950 [rtrs_server]
The problem is when we send imm_wr, the type should be ib_rdma_wr, so hw
driver like mlx4 can do rdma_wr(wr), so fix it by use the ib_rdma_wr as
type for imm_wr.
Fixes: 9cb8374804
("RDMA/rtrs: server: main functionality")
Link: https://lore.kernel.org/r/20210212134525.103456-2-jinpu.wang@cloud.ionos.com
Signed-off-by: Jack Wang <jinpu.wang@cloud.ionos.com>
Reviewed-by: Gioh Kim <gi-oh.kim@cloud.ionos.com>
Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
This commit is contained in:
Родитель
bf139b58af
Коммит
e6daa8f61d
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@ -222,7 +222,8 @@ static int rdma_write_sg(struct rtrs_srv_op *id)
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dma_addr_t dma_addr = sess->dma_addr[id->msg_id];
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struct rtrs_srv_mr *srv_mr;
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struct rtrs_srv *srv = sess->srv;
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struct ib_send_wr inv_wr, imm_wr;
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struct ib_send_wr inv_wr;
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struct ib_rdma_wr imm_wr;
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struct ib_rdma_wr *wr = NULL;
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enum ib_send_flags flags;
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size_t sg_cnt;
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@ -274,15 +275,15 @@ static int rdma_write_sg(struct rtrs_srv_op *id)
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if (need_inval && always_invalidate) {
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wr->wr.next = &rwr.wr;
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rwr.wr.next = &inv_wr;
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inv_wr.next = &imm_wr;
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inv_wr.next = &imm_wr.wr;
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} else if (always_invalidate) {
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wr->wr.next = &rwr.wr;
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rwr.wr.next = &imm_wr;
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rwr.wr.next = &imm_wr.wr;
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} else if (need_inval) {
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wr->wr.next = &inv_wr;
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inv_wr.next = &imm_wr;
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inv_wr.next = &imm_wr.wr;
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} else {
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wr->wr.next = &imm_wr;
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wr->wr.next = &imm_wr.wr;
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}
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/*
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* From time to time we have to post signaled sends,
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@ -300,7 +301,7 @@ static int rdma_write_sg(struct rtrs_srv_op *id)
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inv_wr.ex.invalidate_rkey = rkey;
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}
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imm_wr.next = NULL;
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imm_wr.wr.next = NULL;
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if (always_invalidate) {
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struct rtrs_msg_rkey_rsp *msg;
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@ -321,22 +322,22 @@ static int rdma_write_sg(struct rtrs_srv_op *id)
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list.addr = srv_mr->iu->dma_addr;
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list.length = sizeof(*msg);
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list.lkey = sess->s.dev->ib_pd->local_dma_lkey;
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imm_wr.sg_list = &list;
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imm_wr.num_sge = 1;
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imm_wr.opcode = IB_WR_SEND_WITH_IMM;
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imm_wr.wr.sg_list = &list;
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imm_wr.wr.num_sge = 1;
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imm_wr.wr.opcode = IB_WR_SEND_WITH_IMM;
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ib_dma_sync_single_for_device(sess->s.dev->ib_dev,
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srv_mr->iu->dma_addr,
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srv_mr->iu->size, DMA_TO_DEVICE);
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} else {
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imm_wr.sg_list = NULL;
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imm_wr.num_sge = 0;
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imm_wr.opcode = IB_WR_RDMA_WRITE_WITH_IMM;
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imm_wr.wr.sg_list = NULL;
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imm_wr.wr.num_sge = 0;
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imm_wr.wr.opcode = IB_WR_RDMA_WRITE_WITH_IMM;
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}
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imm_wr.send_flags = flags;
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imm_wr.ex.imm_data = cpu_to_be32(rtrs_to_io_rsp_imm(id->msg_id,
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imm_wr.wr.send_flags = flags;
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imm_wr.wr.ex.imm_data = cpu_to_be32(rtrs_to_io_rsp_imm(id->msg_id,
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0, need_inval));
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imm_wr.wr_cqe = &io_comp_cqe;
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imm_wr.wr.wr_cqe = &io_comp_cqe;
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ib_dma_sync_single_for_device(sess->s.dev->ib_dev, dma_addr,
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offset, DMA_BIDIRECTIONAL);
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@ -363,7 +364,8 @@ static int send_io_resp_imm(struct rtrs_srv_con *con, struct rtrs_srv_op *id,
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{
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struct rtrs_sess *s = con->c.sess;
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struct rtrs_srv_sess *sess = to_srv_sess(s);
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struct ib_send_wr inv_wr, imm_wr, *wr = NULL;
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struct ib_send_wr inv_wr, *wr = NULL;
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struct ib_rdma_wr imm_wr;
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struct ib_reg_wr rwr;
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struct rtrs_srv *srv = sess->srv;
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struct rtrs_srv_mr *srv_mr;
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@ -400,15 +402,15 @@ static int send_io_resp_imm(struct rtrs_srv_con *con, struct rtrs_srv_op *id,
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if (need_inval && always_invalidate) {
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wr = &inv_wr;
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inv_wr.next = &rwr.wr;
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rwr.wr.next = &imm_wr;
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rwr.wr.next = &imm_wr.wr;
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} else if (always_invalidate) {
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wr = &rwr.wr;
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rwr.wr.next = &imm_wr;
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rwr.wr.next = &imm_wr.wr;
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} else if (need_inval) {
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wr = &inv_wr;
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inv_wr.next = &imm_wr;
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inv_wr.next = &imm_wr.wr;
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} else {
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wr = &imm_wr;
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wr = &imm_wr.wr;
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}
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/*
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* From time to time we have to post signalled sends,
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@ -417,13 +419,13 @@ static int send_io_resp_imm(struct rtrs_srv_con *con, struct rtrs_srv_op *id,
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flags = (atomic_inc_return(&con->wr_cnt) % srv->queue_depth) ?
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0 : IB_SEND_SIGNALED;
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imm = rtrs_to_io_rsp_imm(id->msg_id, errno, need_inval);
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imm_wr.next = NULL;
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imm_wr.wr.next = NULL;
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if (always_invalidate) {
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struct ib_sge list;
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struct rtrs_msg_rkey_rsp *msg;
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srv_mr = &sess->mrs[id->msg_id];
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rwr.wr.next = &imm_wr;
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rwr.wr.next = &imm_wr.wr;
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rwr.wr.opcode = IB_WR_REG_MR;
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rwr.wr.wr_cqe = &local_reg_cqe;
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rwr.wr.num_sge = 0;
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@ -440,21 +442,21 @@ static int send_io_resp_imm(struct rtrs_srv_con *con, struct rtrs_srv_op *id,
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list.addr = srv_mr->iu->dma_addr;
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list.length = sizeof(*msg);
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list.lkey = sess->s.dev->ib_pd->local_dma_lkey;
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imm_wr.sg_list = &list;
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imm_wr.num_sge = 1;
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imm_wr.opcode = IB_WR_SEND_WITH_IMM;
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imm_wr.wr.sg_list = &list;
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imm_wr.wr.num_sge = 1;
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imm_wr.wr.opcode = IB_WR_SEND_WITH_IMM;
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ib_dma_sync_single_for_device(sess->s.dev->ib_dev,
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srv_mr->iu->dma_addr,
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srv_mr->iu->size, DMA_TO_DEVICE);
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} else {
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imm_wr.sg_list = NULL;
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imm_wr.num_sge = 0;
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imm_wr.opcode = IB_WR_RDMA_WRITE_WITH_IMM;
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imm_wr.wr.sg_list = NULL;
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imm_wr.wr.num_sge = 0;
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imm_wr.wr.opcode = IB_WR_RDMA_WRITE_WITH_IMM;
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}
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imm_wr.send_flags = flags;
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imm_wr.wr_cqe = &io_comp_cqe;
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imm_wr.wr.send_flags = flags;
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imm_wr.wr.wr_cqe = &io_comp_cqe;
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imm_wr.ex.imm_data = cpu_to_be32(imm);
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imm_wr.wr.ex.imm_data = cpu_to_be32(imm);
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err = ib_post_send(id->con->c.qp, wr, NULL);
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if (unlikely(err))
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