ARM: SoC fixes for 3.12-rc
We have a fairly large batch of fixes this time around, mostly just due to
various platforms all having a fix or two more than usual.
Worth pointing out are:
- A fix for EDMA on Davinci/OMAP where channel allocation broke with
the DT conversion. Due to some miscommunication we didn't
understand the impact of the breakage, so we were pushing back on it
for 3.12, but it sounds like it's actually breaking quite a few people
out there.
- A bunch of fixes for Marvell platforms, some straggling fixes for
merge window fallout and some fixes for a couple of the platforms
(Netgear RN102 in particular).
- A fix for a race between multi-cluster power management and cpu hotplug
on Versatile Express.
And a bunch of other smaller fixes that all add up.
We'll be switching over into stricter regressions-only mode from here
on out.
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Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"We have a fairly large batch of fixes this time around, mostly just
due to various platforms all having a fix or two more than usual.
Worth pointing out are:
- A fix for EDMA on Davinci/OMAP where channel allocation broke with
the DT conversion. Due to some miscommunication we didn't
understand the impact of the breakage, so we were pushing back on
it for 3.12, but it sounds like it's actually breaking quite a few
people out there.
- A bunch of fixes for Marvell platforms, some straggling fixes for
merge window fallout and some fixes for a couple of the platforms
(Netgear RN102 in particular).
- A fix for a race between multi-cluster power management and cpu
hotplug on Versatile Express.
And a bunch of other smaller fixes that all add up.
We'll be switching over into stricter regressions-only mode from here
on out"
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (31 commits)
ARM: multi_v7_defconfig: add SDHCI for i.MX
bus: mvebu-mbus: Fix optional pcie-mem/io-aperture properties
ARM: mvebu: add missing DT Mbus ranges and relocate PCIe DT nodes for RN102
ARM: at91: sam9g45: shutdown ddr1 too when rebooting
MAINTAINERS: ARM: SIRF: use kernel.org mail box
MAINTAINERS: ARM: SIRF: add missed drivers into maintain list
ARM: edma: Fix clearing of unused list for DT DMA resources
ARM: vexpress: tc2: fix hotplug/idle/kexec race on cluster power down
ARM: dts: sirf: fix interrupt and dma prop of VIP for prima2 and atlas6
ARM: dts: sirf: fix the ranges of peri-iobrg of prima2
ARM: dts: makefile: build atlas6-evb.dtb for ARCH_ATLAS6
ARM: dts: sirf: fix fifosize, clks, dma channels for UART
ARM: mvebu: Add DT entry for ReadyNAS 102 to use gpio-poweroff driver
ARM: mvebu: fix ReadyNAS 102 Power button GPIO to make it active high
ARM: mach-integrator: Add stub for pci_v3_early_init() for !CONFIG_PCI
ARM: shmobile: Remove #gpio-ranges-cells DT property
gpio: rcar: Remove #gpio-range-cells DT property usage
ARM: shmobile: armadillo: fixup ether pinctrl naming
ARM: shmobile: Lager: add Micrel KSZ8041 PHY fixup
ARM: shmobile: update SDHI DT compatibility string to the <unit>-<soc> format
...
This commit is contained in:
Linus Torvalds
Коммит
e6e7fb1ffc
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@ -9,12 +9,15 @@ compulsory and any optional properties, common to all SD/MMC drivers, as
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described in mmc.txt, can be used. Additionally the following tmio_mmc-specific
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optional bindings can be used.
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Required properties:
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- compatible: "renesas,sdhi-shmobile" - a generic sh-mobile SDHI unit
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"renesas,sdhi-sh7372" - SDHI IP on SH7372 SoC
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"renesas,sdhi-sh73a0" - SDHI IP on SH73A0 SoC
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"renesas,sdhi-r8a73a4" - SDHI IP on R8A73A4 SoC
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"renesas,sdhi-r8a7740" - SDHI IP on R8A7740 SoC
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"renesas,sdhi-r8a7778" - SDHI IP on R8A7778 SoC
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"renesas,sdhi-r8a7779" - SDHI IP on R8A7779 SoC
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"renesas,sdhi-r8a7790" - SDHI IP on R8A7790 SoC
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Optional properties:
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- toshiba,mmc-wrprotect-disable: write-protect detection is unavailable
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When used with Renesas SDHI hardware, the following compatibility strings
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configure various model-specific properties:
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"renesas,sh7372-sdhi": (default) compatible with SH7372
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"renesas,r8a7740-sdhi": compatible with R8A7740: certain MMC/SD commands have to
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wait for the interface to become idle.
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@ -824,15 +824,21 @@ S: Maintained
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F: arch/arm/mach-gemini/
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ARM/CSR SIRFPRIMA2 MACHINE SUPPORT
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M: Barry Song <baohua.song@csr.com>
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M: Barry Song <baohua@kernel.org>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux.git
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S: Maintained
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F: arch/arm/mach-prima2/
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F: drivers/clk/clk-prima2.c
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F: drivers/clocksource/timer-prima2.c
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F: drivers/clocksource/timer-marco.c
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F: drivers/dma/sirf-dma.c
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F: drivers/i2c/busses/i2c-sirf.c
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F: drivers/input/misc/sirfsoc-onkey.c
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F: drivers/irqchip/irq-sirfsoc.c
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F: drivers/mmc/host/sdhci-sirf.c
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F: drivers/pinctrl/sirf/
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F: drivers/rtc/rtc-sirfsoc.c
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F: drivers/spi/spi-sirf.c
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ARM/EBSA110 MACHINE SUPPORT
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@ -41,6 +41,8 @@ dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb
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dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb
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dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb
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dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
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dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
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dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb \
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bcm28155-ap.dtb
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@ -27,6 +27,25 @@
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
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MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
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pcie-controller {
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status = "okay";
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/* Connected to Marvell SATA controller */
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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/* Connected to FL1009 USB 3.0 controller */
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pcie@2,0 {
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/* Port 1, Lane 0 */
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status = "okay";
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};
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};
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internal-regs {
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serial@12000 {
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clock-frequency = <200000000>;
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@ -57,6 +76,11 @@
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marvell,pins = "mpp56";
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marvell,function = "gpio";
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};
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poweroff: poweroff {
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marvell,pins = "mpp8";
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marvell,function = "gpio";
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};
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};
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mdio {
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@ -89,22 +113,6 @@
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pwm_polarity = <0>;
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};
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};
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pcie-controller {
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status = "okay";
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/* Connected to Marvell SATA controller */
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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/* Connected to FL1009 USB 3.0 controller */
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pcie@2,0 {
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/* Port 1, Lane 0 */
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status = "okay";
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};
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};
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};
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};
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@ -160,7 +168,7 @@
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button@1 {
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label = "Power Button";
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linux,code = <116>; /* KEY_POWER */
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gpios = <&gpio1 30 1>;
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gpios = <&gpio1 30 0>;
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};
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button@2 {
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@ -176,4 +184,11 @@
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};
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};
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gpio_poweroff {
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compatible = "gpio-poweroff";
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pinctrl-0 = <&poweroff>;
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pinctrl-names = "default";
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gpios = <&gpio0 8 1>;
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};
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};
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@ -70,6 +70,8 @@
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timer@20300 {
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compatible = "marvell,armada-xp-timer";
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clocks = <&coreclk 2>, <&refclk>;
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clock-names = "nbclk", "fixed";
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};
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coreclk: mvebu-sar@18230 {
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@ -169,4 +171,13 @@
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};
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};
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};
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clocks {
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/* 25 MHz reference crystal */
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refclk: oscillator {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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};
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};
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@ -190,12 +190,12 @@
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AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA8 periph A */
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};
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pinctrl_uart2_rts: uart2_rts-0 {
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pinctrl_usart2_rts: usart2_rts-0 {
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atmel,pins =
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<AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
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};
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pinctrl_uart2_cts: uart2_cts-0 {
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pinctrl_usart2_cts: usart2_cts-0 {
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atmel,pins =
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<AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */
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};
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@ -556,6 +556,7 @@
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interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
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dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>;
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dma-names = "rxtx";
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pinctrl-names = "default";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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@ -567,6 +568,7 @@
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interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
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dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>;
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dma-names = "rxtx";
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pinctrl-names = "default";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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@ -181,6 +181,8 @@
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interrupts = <17>;
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fifosize = <128>;
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clocks = <&clks 13>;
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sirf,uart-dma-rx-channel = <21>;
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sirf,uart-dma-tx-channel = <2>;
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};
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uart1: uart@b0060000 {
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@ -199,6 +201,8 @@
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interrupts = <19>;
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fifosize = <128>;
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clocks = <&clks 15>;
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sirf,uart-dma-rx-channel = <6>;
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sirf,uart-dma-tx-channel = <7>;
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};
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usp0: usp@b0080000 {
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@ -206,7 +210,10 @@
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compatible = "sirf,prima2-usp";
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reg = <0xb0080000 0x10000>;
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interrupts = <20>;
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fifosize = <128>;
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clocks = <&clks 28>;
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sirf,usp-dma-rx-channel = <17>;
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sirf,usp-dma-tx-channel = <18>;
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};
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usp1: usp@b0090000 {
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@ -214,7 +221,10 @@
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compatible = "sirf,prima2-usp";
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reg = <0xb0090000 0x10000>;
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interrupts = <21>;
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fifosize = <128>;
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clocks = <&clks 29>;
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sirf,usp-dma-rx-channel = <14>;
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sirf,usp-dma-tx-channel = <15>;
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};
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dmac0: dma-controller@b00b0000 {
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@ -237,6 +247,8 @@
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compatible = "sirf,prima2-vip";
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reg = <0xb00C0000 0x10000>;
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clocks = <&clks 31>;
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interrupts = <14>;
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sirf,vip-dma-rx-channel = <16>;
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};
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spi0: spi@b00d0000 {
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@ -13,6 +13,7 @@
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cpu@0 {
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device_type = "cpu";
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compatible = "marvell,feroceon";
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reg = <0>;
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clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
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clock-names = "cpu_clk", "ddrclk", "powersave";
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};
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@ -167,7 +168,7 @@
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xor@60900 {
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compatible = "marvell,orion-xor";
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reg = <0x60900 0x100
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0xd0B00 0x100>;
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0x60B00 0x100>;
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status = "okay";
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clocks = <&gate_clk 16>;
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|
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@ -171,7 +171,8 @@
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0xb0000000 0xb0000000 0x180000>;
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ranges = <0xb0000000 0xb0000000 0x180000>,
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<0x56000000 0x56000000 0x1b00000>;
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timer@b0020000 {
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compatible = "sirf,prima2-tick";
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@ -196,25 +197,32 @@
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uart0: uart@b0050000 {
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cell-index = <0>;
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compatible = "sirf,prima2-uart";
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reg = <0xb0050000 0x10000>;
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reg = <0xb0050000 0x1000>;
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interrupts = <17>;
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fifosize = <128>;
|
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clocks = <&clks 13>;
|
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sirf,uart-dma-rx-channel = <21>;
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sirf,uart-dma-tx-channel = <2>;
|
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};
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uart1: uart@b0060000 {
|
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cell-index = <1>;
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compatible = "sirf,prima2-uart";
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reg = <0xb0060000 0x10000>;
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reg = <0xb0060000 0x1000>;
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interrupts = <18>;
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fifosize = <32>;
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clocks = <&clks 14>;
|
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};
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uart2: uart@b0070000 {
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cell-index = <2>;
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compatible = "sirf,prima2-uart";
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reg = <0xb0070000 0x10000>;
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reg = <0xb0070000 0x1000>;
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interrupts = <19>;
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fifosize = <128>;
|
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clocks = <&clks 15>;
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sirf,uart-dma-rx-channel = <6>;
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sirf,uart-dma-tx-channel = <7>;
|
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};
|
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|
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usp0: usp@b0080000 {
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|
|
@ -222,7 +230,10 @@
|
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compatible = "sirf,prima2-usp";
|
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reg = <0xb0080000 0x10000>;
|
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interrupts = <20>;
|
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fifosize = <128>;
|
||||
clocks = <&clks 28>;
|
||||
sirf,usp-dma-rx-channel = <17>;
|
||||
sirf,usp-dma-tx-channel = <18>;
|
||||
};
|
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|
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usp1: usp@b0090000 {
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||||
|
|
@ -230,7 +241,10 @@
|
|||
compatible = "sirf,prima2-usp";
|
||||
reg = <0xb0090000 0x10000>;
|
||||
interrupts = <21>;
|
||||
fifosize = <128>;
|
||||
clocks = <&clks 29>;
|
||||
sirf,usp-dma-rx-channel = <14>;
|
||||
sirf,usp-dma-tx-channel = <15>;
|
||||
};
|
||||
|
||||
usp2: usp@b00a0000 {
|
||||
|
|
@ -238,7 +252,10 @@
|
|||
compatible = "sirf,prima2-usp";
|
||||
reg = <0xb00a0000 0x10000>;
|
||||
interrupts = <22>;
|
||||
fifosize = <128>;
|
||||
clocks = <&clks 30>;
|
||||
sirf,usp-dma-rx-channel = <10>;
|
||||
sirf,usp-dma-tx-channel = <11>;
|
||||
};
|
||||
|
||||
dmac0: dma-controller@b00b0000 {
|
||||
|
|
@ -261,6 +278,8 @@
|
|||
compatible = "sirf,prima2-vip";
|
||||
reg = <0xb00C0000 0x10000>;
|
||||
clocks = <&clks 31>;
|
||||
interrupts = <14>;
|
||||
sirf,vip-dma-rx-channel = <16>;
|
||||
};
|
||||
|
||||
spi0: spi@b00d0000 {
|
||||
|
|
|
|||
|
|
@ -193,7 +193,7 @@
|
|||
};
|
||||
|
||||
sdhi0: sdhi@ee100000 {
|
||||
compatible = "renesas,r8a73a4-sdhi";
|
||||
compatible = "renesas,sdhi-r8a73a4";
|
||||
reg = <0 0xee100000 0 0x100>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 165 4>;
|
||||
|
|
@ -202,7 +202,7 @@
|
|||
};
|
||||
|
||||
sdhi1: sdhi@ee120000 {
|
||||
compatible = "renesas,r8a73a4-sdhi";
|
||||
compatible = "renesas,sdhi-r8a73a4";
|
||||
reg = <0 0xee120000 0 0x100>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 166 4>;
|
||||
|
|
@ -211,7 +211,7 @@
|
|||
};
|
||||
|
||||
sdhi2: sdhi@ee140000 {
|
||||
compatible = "renesas,r8a73a4-sdhi";
|
||||
compatible = "renesas,sdhi-r8a73a4";
|
||||
reg = <0 0xee140000 0 0x100>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 167 4>;
|
||||
|
|
|
|||
|
|
@ -96,6 +96,5 @@
|
|||
pfc: pfc@fffc0000 {
|
||||
compatible = "renesas,pfc-r8a7778";
|
||||
reg = <0xfffc000 0x118>;
|
||||
#gpio-range-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -188,7 +188,6 @@
|
|||
pfc: pfc@fffc0000 {
|
||||
compatible = "renesas,pfc-r8a7779";
|
||||
reg = <0xfffc0000 0x23c>;
|
||||
#gpio-range-cells = <3>;
|
||||
};
|
||||
|
||||
thermal@ffc48000 {
|
||||
|
|
|
|||
|
|
@ -148,11 +148,10 @@
|
|||
pfc: pfc@e6060000 {
|
||||
compatible = "renesas,pfc-r8a7790";
|
||||
reg = <0 0xe6060000 0 0x250>;
|
||||
#gpio-range-cells = <3>;
|
||||
};
|
||||
|
||||
sdhi0: sdhi@ee100000 {
|
||||
compatible = "renesas,r8a7790-sdhi";
|
||||
compatible = "renesas,sdhi-r8a7790";
|
||||
reg = <0 0xee100000 0 0x100>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 165 4>;
|
||||
|
|
@ -161,7 +160,7 @@
|
|||
};
|
||||
|
||||
sdhi1: sdhi@ee120000 {
|
||||
compatible = "renesas,r8a7790-sdhi";
|
||||
compatible = "renesas,sdhi-r8a7790";
|
||||
reg = <0 0xee120000 0 0x100>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 166 4>;
|
||||
|
|
@ -170,7 +169,7 @@
|
|||
};
|
||||
|
||||
sdhi2: sdhi@ee140000 {
|
||||
compatible = "renesas,r8a7790-sdhi";
|
||||
compatible = "renesas,sdhi-r8a7790";
|
||||
reg = <0 0xee140000 0 0x100>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 167 4>;
|
||||
|
|
@ -179,7 +178,7 @@
|
|||
};
|
||||
|
||||
sdhi3: sdhi@ee160000 {
|
||||
compatible = "renesas,r8a7790-sdhi";
|
||||
compatible = "renesas,sdhi-r8a7790";
|
||||
reg = <0 0xee160000 0 0x100>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 168 4>;
|
||||
|
|
|
|||
|
|
@ -196,7 +196,7 @@
|
|||
};
|
||||
|
||||
sdhi0: sdhi@ee100000 {
|
||||
compatible = "renesas,r8a7740-sdhi";
|
||||
compatible = "renesas,sdhi-r8a7740";
|
||||
reg = <0xee100000 0x100>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 83 4
|
||||
|
|
@ -208,7 +208,7 @@
|
|||
|
||||
/* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
|
||||
sdhi1: sdhi@ee120000 {
|
||||
compatible = "renesas,r8a7740-sdhi";
|
||||
compatible = "renesas,sdhi-r8a7740";
|
||||
reg = <0xee120000 0x100>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 88 4
|
||||
|
|
@ -219,7 +219,7 @@
|
|||
};
|
||||
|
||||
sdhi2: sdhi@ee140000 {
|
||||
compatible = "renesas,r8a7740-sdhi";
|
||||
compatible = "renesas,sdhi-r8a7740";
|
||||
reg = <0xee140000 0x100>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 104 4
|
||||
|
|
|
|||
|
|
@ -269,6 +269,11 @@ static const struct edmacc_param dummy_paramset = {
|
|||
.ccnt = 1,
|
||||
};
|
||||
|
||||
static const struct of_device_id edma_of_ids[] = {
|
||||
{ .compatible = "ti,edma3", },
|
||||
{}
|
||||
};
|
||||
|
||||
/*****************************************************************************/
|
||||
|
||||
static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
|
||||
|
|
@ -560,14 +565,38 @@ static int reserve_contiguous_slots(int ctlr, unsigned int id,
|
|||
static int prepare_unused_channel_list(struct device *dev, void *data)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
int i, ctlr;
|
||||
int i, count, ctlr;
|
||||
struct of_phandle_args dma_spec;
|
||||
|
||||
if (dev->of_node) {
|
||||
count = of_property_count_strings(dev->of_node, "dma-names");
|
||||
if (count < 0)
|
||||
return 0;
|
||||
for (i = 0; i < count; i++) {
|
||||
if (of_parse_phandle_with_args(dev->of_node, "dmas",
|
||||
"#dma-cells", i,
|
||||
&dma_spec))
|
||||
continue;
|
||||
|
||||
if (!of_match_node(edma_of_ids, dma_spec.np)) {
|
||||
of_node_put(dma_spec.np);
|
||||
continue;
|
||||
}
|
||||
|
||||
clear_bit(EDMA_CHAN_SLOT(dma_spec.args[0]),
|
||||
edma_cc[0]->edma_unused);
|
||||
of_node_put(dma_spec.np);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* For non-OF case */
|
||||
for (i = 0; i < pdev->num_resources; i++) {
|
||||
if ((pdev->resource[i].flags & IORESOURCE_DMA) &&
|
||||
(int)pdev->resource[i].start >= 0) {
|
||||
ctlr = EDMA_CTLR(pdev->resource[i].start);
|
||||
clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
|
||||
edma_cc[ctlr]->edma_unused);
|
||||
edma_cc[ctlr]->edma_unused);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1762,11 +1791,6 @@ static int edma_probe(struct platform_device *pdev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id edma_of_ids[] = {
|
||||
{ .compatible = "ti,edma3", },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver edma_driver = {
|
||||
.driver = {
|
||||
.name = "edma",
|
||||
|
|
|
|||
|
|
@ -135,6 +135,7 @@ CONFIG_MMC=y
|
|||
CONFIG_MMC_ARMMMCI=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
CONFIG_MMC_SDHCI_ESDHC_IMX=y
|
||||
CONFIG_MMC_SDHCI_TEGRA=y
|
||||
CONFIG_MMC_SDHCI_SPEAR=y
|
||||
CONFIG_MMC_OMAP=y
|
||||
|
|
|
|||
|
|
@ -93,7 +93,7 @@ static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
|
|||
|
||||
static struct irqaction at91rm9200_timer_irq = {
|
||||
.name = "at91_tick",
|
||||
.flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
|
||||
.flags = IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL,
|
||||
.handler = at91rm9200_timer_interrupt,
|
||||
.irq = NR_IRQS_LEGACY + AT91_ID_SYS,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -171,7 +171,7 @@ static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
|
|||
|
||||
static struct irqaction at91sam926x_pit_irq = {
|
||||
.name = "at91_tick",
|
||||
.flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
|
||||
.flags = IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL,
|
||||
.handler = at91sam926x_pit_interrupt,
|
||||
.irq = NR_IRQS_LEGACY + AT91_ID_SYS,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -16,11 +16,17 @@
|
|||
#include "at91_rstc.h"
|
||||
.arm
|
||||
|
||||
/*
|
||||
* at91_ramc_base is an array void*
|
||||
* init at NULL if only one DDR controler is present in or DT
|
||||
*/
|
||||
.globl at91sam9g45_restart
|
||||
|
||||
at91sam9g45_restart:
|
||||
ldr r5, =at91_ramc_base @ preload constants
|
||||
ldr r0, [r5]
|
||||
ldr r5, [r5, #4] @ ddr1
|
||||
cmp r5, #0
|
||||
ldr r4, =at91_rstc_base
|
||||
ldr r1, [r4]
|
||||
|
||||
|
|
@ -30,6 +36,8 @@ at91sam9g45_restart:
|
|||
|
||||
.balign 32 @ align to cache line
|
||||
|
||||
strne r2, [r5, #AT91_DDRSDRC_RTR] @ disable DDR1 access
|
||||
strne r3, [r5, #AT91_DDRSDRC_LPR] @ power down DDR1
|
||||
str r2, [r0, #AT91_DDRSDRC_RTR] @ disable DDR0 access
|
||||
str r3, [r0, #AT91_DDRSDRC_LPR] @ power down DDR0
|
||||
str r4, [r1, #AT91_RSTC_CR] @ reset processor
|
||||
|
|
|
|||
|
|
@ -57,7 +57,7 @@ static irqreturn_t at91x40_timer_interrupt(int irq, void *dev_id)
|
|||
|
||||
static struct irqaction at91x40_timer_irq = {
|
||||
.name = "at91_tick",
|
||||
.flags = IRQF_DISABLED | IRQF_TIMER,
|
||||
.flags = IRQF_TIMER,
|
||||
.handler = at91x40_timer_interrupt
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -176,7 +176,7 @@ static struct at24_platform_data eeprom_info = {
|
|||
.context = (void *)0x7f00,
|
||||
};
|
||||
|
||||
static struct snd_platform_data dm365_evm_snd_data = {
|
||||
static struct snd_platform_data dm365_evm_snd_data __maybe_unused = {
|
||||
.asp_chan_q = EVENTQ_3,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -15,8 +15,6 @@
|
|||
|
||||
#include <mach/hardware.h>
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000)
|
||||
#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400)
|
||||
#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800)
|
||||
|
|
@ -39,6 +37,8 @@
|
|||
#define UART_DM646X_SCR_TX_WATERMARK 0x08
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
extern int davinci_serial_init(struct platform_device *);
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -1,2 +1,9 @@
|
|||
/* Simple oneliner include to the PCIv3 early init */
|
||||
#ifdef CONFIG_PCI
|
||||
extern int pci_v3_early_init(void);
|
||||
#else
|
||||
static inline int pci_v3_early_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -140,6 +140,7 @@ int __init coherency_init(void)
|
|||
coherency_base = of_iomap(np, 0);
|
||||
coherency_cpu_base = of_iomap(np, 1);
|
||||
set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
|
||||
of_node_put(np);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -147,9 +148,14 @@ int __init coherency_init(void)
|
|||
|
||||
static int __init coherency_late_init(void)
|
||||
{
|
||||
if (of_find_matching_node(NULL, of_coherency_table))
|
||||
struct device_node *np;
|
||||
|
||||
np = of_find_matching_node(NULL, of_coherency_table);
|
||||
if (np) {
|
||||
bus_register_notifier(&platform_bus_type,
|
||||
&mvebu_hwcc_platform_nb);
|
||||
of_node_put(np);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -67,6 +67,7 @@ int __init armada_370_xp_pmsu_init(void)
|
|||
pr_info("Initializing Power Management Service Unit\n");
|
||||
pmsu_mp_base = of_iomap(np, 0);
|
||||
pmsu_reset_base = of_iomap(np, 1);
|
||||
of_node_put(np);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -98,6 +98,7 @@ static int __init mvebu_system_controller_init(void)
|
|||
BUG_ON(!match);
|
||||
system_controller_base = of_iomap(np, 0);
|
||||
mvebu_sc = (struct mvebu_system_controller *)match->data;
|
||||
of_node_put(np);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -1108,9 +1108,9 @@ static const struct pinctrl_map eva_pinctrl_map[] = {
|
|||
PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-r8a7740",
|
||||
"fsib_mclk_in", "fsib"),
|
||||
/* GETHER */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740",
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("r8a7740-gether", "pfc-r8a7740",
|
||||
"gether_mii", "gether"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740",
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("r8a7740-gether", "pfc-r8a7740",
|
||||
"gether_int", "gether"),
|
||||
/* HDMI */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-r8a7740",
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@
|
|||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/platform_data/gpio-rcar.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/phy.h>
|
||||
#include <linux/regulator/fixed.h>
|
||||
#include <linux/regulator/machine.h>
|
||||
#include <linux/sh_eth.h>
|
||||
|
|
@ -155,6 +156,30 @@ static void __init lager_add_standard_devices(void)
|
|||
ðer_pdata, sizeof(ether_pdata));
|
||||
}
|
||||
|
||||
/*
|
||||
* Ether LEDs on the Lager board are named LINK and ACTIVE which corresponds
|
||||
* to non-default 01 setting of the Micrel KSZ8041 PHY control register 1 bits
|
||||
* 14-15. We have to set them back to 01 from the default 00 value each time
|
||||
* the PHY is reset. It's also important because the PHY's LED0 signal is
|
||||
* connected to SoC's ETH_LINK signal and in the PHY's default mode it will
|
||||
* bounce on and off after each packet, which we apparently want to avoid.
|
||||
*/
|
||||
static int lager_ksz8041_fixup(struct phy_device *phydev)
|
||||
{
|
||||
u16 phyctrl1 = phy_read(phydev, 0x1e);
|
||||
|
||||
phyctrl1 &= ~0xc000;
|
||||
phyctrl1 |= 0x4000;
|
||||
return phy_write(phydev, 0x1e, phyctrl1);
|
||||
}
|
||||
|
||||
static void __init lager_init(void)
|
||||
{
|
||||
lager_add_standard_devices();
|
||||
|
||||
phy_register_fixup_for_id("r8a7790-ether-ff:01", lager_ksz8041_fixup);
|
||||
}
|
||||
|
||||
static const char *lager_boards_compat_dt[] __initdata = {
|
||||
"renesas,lager",
|
||||
NULL,
|
||||
|
|
@ -163,6 +188,6 @@ static const char *lager_boards_compat_dt[] __initdata = {
|
|||
DT_MACHINE_START(LAGER_DT, "lager")
|
||||
.init_early = r8a7790_init_delay,
|
||||
.init_time = r8a7790_timer_init,
|
||||
.init_machine = lager_add_standard_devices,
|
||||
.init_machine = lager_init,
|
||||
.dt_compat = lager_boards_compat_dt,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -131,6 +131,16 @@ static void tc2_pm_down(u64 residency)
|
|||
} else
|
||||
BUG();
|
||||
|
||||
/*
|
||||
* If the CPU is committed to power down, make sure
|
||||
* the power controller will be in charge of waking it
|
||||
* up upon IRQ, ie IRQ lines are cut from GIC CPU IF
|
||||
* to the CPU by disabling the GIC CPU IF to prevent wfi
|
||||
* from completing execution behind power controller back
|
||||
*/
|
||||
if (!skip_wfi)
|
||||
gic_cpu_if_down();
|
||||
|
||||
if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
|
||||
arch_spin_unlock(&tc2_pm_lock);
|
||||
|
||||
|
|
@ -231,7 +241,6 @@ static void tc2_pm_suspend(u64 residency)
|
|||
cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
|
||||
cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
|
||||
ve_spc_set_resume_addr(cluster, cpu, virt_to_phys(mcpm_entry_point));
|
||||
gic_cpu_if_down();
|
||||
tc2_pm_down(residency);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -700,6 +700,7 @@ static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
|
|||
phys_addr_t sdramwins_phys_base,
|
||||
size_t sdramwins_size)
|
||||
{
|
||||
struct device_node *np;
|
||||
int win;
|
||||
|
||||
mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size);
|
||||
|
|
@ -712,8 +713,11 @@ static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
|
|||
return -ENOMEM;
|
||||
}
|
||||
|
||||
if (of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric"))
|
||||
np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
|
||||
if (np) {
|
||||
mbus->hw_io_coherency = 1;
|
||||
of_node_put(np);
|
||||
}
|
||||
|
||||
for (win = 0; win < mbus->soc->num_wins; win++)
|
||||
mvebu_mbus_disable_window(mbus, win);
|
||||
|
|
@ -861,11 +865,13 @@ static void __init mvebu_mbus_get_pcie_resources(struct device_node *np,
|
|||
int ret;
|
||||
|
||||
/*
|
||||
* These are optional, so we clear them and they'll
|
||||
* be zero if they are missing from the DT.
|
||||
* These are optional, so we make sure that resource_size(x) will
|
||||
* return 0.
|
||||
*/
|
||||
memset(mem, 0, sizeof(struct resource));
|
||||
mem->end = -1;
|
||||
memset(io, 0, sizeof(struct resource));
|
||||
io->end = -1;
|
||||
|
||||
ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg));
|
||||
if (!ret) {
|
||||
|
|
|
|||
|
|
@ -293,10 +293,9 @@ static void gpio_rcar_parse_pdata(struct gpio_rcar_priv *p)
|
|||
if (pdata) {
|
||||
p->config = *pdata;
|
||||
} else if (IS_ENABLED(CONFIG_OF) && np) {
|
||||
ret = of_parse_phandle_with_args(np, "gpio-ranges",
|
||||
"#gpio-range-cells", 0, &args);
|
||||
p->config.number_of_pins = ret == 0 && args.args_count == 3
|
||||
? args.args[2]
|
||||
ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0,
|
||||
&args);
|
||||
p->config.number_of_pins = ret == 0 ? args.args[2]
|
||||
: RCAR_MAX_GPIO_PER_BANK;
|
||||
p->config.gpio_base = -1;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -113,14 +113,14 @@ static const struct sh_mobile_sdhi_ops sdhi_ops = {
|
|||
};
|
||||
|
||||
static const struct of_device_id sh_mobile_sdhi_of_match[] = {
|
||||
{ .compatible = "renesas,shmobile-sdhi" },
|
||||
{ .compatible = "renesas,sh7372-sdhi" },
|
||||
{ .compatible = "renesas,sh73a0-sdhi", .data = &sh_mobile_sdhi_of_cfg[0], },
|
||||
{ .compatible = "renesas,r8a73a4-sdhi", .data = &sh_mobile_sdhi_of_cfg[0], },
|
||||
{ .compatible = "renesas,r8a7740-sdhi", .data = &sh_mobile_sdhi_of_cfg[0], },
|
||||
{ .compatible = "renesas,r8a7778-sdhi", .data = &sh_mobile_sdhi_of_cfg[0], },
|
||||
{ .compatible = "renesas,r8a7779-sdhi", .data = &sh_mobile_sdhi_of_cfg[0], },
|
||||
{ .compatible = "renesas,r8a7790-sdhi", .data = &sh_mobile_sdhi_of_cfg[0], },
|
||||
{ .compatible = "renesas,sdhi-shmobile" },
|
||||
{ .compatible = "renesas,sdhi-sh7372" },
|
||||
{ .compatible = "renesas,sdhi-sh73a0", .data = &sh_mobile_sdhi_of_cfg[0], },
|
||||
{ .compatible = "renesas,sdhi-r8a73a4", .data = &sh_mobile_sdhi_of_cfg[0], },
|
||||
{ .compatible = "renesas,sdhi-r8a7740", .data = &sh_mobile_sdhi_of_cfg[0], },
|
||||
{ .compatible = "renesas,sdhi-r8a7778", .data = &sh_mobile_sdhi_of_cfg[0], },
|
||||
{ .compatible = "renesas,sdhi-r8a7779", .data = &sh_mobile_sdhi_of_cfg[0], },
|
||||
{ .compatible = "renesas,sdhi-r8a7790", .data = &sh_mobile_sdhi_of_cfg[0], },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, sh_mobile_sdhi_of_match);
|
||||
|
|
|
|||
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