drm/msm: add headless gpu device for imx5
This patch allows using drm/msm without qcom display hardware. It adds a amd,imageon compatible, which is used instead of qcom,adreno, but does not require a top level msm node. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@gmail.com>
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Коммит
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@ -2,7 +2,7 @@
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config DRM_MSM
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tristate "MSM DRM"
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depends on DRM
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depends on ARCH_QCOM || (ARM && COMPILE_TEST)
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depends on ARCH_QCOM || SOC_IMX5 || (ARM && COMPILE_TEST)
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depends on OF && COMMON_CLK
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depends on MMU
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select QCOM_MDT_LOADER if ARCH_QCOM
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@ -11,7 +11,7 @@ config DRM_MSM
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select DRM_PANEL
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select SHMEM
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select TMPFS
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select QCOM_SCM
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select QCOM_SCM if ARCH_QCOM
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select WANT_DEV_COREDUMP
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select SND_SOC_HDMI_CODEC if SND_SOC
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select SYNC_FILE
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@ -271,7 +271,8 @@ static int find_chipid(struct device *dev, struct adreno_rev *rev)
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if (ret == 0) {
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unsigned int r, patch;
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if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2) {
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if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 ||
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sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) {
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rev->core = r / 100;
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r %= 100;
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rev->major = r / 10;
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@ -359,9 +360,37 @@ static const struct component_ops a3xx_ops = {
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.unbind = adreno_unbind,
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};
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static void adreno_device_register_headless(void)
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{
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/* on imx5, we don't have a top-level mdp/dpu node
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* this creates a dummy node for the driver for that case
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*/
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struct platform_device_info dummy_info = {
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.parent = NULL,
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.name = "msm",
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.id = -1,
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.res = NULL,
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.num_res = 0,
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.data = NULL,
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.size_data = 0,
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.dma_mask = ~0,
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};
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platform_device_register_full(&dummy_info);
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}
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static int adreno_probe(struct platform_device *pdev)
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{
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return component_add(&pdev->dev, &a3xx_ops);
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int ret;
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ret = component_add(&pdev->dev, &a3xx_ops);
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if (ret)
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return ret;
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if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon"))
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adreno_device_register_headless();
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return 0;
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}
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static int adreno_remove(struct platform_device *pdev)
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@ -373,6 +402,8 @@ static int adreno_remove(struct platform_device *pdev)
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static const struct of_device_id dt_match[] = {
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{ .compatible = "qcom,adreno" },
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{ .compatible = "qcom,adreno-3xx" },
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/* for compatibility with imx5 gpu: */
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{ .compatible = "amd,imageon" },
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/* for backwards compat w/ downstream kgsl DT files: */
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{ .compatible = "qcom,kgsl-3d0" },
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{}
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@ -235,7 +235,7 @@ int msm_debugfs_init(struct drm_minor *minor)
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debugfs_create_file("gpu", S_IRUSR, minor->debugfs_root,
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dev, &msm_gpu_fops);
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if (priv->kms->funcs->debugfs_init) {
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if (priv->kms && priv->kms->funcs->debugfs_init) {
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ret = priv->kms->funcs->debugfs_init(priv->kms, minor);
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if (ret)
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return ret;
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@ -520,17 +520,13 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv)
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priv->kms = kms;
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break;
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default:
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kms = ERR_PTR(-ENODEV);
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/* valid only for the dummy headless case, where of_node=NULL */
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WARN_ON(dev->of_node);
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kms = NULL;
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break;
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}
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if (IS_ERR(kms)) {
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/*
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* NOTE: once we have GPU support, having no kms should not
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* be considered fatal.. ideally we would still support gpu
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* and (for example) use dmabuf/prime to share buffers with
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* imx drm driver on iMX5
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*/
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DRM_DEV_ERROR(dev, "failed to load kms\n");
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ret = PTR_ERR(kms);
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priv->kms = NULL;
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@ -648,7 +644,7 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv)
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drm_mode_config_reset(ddev);
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#ifdef CONFIG_DRM_FBDEV_EMULATION
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if (fbdev)
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if (kms && fbdev)
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priv->fbdev = msm_fbdev_init(ddev);
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#endif
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@ -1332,6 +1328,7 @@ static int add_display_components(struct device *dev,
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static const struct of_device_id msm_gpu_match[] = {
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{ .compatible = "qcom,adreno" },
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{ .compatible = "qcom,adreno-3xx" },
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{ .compatible = "amd,imageon" },
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{ .compatible = "qcom,kgsl-3d0" },
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{ },
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};
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@ -1376,9 +1373,11 @@ static int msm_pdev_probe(struct platform_device *pdev)
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struct component_match *match = NULL;
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int ret;
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ret = add_display_components(&pdev->dev, &match);
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if (ret)
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return ret;
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if (get_mdp_ver(pdev)) {
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ret = add_display_components(&pdev->dev, &match);
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if (ret)
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return ret;
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}
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ret = add_gpu_components(&pdev->dev, &match);
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if (ret)
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