x86: add clflush before monitor for Intel 7400 series
For Intel 7400 series CPUs, the recommendation is to use a clflush on the monitored address just before monitor and mwait pair [1]. This clflush makes sure that there are no false wakeups from mwait when the monitored address was recently written to. [1] "MONITOR/MWAIT Recommendations for Intel Xeon Processor 7400 series" section in specification update document of 7400 series http://download.intel.com/design/xeon/specupdt/32033601.pdf Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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0cd5c3c80a
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e736ad548d
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@ -93,6 +93,7 @@
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#define X86_FEATURE_XTOPOLOGY (3*32+22) /* cpu topology enum extensions */
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#define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */
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#define X86_FEATURE_NONSTOP_TSC (3*32+24) /* TSC does not stop in C states */
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#define X86_FEATURE_CLFLUSH_MONITOR (3*32+25) /* "" clflush reqd with monitor */
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/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
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#define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */
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@ -291,6 +291,9 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
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ds_init_intel(c);
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}
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if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush)
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set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR);
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#ifdef CONFIG_X86_64
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if (c->x86 == 15)
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c->x86_cache_alignment = c->x86_clflush_size * 2;
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@ -180,6 +180,9 @@ void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
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trace_power_start(&it, POWER_CSTATE, (ax>>4)+1);
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if (!need_resched()) {
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if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
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clflush((void *)¤t_thread_info()->flags);
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__monitor((void *)¤t_thread_info()->flags, 0, 0);
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smp_mb();
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if (!need_resched())
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@ -194,6 +197,9 @@ static void mwait_idle(void)
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struct power_trace it;
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if (!need_resched()) {
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trace_power_start(&it, POWER_CSTATE, 1);
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if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
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clflush((void *)¤t_thread_info()->flags);
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__monitor((void *)¤t_thread_info()->flags, 0, 0);
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smp_mb();
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if (!need_resched())
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