RISC-V: Support HI20/LO12_I/LO12_S relocation type in kernel module
HI20 and LO12_I/LO12_S relocate the absolute address, the range of offset must in 32-bit. Signed-off-by: Zong Li <zong@andestech.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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e1910c72bd
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e7456e696b
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@ -92,6 +92,45 @@ static int apply_r_riscv_pcrel_lo12_s_rela(struct module *me, u32 *location,
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return 0;
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}
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static int apply_r_riscv_hi20_rela(struct module *me, u32 *location,
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Elf_Addr v)
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{
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s32 hi20;
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if (IS_ENABLED(CMODEL_MEDLOW)) {
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pr_err(
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"%s: target %016llx can not be addressed by the 32-bit offset from PC = %p\n",
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me->name, v, location);
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return -EINVAL;
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}
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hi20 = ((s32)v + 0x800) & 0xfffff000;
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*location = (*location & 0xfff) | hi20;
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return 0;
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}
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static int apply_r_riscv_lo12_i_rela(struct module *me, u32 *location,
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Elf_Addr v)
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{
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/* Skip medlow checking because of filtering by HI20 already */
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s32 hi20 = ((s32)v + 0x800) & 0xfffff000;
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s32 lo12 = ((s32)v - hi20);
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*location = (*location & 0xfffff) | ((lo12 & 0xfff) << 20);
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return 0;
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}
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static int apply_r_riscv_lo12_s_rela(struct module *me, u32 *location,
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Elf_Addr v)
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{
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/* Skip medlow checking because of filtering by HI20 already */
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s32 hi20 = ((s32)v + 0x800) & 0xfffff000;
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s32 lo12 = ((s32)v - hi20);
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u32 imm11_5 = (lo12 & 0xfe0) << (31 - 11);
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u32 imm4_0 = (lo12 & 0x1f) << (11 - 4);
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*location = (*location & 0x1fff07f) | imm11_5 | imm4_0;
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return 0;
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}
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static int apply_r_riscv_got_hi20_rela(struct module *me, u32 *location,
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Elf_Addr v)
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{
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@ -176,6 +215,9 @@ static int (*reloc_handlers_rela[]) (struct module *me, u32 *location,
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[R_RISCV_PCREL_HI20] = apply_r_riscv_pcrel_hi20_rela,
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[R_RISCV_PCREL_LO12_I] = apply_r_riscv_pcrel_lo12_i_rela,
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[R_RISCV_PCREL_LO12_S] = apply_r_riscv_pcrel_lo12_s_rela,
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[R_RISCV_HI20] = apply_r_riscv_hi20_rela,
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[R_RISCV_LO12_I] = apply_r_riscv_lo12_i_rela,
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[R_RISCV_LO12_S] = apply_r_riscv_lo12_s_rela,
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[R_RISCV_GOT_HI20] = apply_r_riscv_got_hi20_rela,
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[R_RISCV_CALL_PLT] = apply_r_riscv_call_plt_rela,
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[R_RISCV_CALL] = apply_r_riscv_call_rela,
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