iommu/exynos: Don't open-code loop unrolling
IOMMU domain allocation is not performance critical operation, so remove hand made optimisation of unrolled initialization loop and leave this to the compiler. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
This commit is contained in:
Родитель
97da3854c5
Коммит
e75276638c
|
@ -741,16 +741,8 @@ static struct iommu_domain *exynos_iommu_domain_alloc(unsigned type)
|
||||||
goto err_counter;
|
goto err_counter;
|
||||||
|
|
||||||
/* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */
|
/* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */
|
||||||
for (i = 0; i < NUM_LV1ENTRIES; i += 8) {
|
for (i = 0; i < NUM_LV1ENTRIES; i++)
|
||||||
domain->pgtable[i + 0] = ZERO_LV2LINK;
|
domain->pgtable[i] = ZERO_LV2LINK;
|
||||||
domain->pgtable[i + 1] = ZERO_LV2LINK;
|
|
||||||
domain->pgtable[i + 2] = ZERO_LV2LINK;
|
|
||||||
domain->pgtable[i + 3] = ZERO_LV2LINK;
|
|
||||||
domain->pgtable[i + 4] = ZERO_LV2LINK;
|
|
||||||
domain->pgtable[i + 5] = ZERO_LV2LINK;
|
|
||||||
domain->pgtable[i + 6] = ZERO_LV2LINK;
|
|
||||||
domain->pgtable[i + 7] = ZERO_LV2LINK;
|
|
||||||
}
|
|
||||||
|
|
||||||
handle = dma_map_single(dma_dev, domain->pgtable, LV1TABLE_SIZE,
|
handle = dma_map_single(dma_dev, domain->pgtable, LV1TABLE_SIZE,
|
||||||
DMA_TO_DEVICE);
|
DMA_TO_DEVICE);
|
||||||
|
|
Загрузка…
Ссылка в новой задаче