arm64: dts: qcom: sm8350: add USB and PHY device nodes
Add device nodes for the two instances each of USB3 controllers, QMP SS PHYs and SNPS HS PHYs. Signed-off-by: Jack Pham <jackp@codeaurora.org> Link: https://lore.kernel.org/r/20210116013802.1609-2-jackp@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210204170907.63545-3-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Jack Pham
Bjorn Andersson
Родитель
187f65b7f0
Коммит
e780fb318f
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@ -592,6 +592,185 @@
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};
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};
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usb_1_hsphy: phy@88e3000 {
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compatible = "qcom,sm8350-usb-hs-phy",
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"qcom,usb-snps-hs-7nm-phy";
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reg = <0 0x088e3000 0 0x400>;
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status = "disabled";
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#phy-cells = <0>;
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "ref";
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resets = <&gcc 20>;
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};
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usb_2_hsphy: phy@88e4000 {
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compatible = "qcom,sm8250-usb-hs-phy",
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"qcom,usb-snps-hs-7nm-phy";
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reg = <0 0x088e4000 0 0x400>;
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status = "disabled";
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#phy-cells = <0>;
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "ref";
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resets = <&gcc 21>;
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};
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usb_1_qmpphy: phy-wrapper@88e9000 {
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compatible = "qcom,sm8350-qmp-usb3-phy";
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reg = <0 0x088e9000 0 0x200>,
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<0 0x088e8000 0 0x20>;
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reg-names = "reg-base", "dp_com";
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status = "disabled";
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#clock-cells = <1>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clocks = <&gcc 187>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc 189>;
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clock-names = "aux", "ref_clk_src", "com_aux";
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resets = <&gcc 28>,
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<&gcc 30>;
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reset-names = "phy", "common";
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usb_1_ssphy: phy@88e9200 {
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reg = <0 0x088e9200 0 0x200>,
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<0 0x088e9400 0 0x200>,
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<0 0x088e9c00 0 0x400>,
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<0 0x088e9600 0 0x200>,
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<0 0x088e9800 0 0x200>,
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<0 0x088e9a00 0 0x100>;
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#phy-cells = <0>;
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#clock-cells = <1>;
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clocks = <&gcc 190>;
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clock-names = "pipe0";
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clock-output-names = "usb3_phy_pipe_clk_src";
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};
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};
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usb_2_qmpphy: phy-wrapper@88eb000 {
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compatible = "qcom,sm8350-qmp-usb3-uni-phy";
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reg = <0 0x088eb000 0 0x200>;
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status = "disabled";
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#clock-cells = <1>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clocks = <&gcc 193>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc 192>,
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<&gcc 195>;
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clock-names = "aux", "ref_clk_src", "ref", "com_aux";
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resets = <&gcc 33>,
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<&gcc 31>;
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reset-names = "phy", "common";
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usb_2_ssphy: phy@88ebe00 {
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reg = <0 0x088ebe00 0 0x200>,
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<0 0x088ec000 0 0x200>,
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<0 0x088eb200 0 0x1100>;
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#phy-cells = <0>;
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#clock-cells = <1>;
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clocks = <&gcc 196>;
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clock-names = "pipe0";
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clock-output-names = "usb3_uni_phy_pipe_clk_src";
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};
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};
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usb_1: usb@a6f8800 {
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compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
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reg = <0 0x0a6f8800 0 0x400>;
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status = "disabled";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clocks = <&gcc 23>,
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<&gcc 173>,
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<&gcc 18>,
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<&gcc 176>,
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<&gcc 179>;
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clock-names = "cfg_noc", "core", "iface", "mock_utmi",
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"sleep";
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assigned-clocks = <&gcc 176>,
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<&gcc 173>;
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assigned-clock-rates = <19200000>, <200000000>;
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interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
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<&pdc 14 IRQ_TYPE_EDGE_BOTH>,
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<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
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<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
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"dm_hs_phy_irq", "ss_phy_irq";
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power-domains = <&gcc 4>;
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resets = <&gcc 26>;
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usb_1_dwc3: dwc3@a600000 {
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compatible = "snps,dwc3";
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reg = <0 0x0a600000 0 0xcd00>;
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interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
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iommus = <&apps_smmu 0x0 0x0>;
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snps,dis_u2_susphy_quirk;
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snps,dis_enblslpm_quirk;
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phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
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phy-names = "usb2-phy", "usb3-phy";
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};
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};
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usb_2: usb@a8f8800 {
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compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
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reg = <0 0x0a8f8800 0 0x400>;
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status = "disabled";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clocks = <&gcc 24>,
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<&gcc 180>,
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<&gcc 19>,
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<&gcc 183>,
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<&gcc 186>,
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<&gcc 192>;
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clock-names = "cfg_noc", "core", "iface", "mock_utmi",
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"sleep", "xo";
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assigned-clocks = <&gcc 183>,
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<&gcc 180>;
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assigned-clock-rates = <19200000>, <200000000>;
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interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
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<&pdc 12 IRQ_TYPE_EDGE_BOTH>,
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<&pdc 13 IRQ_TYPE_EDGE_BOTH>,
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<&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
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"dm_hs_phy_irq", "ss_phy_irq";
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power-domains = <&gcc 5>;
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resets = <&gcc 27>;
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usb_2_dwc3: dwc3@a800000 {
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compatible = "snps,dwc3";
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reg = <0 0x0a800000 0 0xcd00>;
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interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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iommus = <&apps_smmu 0x20 0x0>;
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snps,dis_u2_susphy_quirk;
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snps,dis_enblslpm_quirk;
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phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
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phy-names = "usb2-phy", "usb3-phy";
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};
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};
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};
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timer {
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