Qualcomm ARM64 Updates for v4.21 Part 2
* Switch to use dwc3-qcom glue driver on MSM8996 * Fix issue with xo clk name on MSM8998 * Add cooling maps on MSM8916 * Add UART nodes on SDM845 * Add camera subsystem support on MSM8996 and MSM8916 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJcCv8oAAoJEFKiBbHx2RXVPU8P/RdMSnKQp4hWtXyi/n0x8A7W 221Q/VQNzv4HjujdBP/+QsDBErrkb2JKUvqS5VPYqh1MPHnmbXuv185Ccr9m6L+D YMNpZoMe1bWhUmdQnSS95DSeLzIpCS8sSyczWUdQlm1faVoFZ7A6XyGdFUKVCBqf 6x3egZb8gBDKfUS1KnzEo8bhWxltdzK7TOmjZQJzZIqFmQ5eb42YV+mBhRAwj6nt 1wi93eof+f7DOSVOtBebyiDiWAKVcuDAZgMDe0cDVJzxgNx9ODAxheF1DPM9P2XK izak3TRdlEgZLMUuH65mlqxR3FGqMoKpPrl+WYrQIFO6NdgUiB308TJDPW85B9eE 1ZSZOFr059K4btP8kG27PBKxISKuLsiFW348zP2Cx1QOquQUX/R2t7yfsShAABQX S3MpUvHzGwfCuHih+SNSmk3cd10C65efNR9UN4MwbKtFqVRfiWRSKWGgWMQNkOQ0 ga6NKK2OfTqGeJ5MYnqM0Ke25+ACkdW1UMhGaFg3IPqTwdZZ2ClKDq2I8AvqnZ1G k656Z4KGud8RifPBeRARqzRe8ZCxomns7f66IAyCP6xO/pxC+JcjBL0GY3bBDNsE QA4kfrLQ27LTDvICEOdUsshUoiDBg+keEttbLI0QCh6GTyZKL8yqDp8xICp1AEvq InAboFK/dxsqdmRNkgAh =EMri -----END PGP SIGNATURE----- Merge tag 'qcom-arm64-for-4.21-2' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt Qualcomm ARM64 Updates for v4.21 Part 2 * Switch to use dwc3-qcom glue driver on MSM8996 * Fix issue with xo clk name on MSM8998 * Add cooling maps on MSM8916 * Add UART nodes on SDM845 * Add camera subsystem support on MSM8996 and MSM8916 * tag 'qcom-arm64-for-4.21-2' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: arm64: dts: msm8996: Use dwc3-qcom glue driver for USB arm64: dts: qcom: msm8998: Fixup clock to use xo_board arm64: dts: qcom: sdm845: Add UART nodes arm64: dts: qcom: msm8996: Add CAMSS support arm64: dts: qcom: msm8996: Add VFE SMMU node arm64: dts: qcom: Add pinctrls for camera sensors arm64: dts: qcom: Add Camera Control Interface pinctrls arm64: dts: qcom: msm8916: Add CAMSS support arm64: dts: qcom: msm8916: Add IOMMU sub-node for VFE context bank arm64: dts: msm8916: Add all CPUs in cooling maps Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
Коммит
e7828317a4
|
|
@ -385,8 +385,9 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
usb@6a00000 {
|
||||
usb@6af8800 {
|
||||
status = "okay";
|
||||
extcon = <&usb3_id>;
|
||||
|
||||
dwc3@6a00000 {
|
||||
extcon = <&usb3_id>;
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||||
|
|
@ -401,8 +402,9 @@
|
|||
pinctrl-0 = <&usb3_vbus_det_gpio>;
|
||||
};
|
||||
|
||||
usb@7600000 {
|
||||
usb@76f8800 {
|
||||
status = "okay";
|
||||
extcon = <&usb2_id>;
|
||||
|
||||
dwc3@7600000 {
|
||||
extcon = <&usb2_id>;
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||||
|
|
|
|||
|
|
@ -689,4 +689,80 @@
|
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bias-pull-up;
|
||||
};
|
||||
};
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||||
|
||||
cci0_default: cci0_default {
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||||
pinmux {
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||||
function = "cci_i2c";
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||||
pins = "gpio29", "gpio30";
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||||
};
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pinconf {
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||||
pins = "gpio29", "gpio30";
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drive-strength = <16>;
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bias-disable;
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};
|
||||
};
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||||
|
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camera_front_default: camera_front_default {
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pinmux_pwdn {
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function = "gpio";
|
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pins = "gpio33";
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};
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pinconf_pwdn {
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pins = "gpio33";
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drive-strength = <16>;
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bias-disable;
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};
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|
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pinmux_rst {
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function = "gpio";
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pins = "gpio28";
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};
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pinconf_rst {
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pins = "gpio28";
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drive-strength = <16>;
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bias-disable;
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};
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|
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pinmux_mclk1 {
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function = "cam_mclk1";
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pins = "gpio27";
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};
|
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pinconf_mclk1 {
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pins = "gpio27";
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drive-strength = <16>;
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bias-disable;
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};
|
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};
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camera_rear_default: camera_rear_default {
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pinmux_pwdn {
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function = "gpio";
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pins = "gpio34";
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};
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pinconf_pwdn {
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pins = "gpio34";
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drive-strength = <16>;
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bias-disable;
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};
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|
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pinmux_rst {
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function = "gpio";
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pins = "gpio35";
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};
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pinconf_rst {
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pins = "gpio35";
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drive-strength = <16>;
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bias-disable;
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};
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pinmux_mclk0 {
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function = "cam_mclk0";
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pins = "gpio26";
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};
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pinconf_mclk0 {
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pins = "gpio26";
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drive-strength = <16>;
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bias-disable;
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};
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};
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};
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@ -202,7 +202,10 @@
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cooling-maps {
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map0 {
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trip = <&cpu_alert0>;
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cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
|
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};
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};
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@ -229,7 +232,10 @@
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cooling-maps {
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map0 {
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trip = <&cpu_alert1>;
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cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
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<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
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};
|
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};
|
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};
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|
|
@ -821,6 +827,13 @@
|
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clock-names = "iface", "bus";
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qcom,iommu-secure-id = <17>;
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|
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// vfe:
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iommu-ctx@3000 {
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compatible = "qcom,msm-iommu-v1-sec";
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reg = <0x3000 0x1000>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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};
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|
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// mdp_0:
|
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iommu-ctx@4000 {
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compatible = "qcom,msm-iommu-v1-ns";
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|
|
@ -1432,6 +1445,86 @@
|
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compatible = "venus-encoder";
|
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};
|
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};
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|
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camss: camss@1b00000 {
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compatible = "qcom,msm8916-camss";
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reg = <0x1b0ac00 0x200>,
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<0x1b00030 0x4>,
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<0x1b0b000 0x200>,
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<0x1b00038 0x4>,
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<0x1b08000 0x100>,
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<0x1b08400 0x100>,
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<0x1b0a000 0x500>,
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<0x1b00020 0x10>,
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<0x1b10000 0x1000>;
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reg-names = "csiphy0",
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"csiphy0_clk_mux",
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"csiphy1",
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"csiphy1_clk_mux",
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"csid0",
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"csid1",
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"ispif",
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"csi_clk_mux",
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"vfe0";
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interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
|
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<GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
|
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<GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "csiphy0",
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"csiphy1",
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"csid0",
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"csid1",
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"ispif",
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"vfe0";
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power-domains = <&gcc VFE_GDSC>;
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clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
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<&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
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<&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
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<&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
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<&gcc GCC_CAMSS_CSI0_AHB_CLK>,
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<&gcc GCC_CAMSS_CSI0_CLK>,
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<&gcc GCC_CAMSS_CSI0PHY_CLK>,
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<&gcc GCC_CAMSS_CSI0PIX_CLK>,
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<&gcc GCC_CAMSS_CSI0RDI_CLK>,
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<&gcc GCC_CAMSS_CSI1_AHB_CLK>,
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<&gcc GCC_CAMSS_CSI1_CLK>,
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<&gcc GCC_CAMSS_CSI1PHY_CLK>,
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<&gcc GCC_CAMSS_CSI1PIX_CLK>,
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<&gcc GCC_CAMSS_CSI1RDI_CLK>,
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<&gcc GCC_CAMSS_AHB_CLK>,
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<&gcc GCC_CAMSS_VFE0_CLK>,
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<&gcc GCC_CAMSS_CSI_VFE0_CLK>,
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<&gcc GCC_CAMSS_VFE_AHB_CLK>,
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<&gcc GCC_CAMSS_VFE_AXI_CLK>;
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clock-names = "top_ahb",
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"ispif_ahb",
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"csiphy0_timer",
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"csiphy1_timer",
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"csi0_ahb",
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"csi0",
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"csi0_phy",
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"csi0_pix",
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"csi0_rdi",
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"csi1_ahb",
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"csi1",
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"csi1_phy",
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"csi1_pix",
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"csi1_rdi",
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"ahb",
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"vfe0",
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"csi_vfe0",
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"vfe_ahb",
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"vfe_axi";
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vdda-supply = <&pm8916_l2>;
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iommus = <&apps_iommu 3>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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smd {
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|
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@ -495,4 +495,124 @@
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bias-disable;
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};
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};
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cci0_default: cci0_default {
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pinmux {
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function = "cci_i2c";
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pins = "gpio17", "gpio18";
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};
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pinconf {
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pins = "gpio17", "gpio18";
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drive-strength = <16>;
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bias-disable;
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};
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};
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cci1_default: cci1_default {
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pinmux {
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function = "cci_i2c";
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pins = "gpio19", "gpio20";
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};
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pinconf {
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pins = "gpio19", "gpio20";
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drive-strength = <16>;
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bias-disable;
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};
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};
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camera_board_default: camera_board_default {
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mux_pwdn {
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function = "gpio";
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pins = "gpio98";
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};
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config_pwdn {
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pins = "gpio98";
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drive-strength = <16>;
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bias-disable;
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};
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mux_rst {
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function = "gpio";
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pins = "gpio104";
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};
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config_rst {
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pins = "gpio104";
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drive-strength = <16>;
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bias-disable;
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};
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mux_mclk1 {
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function = "cam_mclk";
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pins = "gpio14";
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};
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config_mclk1 {
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pins = "gpio14";
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drive-strength = <16>;
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bias-disable;
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};
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};
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|
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camera_front_default: camera_front_default {
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mux_pwdn {
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function = "gpio";
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pins = "gpio133";
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};
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config_pwdn {
|
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pins = "gpio133";
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drive-strength = <16>;
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bias-disable;
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};
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|
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mux_rst {
|
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function = "gpio";
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pins = "gpio23";
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};
|
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config_rst {
|
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pins = "gpio23";
|
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drive-strength = <16>;
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bias-disable;
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};
|
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|
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mux_mclk2 {
|
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function = "cam_mclk";
|
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pins = "gpio15";
|
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};
|
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config_mclk2 {
|
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pins = "gpio15";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
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};
|
||||
};
|
||||
|
||||
camera_rear_default: camera_rear_default {
|
||||
mux_pwdn {
|
||||
function = "gpio";
|
||||
pins = "gpio26";
|
||||
};
|
||||
config_pwdn {
|
||||
pins = "gpio26";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux_rst {
|
||||
function = "gpio";
|
||||
pins = "gpio25";
|
||||
};
|
||||
config_rst {
|
||||
pins = "gpio25";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux_mclk0 {
|
||||
function = "cam_mclk";
|
||||
pins = "gpio13";
|
||||
};
|
||||
config_mclk0 {
|
||||
pins = "gpio13";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -893,8 +893,9 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
usb2: usb@7600000 {
|
||||
compatible = "qcom,dwc3";
|
||||
usb2: usb@76f8800 {
|
||||
compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
|
||||
reg = <0x76f8800 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
|
@ -921,8 +922,9 @@
|
|||
};
|
||||
};
|
||||
|
||||
usb3: usb@6a00000 {
|
||||
compatible = "qcom,dwc3";
|
||||
usb3: usb@6af8800 {
|
||||
compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
|
||||
reg = <0x6af8800 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
|
@ -950,6 +952,158 @@
|
|||
};
|
||||
};
|
||||
|
||||
vfe_smmu: arm,smmu@da0000 {
|
||||
compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
|
||||
reg = <0xda0000 0x10000>;
|
||||
|
||||
#global-interrupts = <1>;
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
|
||||
clocks = <&mmcc SMMU_VFE_AHB_CLK>,
|
||||
<&mmcc SMMU_VFE_AXI_CLK>;
|
||||
clock-names = "iface",
|
||||
"bus";
|
||||
#iommu-cells = <1>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
camss: camss@a00000 {
|
||||
compatible = "qcom,msm8996-camss";
|
||||
reg = <0xa34000 0x1000>,
|
||||
<0xa00030 0x4>,
|
||||
<0xa35000 0x1000>,
|
||||
<0xa00038 0x4>,
|
||||
<0xa36000 0x1000>,
|
||||
<0xa00040 0x4>,
|
||||
<0xa30000 0x100>,
|
||||
<0xa30400 0x100>,
|
||||
<0xa30800 0x100>,
|
||||
<0xa30c00 0x100>,
|
||||
<0xa31000 0x500>,
|
||||
<0xa00020 0x10>,
|
||||
<0xa10000 0x1000>,
|
||||
<0xa14000 0x1000>;
|
||||
reg-names = "csiphy0",
|
||||
"csiphy0_clk_mux",
|
||||
"csiphy1",
|
||||
"csiphy1_clk_mux",
|
||||
"csiphy2",
|
||||
"csiphy2_clk_mux",
|
||||
"csid0",
|
||||
"csid1",
|
||||
"csid2",
|
||||
"csid3",
|
||||
"ispif",
|
||||
"csi_clk_mux",
|
||||
"vfe0",
|
||||
"vfe1";
|
||||
interrupts = <GIC_SPI 78 0>,
|
||||
<GIC_SPI 79 0>,
|
||||
<GIC_SPI 80 0>,
|
||||
<GIC_SPI 296 0>,
|
||||
<GIC_SPI 297 0>,
|
||||
<GIC_SPI 298 0>,
|
||||
<GIC_SPI 299 0>,
|
||||
<GIC_SPI 309 0>,
|
||||
<GIC_SPI 314 0>,
|
||||
<GIC_SPI 315 0>;
|
||||
interrupt-names = "csiphy0",
|
||||
"csiphy1",
|
||||
"csiphy2",
|
||||
"csid0",
|
||||
"csid1",
|
||||
"csid2",
|
||||
"csid3",
|
||||
"ispif",
|
||||
"vfe0",
|
||||
"vfe1";
|
||||
power-domains = <&mmcc VFE0_GDSC>;
|
||||
clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
|
||||
<&mmcc CAMSS_ISPIF_AHB_CLK>,
|
||||
<&mmcc CAMSS_CSI0PHYTIMER_CLK>,
|
||||
<&mmcc CAMSS_CSI1PHYTIMER_CLK>,
|
||||
<&mmcc CAMSS_CSI2PHYTIMER_CLK>,
|
||||
<&mmcc CAMSS_CSI0_AHB_CLK>,
|
||||
<&mmcc CAMSS_CSI0_CLK>,
|
||||
<&mmcc CAMSS_CSI0PHY_CLK>,
|
||||
<&mmcc CAMSS_CSI0PIX_CLK>,
|
||||
<&mmcc CAMSS_CSI0RDI_CLK>,
|
||||
<&mmcc CAMSS_CSI1_AHB_CLK>,
|
||||
<&mmcc CAMSS_CSI1_CLK>,
|
||||
<&mmcc CAMSS_CSI1PHY_CLK>,
|
||||
<&mmcc CAMSS_CSI1PIX_CLK>,
|
||||
<&mmcc CAMSS_CSI1RDI_CLK>,
|
||||
<&mmcc CAMSS_CSI2_AHB_CLK>,
|
||||
<&mmcc CAMSS_CSI2_CLK>,
|
||||
<&mmcc CAMSS_CSI2PHY_CLK>,
|
||||
<&mmcc CAMSS_CSI2PIX_CLK>,
|
||||
<&mmcc CAMSS_CSI2RDI_CLK>,
|
||||
<&mmcc CAMSS_CSI3_AHB_CLK>,
|
||||
<&mmcc CAMSS_CSI3_CLK>,
|
||||
<&mmcc CAMSS_CSI3PHY_CLK>,
|
||||
<&mmcc CAMSS_CSI3PIX_CLK>,
|
||||
<&mmcc CAMSS_CSI3RDI_CLK>,
|
||||
<&mmcc CAMSS_AHB_CLK>,
|
||||
<&mmcc CAMSS_VFE0_CLK>,
|
||||
<&mmcc CAMSS_CSI_VFE0_CLK>,
|
||||
<&mmcc CAMSS_VFE0_AHB_CLK>,
|
||||
<&mmcc CAMSS_VFE0_STREAM_CLK>,
|
||||
<&mmcc CAMSS_VFE1_CLK>,
|
||||
<&mmcc CAMSS_CSI_VFE1_CLK>,
|
||||
<&mmcc CAMSS_VFE1_AHB_CLK>,
|
||||
<&mmcc CAMSS_VFE1_STREAM_CLK>,
|
||||
<&mmcc CAMSS_VFE_AHB_CLK>,
|
||||
<&mmcc CAMSS_VFE_AXI_CLK>;
|
||||
clock-names = "top_ahb",
|
||||
"ispif_ahb",
|
||||
"csiphy0_timer",
|
||||
"csiphy1_timer",
|
||||
"csiphy2_timer",
|
||||
"csi0_ahb",
|
||||
"csi0",
|
||||
"csi0_phy",
|
||||
"csi0_pix",
|
||||
"csi0_rdi",
|
||||
"csi1_ahb",
|
||||
"csi1",
|
||||
"csi1_phy",
|
||||
"csi1_pix",
|
||||
"csi1_rdi",
|
||||
"csi2_ahb",
|
||||
"csi2",
|
||||
"csi2_phy",
|
||||
"csi2_pix",
|
||||
"csi2_rdi",
|
||||
"csi3_ahb",
|
||||
"csi3",
|
||||
"csi3_phy",
|
||||
"csi3_pix",
|
||||
"csi3_rdi",
|
||||
"ahb",
|
||||
"vfe0",
|
||||
"csi_vfe0",
|
||||
"vfe0_ahb",
|
||||
"vfe0_stream",
|
||||
"vfe1",
|
||||
"csi_vfe1",
|
||||
"vfe1_ahb",
|
||||
"vfe1_stream",
|
||||
"vfe_ahb",
|
||||
"vfe_axi";
|
||||
vdda-supply = <&pm8994_l2>;
|
||||
iommus = <&vfe_smmu 0>,
|
||||
<&vfe_smmu 1>,
|
||||
<&vfe_smmu 2>,
|
||||
<&vfe_smmu 3>;
|
||||
status = "disabled";
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
agnoc@0 {
|
||||
power-domains = <&gcc AGGRE0_NOC_GDSC>;
|
||||
compatible = "simple-pm-bus";
|
||||
|
|
|
|||
|
|
@ -54,10 +54,11 @@
|
|||
};
|
||||
|
||||
clocks {
|
||||
xo: xo {
|
||||
xo: xo-board {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <19200000>;
|
||||
clock-output-names = "xo_board";
|
||||
};
|
||||
|
||||
sleep_clk {
|
||||
|
|
|
|||
|
|
@ -402,6 +402,17 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@880000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0x880000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_uart0_default>;
|
||||
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@884000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0x884000 0x4000>;
|
||||
|
|
@ -428,6 +439,17 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@884000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0x884000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_uart1_default>;
|
||||
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@888000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0x888000 0x4000>;
|
||||
|
|
@ -454,6 +476,17 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@888000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0x888000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_uart2_default>;
|
||||
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@88c000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0x88c000 0x4000>;
|
||||
|
|
@ -480,6 +513,17 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@88c000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0x88c000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_uart3_default>;
|
||||
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@890000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0x890000 0x4000>;
|
||||
|
|
@ -506,6 +550,17 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@890000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0x890000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_uart4_default>;
|
||||
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c5: i2c@894000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0x894000 0x4000>;
|
||||
|
|
@ -532,6 +587,17 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@894000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0x894000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_uart5_default>;
|
||||
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c6: i2c@898000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0x898000 0x4000>;
|
||||
|
|
@ -558,6 +624,17 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
uart6: serial@898000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0x898000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_uart6_default>;
|
||||
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c7: i2c@89c000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0x89c000 0x4000>;
|
||||
|
|
@ -583,6 +660,17 @@
|
|||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart7: serial@89c000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0x89c000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_uart7_default>;
|
||||
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_id_1: geniqup@ac0000 {
|
||||
|
|
@ -622,6 +710,17 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
uart8: serial@a80000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0xa80000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_uart8_default>;
|
||||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c9: i2c@a84000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0xa84000 0x4000>;
|
||||
|
|
@ -685,6 +784,17 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
uart10: serial@a88000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0xa88000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_uart10_default>;
|
||||
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c11: i2c@a8c000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0xa8c000 0x4000>;
|
||||
|
|
@ -711,6 +821,17 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
uart11: serial@a8c000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0xa8c000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_uart11_default>;
|
||||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c12: i2c@a90000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0xa90000 0x4000>;
|
||||
|
|
@ -737,6 +858,17 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
uart12: serial@a90000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0xa90000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_uart12_default>;
|
||||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c13: i2c@a94000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0xa94000 0x4000>;
|
||||
|
|
@ -763,6 +895,17 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
uart13: serial@a94000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0xa94000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_uart13_default>;
|
||||
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c14: i2c@a98000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0xa98000 0x4000>;
|
||||
|
|
@ -789,6 +932,17 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
uart14: serial@a98000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0xa98000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_uart14_default>;
|
||||
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c15: i2c@a9c000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0xa9c000 0x4000>;
|
||||
|
|
@ -814,6 +968,17 @@
|
|||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart15: serial@a9c000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0xa9c000 0x4000>;
|
||||
clock-names = "se";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_uart15_default>;
|
||||
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
tcsr_mutex_regs: syscon@1f40000 {
|
||||
|
|
@ -1070,12 +1235,117 @@
|
|||
};
|
||||
};
|
||||
|
||||
qup_uart0_default: qup-uart0-default {
|
||||
pinmux {
|
||||
pins = "gpio2", "gpio3";
|
||||
function = "qup0";
|
||||
};
|
||||
};
|
||||
|
||||
qup_uart1_default: qup-uart1-default {
|
||||
pinmux {
|
||||
pins = "gpio19", "gpio20";
|
||||
function = "qup1";
|
||||
};
|
||||
};
|
||||
|
||||
qup_uart2_default: qup-uart2-default {
|
||||
pinmux {
|
||||
pins = "gpio29", "gpio30";
|
||||
function = "qup2";
|
||||
};
|
||||
};
|
||||
|
||||
qup_uart3_default: qup-uart3-default {
|
||||
pinmux {
|
||||
pins = "gpio43", "gpio44";
|
||||
function = "qup3";
|
||||
};
|
||||
};
|
||||
|
||||
qup_uart4_default: qup-uart4-default {
|
||||
pinmux {
|
||||
pins = "gpio91", "gpio92";
|
||||
function = "qup4";
|
||||
};
|
||||
};
|
||||
|
||||
qup_uart5_default: qup-uart5-default {
|
||||
pinmux {
|
||||
pins = "gpio87", "gpio88";
|
||||
function = "qup5";
|
||||
};
|
||||
};
|
||||
|
||||
qup_uart6_default: qup-uart6-default {
|
||||
pinmux {
|
||||
pins = "gpio47", "gpio48";
|
||||
function = "qup6";
|
||||
};
|
||||
};
|
||||
|
||||
qup_uart7_default: qup-uart7-default {
|
||||
pinmux {
|
||||
pins = "gpio95", "gpio96";
|
||||
function = "qup7";
|
||||
};
|
||||
};
|
||||
|
||||
qup_uart8_default: qup-uart8-default {
|
||||
pinmux {
|
||||
pins = "gpio67", "gpio68";
|
||||
function = "qup8";
|
||||
};
|
||||
};
|
||||
|
||||
qup_uart9_default: qup-uart9-default {
|
||||
pinmux {
|
||||
pins = "gpio4", "gpio5";
|
||||
function = "qup9";
|
||||
};
|
||||
};
|
||||
|
||||
qup_uart10_default: qup-uart10-default {
|
||||
pinmux {
|
||||
pins = "gpio53", "gpio54";
|
||||
function = "qup10";
|
||||
};
|
||||
};
|
||||
|
||||
qup_uart11_default: qup-uart11-default {
|
||||
pinmux {
|
||||
pins = "gpio33", "gpio34";
|
||||
function = "qup11";
|
||||
};
|
||||
};
|
||||
|
||||
qup_uart12_default: qup-uart12-default {
|
||||
pinmux {
|
||||
pins = "gpio51", "gpio52";
|
||||
function = "qup12";
|
||||
};
|
||||
};
|
||||
|
||||
qup_uart13_default: qup-uart13-default {
|
||||
pinmux {
|
||||
pins = "gpio107", "gpio108";
|
||||
function = "qup13";
|
||||
};
|
||||
};
|
||||
|
||||
qup_uart14_default: qup-uart14-default {
|
||||
pinmux {
|
||||
pins = "gpio31", "gpio32";
|
||||
function = "qup14";
|
||||
};
|
||||
};
|
||||
|
||||
qup_uart15_default: qup-uart15-default {
|
||||
pinmux {
|
||||
pins = "gpio83", "gpio84";
|
||||
function = "qup15";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usb_1_hsphy: phy@88e2000 {
|
||||
|
|
|
|||
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