dmaengine: fsl-edma: add ColdFire mcf5441x edma support
This patch adds support for ColdFire mcf5441x-family edma module. The ColdFire edma module is slightly different from fsl-edma, so a new driver is added. But most of the code is common between fsl-edma and mcf-edma so it has been collected into a separate common module fsl-edma-common (patch 1/3). Signed-off-by: Angelo Dureghello <angelo@sysam.it> Tested-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Angelo Dureghello
Vinod Koul
Родитель
4d6d3a90e4
Коммит
e7a3ff92ea
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@ -321,6 +321,17 @@ config LPC18XX_DMAMUX
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Enable support for DMA on NXP LPC18xx/43xx platforms
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with PL080 and multiplexed DMA request lines.
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config MCF_EDMA
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tristate "Freescale eDMA engine support, ColdFire mcf5441x SoCs"
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depends on M5441x || COMPILE_TEST
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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help
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Support the Freescale ColdFire eDMA engine, 64-channel
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implementation that performs complex data transfers with
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minimal intervention from a host processor.
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This module can be found on Freescale ColdFire mcf5441x SoCs.
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config MMP_PDMA
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bool "MMP PDMA support"
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depends on ARCH_MMP || ARCH_PXA || COMPILE_TEST
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@ -32,6 +32,7 @@ obj-$(CONFIG_DW_DMAC_CORE) += dw/
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obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
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obj-$(CONFIG_FSL_DMA) += fsldma.o
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obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o
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obj-$(CONFIG_MCF_EDMA) += mcf-edma.o fsl-edma-common.o
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obj-$(CONFIG_FSL_RAID) += fsl_raid.o
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obj-$(CONFIG_HSU_DMA) += hsu/
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obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o
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@ -46,8 +46,16 @@ static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan)
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struct edma_regs *regs = &fsl_chan->edma->regs;
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u32 ch = fsl_chan->vchan.chan.chan_id;
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if (fsl_chan->edma->version == v1) {
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edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei);
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edma_writeb(fsl_chan->edma, ch, regs->serq);
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} else {
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/* ColdFire is big endian, and accesses natively
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* big endian I/O peripherals
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*/
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iowrite8(EDMA_SEEI_SEEI(ch), regs->seei);
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iowrite8(ch, regs->serq);
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}
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}
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void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan)
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@ -55,8 +63,16 @@ void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan)
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struct edma_regs *regs = &fsl_chan->edma->regs;
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u32 ch = fsl_chan->vchan.chan.chan_id;
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if (fsl_chan->edma->version == v1) {
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edma_writeb(fsl_chan->edma, ch, regs->cerq);
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edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei);
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} else {
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/* ColdFire is big endian, and accesses natively
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* big endian I/O peripherals
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*/
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iowrite8(ch, regs->cerq);
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iowrite8(EDMA_CEEI_CEEI(ch), regs->ceei);
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}
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}
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EXPORT_SYMBOL_GPL(fsl_edma_disable_request);
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@ -0,0 +1,317 @@
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// SPDX-License-Identifier: GPL-2.0+
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//
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// Copyright (c) 2013-2014 Freescale Semiconductor, Inc
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// Copyright (c) 2017 Sysam, Angelo Dureghello <angelo@sysam.it>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/dmaengine.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/dma-mcf-edma.h>
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#include "fsl-edma-common.h"
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#define EDMA_CHANNELS 64
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#define EDMA_MASK_CH(x) ((x) & GENMASK(5, 0))
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static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id)
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{
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struct fsl_edma_engine *mcf_edma = dev_id;
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struct edma_regs *regs = &mcf_edma->regs;
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unsigned int ch;
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struct fsl_edma_chan *mcf_chan;
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u64 intmap;
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intmap = ioread32(regs->inth);
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intmap <<= 32;
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intmap |= ioread32(regs->intl);
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if (!intmap)
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return IRQ_NONE;
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for (ch = 0; ch < mcf_edma->n_chans; ch++) {
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if (intmap & BIT(ch)) {
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iowrite8(EDMA_MASK_CH(ch), regs->cint);
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mcf_chan = &mcf_edma->chans[ch];
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spin_lock(&mcf_chan->vchan.lock);
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if (!mcf_chan->edesc->iscyclic) {
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list_del(&mcf_chan->edesc->vdesc.node);
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vchan_cookie_complete(&mcf_chan->edesc->vdesc);
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mcf_chan->edesc = NULL;
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mcf_chan->status = DMA_COMPLETE;
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mcf_chan->idle = true;
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} else {
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vchan_cyclic_callback(&mcf_chan->edesc->vdesc);
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}
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if (!mcf_chan->edesc)
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fsl_edma_xfer_desc(mcf_chan);
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spin_unlock(&mcf_chan->vchan.lock);
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}
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}
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return IRQ_HANDLED;
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}
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static irqreturn_t mcf_edma_err_handler(int irq, void *dev_id)
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{
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struct fsl_edma_engine *mcf_edma = dev_id;
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struct edma_regs *regs = &mcf_edma->regs;
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unsigned int err, ch;
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err = ioread32(regs->errl);
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if (!err)
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return IRQ_NONE;
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for (ch = 0; ch < (EDMA_CHANNELS / 2); ch++) {
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if (err & BIT(ch)) {
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fsl_edma_disable_request(&mcf_edma->chans[ch]);
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iowrite8(EDMA_CERR_CERR(ch), regs->cerr);
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mcf_edma->chans[ch].status = DMA_ERROR;
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mcf_edma->chans[ch].idle = true;
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}
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}
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err = ioread32(regs->errh);
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if (!err)
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return IRQ_NONE;
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for (ch = (EDMA_CHANNELS / 2); ch < EDMA_CHANNELS; ch++) {
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if (err & (BIT(ch - (EDMA_CHANNELS / 2)))) {
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fsl_edma_disable_request(&mcf_edma->chans[ch]);
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iowrite8(EDMA_CERR_CERR(ch), regs->cerr);
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mcf_edma->chans[ch].status = DMA_ERROR;
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mcf_edma->chans[ch].idle = true;
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}
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}
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return IRQ_HANDLED;
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}
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static int mcf_edma_irq_init(struct platform_device *pdev,
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struct fsl_edma_engine *mcf_edma)
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{
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int ret = 0, i;
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struct resource *res;
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res = platform_get_resource_byname(pdev,
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IORESOURCE_IRQ, "edma-tx-00-15");
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if (!res)
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return -1;
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for (ret = 0, i = res->start; i <= res->end; ++i)
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ret |= request_irq(i, mcf_edma_tx_handler, 0, "eDMA", mcf_edma);
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if (ret)
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return ret;
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res = platform_get_resource_byname(pdev,
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IORESOURCE_IRQ, "edma-tx-16-55");
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if (!res)
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return -1;
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for (ret = 0, i = res->start; i <= res->end; ++i)
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ret |= request_irq(i, mcf_edma_tx_handler, 0, "eDMA", mcf_edma);
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if (ret)
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return ret;
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ret = platform_get_irq_byname(pdev, "edma-tx-56-63");
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if (ret != -ENXIO) {
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ret = request_irq(ret, mcf_edma_tx_handler,
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0, "eDMA", mcf_edma);
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if (ret)
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return ret;
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}
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ret = platform_get_irq_byname(pdev, "edma-err");
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if (ret != -ENXIO) {
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ret = request_irq(ret, mcf_edma_err_handler,
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0, "eDMA", mcf_edma);
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if (ret)
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return ret;
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}
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return 0;
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}
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static void mcf_edma_irq_free(struct platform_device *pdev,
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struct fsl_edma_engine *mcf_edma)
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{
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int irq;
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struct resource *res;
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res = platform_get_resource_byname(pdev,
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IORESOURCE_IRQ, "edma-tx-00-15");
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if (res) {
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for (irq = res->start; irq <= res->end; irq++)
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free_irq(irq, mcf_edma);
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}
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res = platform_get_resource_byname(pdev,
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IORESOURCE_IRQ, "edma-tx-16-55");
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if (res) {
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for (irq = res->start; irq <= res->end; irq++)
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free_irq(irq, mcf_edma);
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}
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irq = platform_get_irq_byname(pdev, "edma-tx-56-63");
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if (irq != -ENXIO)
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free_irq(irq, mcf_edma);
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irq = platform_get_irq_byname(pdev, "edma-err");
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if (irq != -ENXIO)
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free_irq(irq, mcf_edma);
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}
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static int mcf_edma_probe(struct platform_device *pdev)
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{
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struct mcf_edma_platform_data *pdata;
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struct fsl_edma_engine *mcf_edma;
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struct fsl_edma_chan *mcf_chan;
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struct edma_regs *regs;
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struct resource *res;
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int ret, i, len, chans;
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pdata = dev_get_platdata(&pdev->dev);
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if (!pdata) {
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dev_err(&pdev->dev, "no platform data supplied\n");
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return -EINVAL;
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}
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chans = pdata->dma_channels;
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len = sizeof(*mcf_edma) + sizeof(*mcf_chan) * chans;
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mcf_edma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
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if (!mcf_edma)
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return -ENOMEM;
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mcf_edma->n_chans = chans;
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/* Set up version for ColdFire edma */
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mcf_edma->version = v2;
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mcf_edma->big_endian = 1;
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if (!mcf_edma->n_chans) {
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dev_info(&pdev->dev, "setting default channel number to 64");
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mcf_edma->n_chans = 64;
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}
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mutex_init(&mcf_edma->fsl_edma_mutex);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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mcf_edma->membase = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(mcf_edma->membase))
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return PTR_ERR(mcf_edma->membase);
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fsl_edma_setup_regs(mcf_edma);
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regs = &mcf_edma->regs;
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INIT_LIST_HEAD(&mcf_edma->dma_dev.channels);
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for (i = 0; i < mcf_edma->n_chans; i++) {
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struct fsl_edma_chan *mcf_chan = &mcf_edma->chans[i];
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mcf_chan->edma = mcf_edma;
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mcf_chan->slave_id = i;
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mcf_chan->idle = true;
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mcf_chan->vchan.desc_free = fsl_edma_free_desc;
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vchan_init(&mcf_chan->vchan, &mcf_edma->dma_dev);
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iowrite32(0x0, ®s->tcd[i].csr);
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}
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iowrite32(~0, regs->inth);
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iowrite32(~0, regs->intl);
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ret = mcf_edma_irq_init(pdev, mcf_edma);
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if (ret)
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return ret;
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dma_cap_set(DMA_PRIVATE, mcf_edma->dma_dev.cap_mask);
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dma_cap_set(DMA_SLAVE, mcf_edma->dma_dev.cap_mask);
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dma_cap_set(DMA_CYCLIC, mcf_edma->dma_dev.cap_mask);
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mcf_edma->dma_dev.dev = &pdev->dev;
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mcf_edma->dma_dev.device_alloc_chan_resources =
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fsl_edma_alloc_chan_resources;
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mcf_edma->dma_dev.device_free_chan_resources =
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fsl_edma_free_chan_resources;
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mcf_edma->dma_dev.device_config = fsl_edma_slave_config;
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mcf_edma->dma_dev.device_prep_dma_cyclic =
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fsl_edma_prep_dma_cyclic;
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mcf_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg;
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mcf_edma->dma_dev.device_tx_status = fsl_edma_tx_status;
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mcf_edma->dma_dev.device_pause = fsl_edma_pause;
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mcf_edma->dma_dev.device_resume = fsl_edma_resume;
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mcf_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all;
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mcf_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending;
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mcf_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS;
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mcf_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS;
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mcf_edma->dma_dev.directions =
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BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
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mcf_edma->dma_dev.filter.fn = mcf_edma_filter_fn;
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mcf_edma->dma_dev.filter.map = pdata->slave_map;
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mcf_edma->dma_dev.filter.mapcnt = pdata->slavecnt;
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platform_set_drvdata(pdev, mcf_edma);
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ret = dma_async_device_register(&mcf_edma->dma_dev);
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if (ret) {
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dev_err(&pdev->dev,
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"Can't register Freescale eDMA engine. (%d)\n", ret);
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return ret;
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}
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/* Enable round robin arbitration */
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iowrite32(EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
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return 0;
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}
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static int mcf_edma_remove(struct platform_device *pdev)
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{
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struct fsl_edma_engine *mcf_edma = platform_get_drvdata(pdev);
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mcf_edma_irq_free(pdev, mcf_edma);
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fsl_edma_cleanup_vchan(&mcf_edma->dma_dev);
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dma_async_device_unregister(&mcf_edma->dma_dev);
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return 0;
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}
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static struct platform_driver mcf_edma_driver = {
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.driver = {
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.name = "mcf-edma",
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},
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.probe = mcf_edma_probe,
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.remove = mcf_edma_remove,
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};
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bool mcf_edma_filter_fn(struct dma_chan *chan, void *param)
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{
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if (chan->device->dev->driver == &mcf_edma_driver.driver) {
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struct fsl_edma_chan *mcf_chan = to_fsl_edma_chan(chan);
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return (mcf_chan->slave_id == (u32)param);
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}
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return false;
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}
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EXPORT_SYMBOL(mcf_edma_filter_fn);
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static int __init mcf_edma_init(void)
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{
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return platform_driver_register(&mcf_edma_driver);
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}
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subsys_initcall(mcf_edma_init);
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static void __exit mcf_edma_exit(void)
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{
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platform_driver_unregister(&mcf_edma_driver);
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}
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module_exit(mcf_edma_exit);
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MODULE_ALIAS("platform:mcf-edma");
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MODULE_DESCRIPTION("Freescale eDMA engine driver, ColdFire family");
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MODULE_LICENSE("GPL v2");
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@ -0,0 +1,38 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Freescale eDMA platform data, ColdFire SoC's family.
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*
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* Copyright (c) 2017 Angelo Dureghello <angelo@sysam.it>
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*
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* This program is free software; you can redistribute it and/or modify
|
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* it under the terms of the GNU General Public License version 2 as
|
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
|
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*/
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#ifndef __LINUX_PLATFORM_DATA_MCF_EDMA_H__
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#define __LINUX_PLATFORM_DATA_MCF_EDMA_H__
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struct dma_slave_map;
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bool mcf_edma_filter_fn(struct dma_chan *chan, void *param);
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||||
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||||
#define MCF_EDMA_FILTER_PARAM(ch) ((void *)ch)
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/**
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* struct mcf_edma_platform_data - platform specific data for eDMA engine
|
||||
*
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||||
* @ver The eDMA module version.
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* @dma_channels The number of eDMA channels.
|
||||
*/
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struct mcf_edma_platform_data {
|
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int dma_channels;
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const struct dma_slave_map *slave_map;
|
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int slavecnt;
|
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};
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#endif /* __LINUX_PLATFORM_DATA_MCF_EDMA_H__ */
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