Merge branch 'pci/switchtec'
- Add DMA alias quirk for Microsemi Switchtec NTB (Doug Meyer) - Expand documentation for pci_add_dma_alias() (Logan Gunthorpe) * pci/switchtec: PCI: Expand documentation for pci_add_dma_alias() PCI: Add DMA alias quirk for Microsemi Switchtec NTB switchtec: Use generic PCI Vendor ID and Class Code # Conflicts: # drivers/pci/quirks.c
This commit is contained in:
Bjorn Helgaas
Коммит
e7aaf90f9d
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@ -19,6 +19,7 @@
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#include <linux/kthread.h>
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#include <linux/interrupt.h>
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#include <linux/ntb.h>
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#include <linux/pci.h>
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MODULE_DESCRIPTION("Microsemi Switchtec(tm) NTB Driver");
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MODULE_VERSION("0.1");
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@ -1487,7 +1488,7 @@ static int switchtec_ntb_add(struct device *dev,
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stdev->sndev = NULL;
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if (stdev->pdev->class != MICROSEMI_NTB_CLASSCODE)
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if (stdev->pdev->class != (PCI_CLASS_BRIDGE_OTHER << 8))
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return -ENODEV;
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sndev = kzalloc_node(sizeof(*sndev), GFP_KERNEL, dev_to_node(dev));
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@ -5710,8 +5710,19 @@ int pci_set_vga_state(struct pci_dev *dev, bool decode,
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* @dev: the PCI device for which alias is added
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* @devfn: alias slot and function
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*
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* This helper encodes 8-bit devfn as bit number in dma_alias_mask.
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* It should be called early, preferably as PCI fixup header quirk.
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* This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
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* which is used to program permissible bus-devfn source addresses for DMA
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* requests in an IOMMU. These aliases factor into IOMMU group creation
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* and are useful for devices generating DMA requests beyond or different
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* from their logical bus-devfn. Examples include device quirks where the
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* device simply uses the wrong devfn, as well as non-transparent bridges
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* where the alias may be a proxy for devices in another domain.
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*
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* IOMMU group creation is performed during device discovery or addition,
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* prior to any potential DMA mapping and therefore prior to driver probing
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* (especially for userspace assigned devices where IOMMU group definition
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* cannot be left as a userspace activity). DMA aliases should therefore
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* be configured via quirks, such as the PCI fixup header quirk.
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*/
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void pci_add_dma_alias(struct pci_dev *dev, u8 devfn)
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{
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@ -27,6 +27,7 @@
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#include <linux/mm.h>
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#include <linux/platform_data/x86/apple.h>
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#include <linux/pm_runtime.h>
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#include <linux/switchtec.h>
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#include <asm/dma.h> /* isa_dma_bridge_buggy */
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#include "pci.h"
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@ -4862,3 +4863,142 @@ int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout)
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return found;
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}
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/*
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* Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
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* NT endpoints via the internal switch fabric. These IDs replace the
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* originating requestor ID TLPs which access host memory on peer NTB
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* ports. Therefore, all proxy IDs must be aliased to the NTB device
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* to permit access when the IOMMU is turned on.
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*/
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static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev)
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{
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void __iomem *mmio;
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struct ntb_info_regs __iomem *mmio_ntb;
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struct ntb_ctrl_regs __iomem *mmio_ctrl;
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struct sys_info_regs __iomem *mmio_sys_info;
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u64 partition_map;
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u8 partition;
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int pp;
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if (pci_enable_device(pdev)) {
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pci_err(pdev, "Cannot enable Switchtec device\n");
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return;
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}
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mmio = pci_iomap(pdev, 0, 0);
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if (mmio == NULL) {
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pci_disable_device(pdev);
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pci_err(pdev, "Cannot iomap Switchtec device\n");
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return;
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}
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pci_info(pdev, "Setting Switchtec proxy ID aliases\n");
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mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET;
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mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET;
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mmio_sys_info = mmio + SWITCHTEC_GAS_SYS_INFO_OFFSET;
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partition = ioread8(&mmio_ntb->partition_id);
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partition_map = ioread32(&mmio_ntb->ep_map);
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partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32;
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partition_map &= ~(1ULL << partition);
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for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) {
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struct ntb_ctrl_regs __iomem *mmio_peer_ctrl;
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u32 table_sz = 0;
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int te;
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if (!(partition_map & (1ULL << pp)))
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continue;
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pci_dbg(pdev, "Processing partition %d\n", pp);
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mmio_peer_ctrl = &mmio_ctrl[pp];
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table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size);
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if (!table_sz) {
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pci_warn(pdev, "Partition %d table_sz 0\n", pp);
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continue;
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}
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if (table_sz > 512) {
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pci_warn(pdev,
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"Invalid Switchtec partition %d table_sz %d\n",
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pp, table_sz);
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continue;
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}
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for (te = 0; te < table_sz; te++) {
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u32 rid_entry;
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u8 devfn;
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rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]);
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devfn = (rid_entry >> 1) & 0xFF;
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pci_dbg(pdev,
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"Aliasing Partition %d Proxy ID %02x.%d\n",
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pp, PCI_SLOT(devfn), PCI_FUNC(devfn));
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pci_add_dma_alias(pdev, devfn);
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}
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}
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pci_iounmap(pdev, mmio);
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pci_disable_device(pdev);
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8531,
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quirk_switchtec_ntb_dma_alias);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8532,
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quirk_switchtec_ntb_dma_alias);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8533,
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quirk_switchtec_ntb_dma_alias);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8534,
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quirk_switchtec_ntb_dma_alias);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8535,
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quirk_switchtec_ntb_dma_alias);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8536,
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quirk_switchtec_ntb_dma_alias);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8543,
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quirk_switchtec_ntb_dma_alias);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8544,
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quirk_switchtec_ntb_dma_alias);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8545,
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quirk_switchtec_ntb_dma_alias);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8546,
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quirk_switchtec_ntb_dma_alias);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8551,
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quirk_switchtec_ntb_dma_alias);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8552,
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quirk_switchtec_ntb_dma_alias);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8553,
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quirk_switchtec_ntb_dma_alias);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8554,
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quirk_switchtec_ntb_dma_alias);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8555,
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quirk_switchtec_ntb_dma_alias);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8556,
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quirk_switchtec_ntb_dma_alias);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8561,
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quirk_switchtec_ntb_dma_alias);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8562,
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quirk_switchtec_ntb_dma_alias);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8563,
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quirk_switchtec_ntb_dma_alias);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8564,
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quirk_switchtec_ntb_dma_alias);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8565,
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quirk_switchtec_ntb_dma_alias);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8566,
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quirk_switchtec_ntb_dma_alias);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8571,
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quirk_switchtec_ntb_dma_alias);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8572,
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quirk_switchtec_ntb_dma_alias);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8573,
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quirk_switchtec_ntb_dma_alias);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8574,
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quirk_switchtec_ntb_dma_alias);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8575,
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quirk_switchtec_ntb_dma_alias);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8576,
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quirk_switchtec_ntb_dma_alias);
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@ -641,7 +641,7 @@ static int ioctl_event_summary(struct switchtec_dev *stdev,
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for (i = 0; i < SWITCHTEC_MAX_PFF_CSR; i++) {
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reg = ioread16(&stdev->mmio_pff_csr[i].vendor_id);
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if (reg != MICROSEMI_VENDOR_ID)
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if (reg != PCI_VENDOR_ID_MICROSEMI)
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break;
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reg = ioread32(&stdev->mmio_pff_csr[i].pff_event_summary);
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@ -1203,7 +1203,7 @@ static void init_pff(struct switchtec_dev *stdev)
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for (i = 0; i < SWITCHTEC_MAX_PFF_CSR; i++) {
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reg = ioread16(&stdev->mmio_pff_csr[i].vendor_id);
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if (reg != MICROSEMI_VENDOR_ID)
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if (reg != PCI_VENDOR_ID_MICROSEMI)
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break;
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}
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@ -1267,7 +1267,7 @@ static int switchtec_pci_probe(struct pci_dev *pdev,
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struct switchtec_dev *stdev;
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int rc;
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if (pdev->class == MICROSEMI_NTB_CLASSCODE)
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if (pdev->class == (PCI_CLASS_BRIDGE_OTHER << 8))
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request_module_nowait("ntb_hw_switchtec");
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stdev = stdev_create(pdev);
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@ -1321,19 +1321,19 @@ static void switchtec_pci_remove(struct pci_dev *pdev)
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#define SWITCHTEC_PCI_DEVICE(device_id) \
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{ \
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.vendor = MICROSEMI_VENDOR_ID, \
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.vendor = PCI_VENDOR_ID_MICROSEMI, \
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.device = device_id, \
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.subvendor = PCI_ANY_ID, \
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.subdevice = PCI_ANY_ID, \
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.class = MICROSEMI_MGMT_CLASSCODE, \
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.class = (PCI_CLASS_MEMORY_OTHER << 8), \
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.class_mask = 0xFFFFFFFF, \
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}, \
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{ \
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.vendor = MICROSEMI_VENDOR_ID, \
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.vendor = PCI_VENDOR_ID_MICROSEMI, \
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.device = device_id, \
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.subvendor = PCI_ANY_ID, \
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.subdevice = PCI_ANY_ID, \
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.class = MICROSEMI_NTB_CLASSCODE, \
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.class = (PCI_CLASS_BRIDGE_OTHER << 8), \
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.class_mask = 0xFFFFFFFF, \
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}
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@ -1668,6 +1668,7 @@
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#define PCI_DEVICE_ID_COMPEX_ENET100VG4 0x0112
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#define PCI_VENDOR_ID_PMC_Sierra 0x11f8
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#define PCI_VENDOR_ID_MICROSEMI 0x11f8
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#define PCI_VENDOR_ID_RP 0x11fe
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#define PCI_DEVICE_ID_RP32INTF 0x0001
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@ -19,10 +19,6 @@
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#include <linux/pci.h>
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#include <linux/cdev.h>
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#define MICROSEMI_VENDOR_ID 0x11f8
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#define MICROSEMI_NTB_CLASSCODE 0x068000
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#define MICROSEMI_MGMT_CLASSCODE 0x058000
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#define SWITCHTEC_MRPC_PAYLOAD_SIZE 1024
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#define SWITCHTEC_MAX_PFF_CSR 48
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