powerpc/cache: add cache flush operation for various e500
Various e500 core have different cache architecture, so they need different cache flush operations. Therefore, add a callback function cpu_flush_caches to the struct cpu_spec. The cache flush operation for the specific kind of e500 is selected at init time. The callback function will flush all caches inside the current cpu. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Signed-off-by: Tang Yuantian <Yuantian.Tang@feescale.com> Signed-off-by: Scott Wood <oss@buserror.net>
This commit is contained in:
chenhui zhao
Scott Wood
Родитель
ebb9d30a6a
Коммит
e7affb1dba
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@ -30,8 +30,6 @@ extern void flush_dcache_page(struct page *page);
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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extern void __flush_disable_L1(void);
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extern void flush_icache_range(unsigned long, unsigned long);
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extern void flush_icache_user_range(struct vm_area_struct *vma,
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struct page *page, unsigned long addr,
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@ -43,6 +43,11 @@ extern int machine_check_e500(struct pt_regs *regs);
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extern int machine_check_e200(struct pt_regs *regs);
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extern int machine_check_47x(struct pt_regs *regs);
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extern void cpu_down_flush_e500v2(void);
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extern void cpu_down_flush_e500mc(void);
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extern void cpu_down_flush_e5500(void);
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extern void cpu_down_flush_e6500(void);
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/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
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struct cpu_spec {
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/* CPU is matched via (PVR & pvr_mask) == pvr_value */
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@ -59,6 +64,9 @@ struct cpu_spec {
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unsigned int icache_bsize;
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unsigned int dcache_bsize;
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/* flush caches inside the current cpu */
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void (*cpu_down_flush)(void);
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/* number of performance monitor counters */
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unsigned int num_pmcs;
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enum powerpc_pmc_type pmc_type;
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@ -376,6 +376,7 @@ int main(void)
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DEFINE(CPU_SPEC_FEATURES, offsetof(struct cpu_spec, cpu_features));
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DEFINE(CPU_SPEC_SETUP, offsetof(struct cpu_spec, cpu_setup));
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DEFINE(CPU_SPEC_RESTORE, offsetof(struct cpu_spec, cpu_restore));
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DEFINE(CPU_DOWN_FLUSH, offsetof(struct cpu_spec, cpu_down_flush));
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DEFINE(pbe_address, offsetof(struct pbe, address));
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DEFINE(pbe_orig_address, offsetof(struct pbe, orig_address));
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@ -13,11 +13,13 @@
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*
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*/
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#include <asm/page.h>
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#include <asm/processor.h>
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#include <asm/cputable.h>
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#include <asm/ppc_asm.h>
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#include <asm/mmu-book3e.h>
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#include <asm/asm-offsets.h>
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#include <asm/mpc85xx.h>
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_GLOBAL(__e500_icache_setup)
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mfspr r0, SPRN_L1CSR1
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@ -233,3 +235,113 @@ _GLOBAL(__setup_cpu_e5500)
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mtlr r5
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blr
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#endif
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/* flush L1 date cache, it can apply to e500v2, e500mc and e5500 */
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_GLOBAL(flush_dcache_L1)
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mfmsr r10
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wrteei 0
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mfspr r3,SPRN_L1CFG0
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rlwinm r5,r3,9,3 /* Extract cache block size */
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twlgti r5,1 /* Only 32 and 64 byte cache blocks
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* are currently defined.
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*/
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li r4,32
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subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
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* log2(number of ways)
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*/
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slw r5,r4,r5 /* r5 = cache block size */
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rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
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mulli r7,r7,13 /* An 8-way cache will require 13
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* loads per set.
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*/
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slw r7,r7,r6
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/* save off HID0 and set DCFA */
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mfspr r8,SPRN_HID0
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ori r9,r8,HID0_DCFA@l
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mtspr SPRN_HID0,r9
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isync
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LOAD_REG_IMMEDIATE(r6, KERNELBASE)
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mr r4, r6
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mtctr r7
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1: lwz r3,0(r4) /* Load... */
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add r4,r4,r5
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bdnz 1b
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msync
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mr r4, r6
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mtctr r7
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1: dcbf 0,r4 /* ...and flush. */
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add r4,r4,r5
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bdnz 1b
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/* restore HID0 */
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mtspr SPRN_HID0,r8
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isync
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wrtee r10
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blr
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has_L2_cache:
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/* skip L2 cache on P2040/P2040E as they have no L2 cache */
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mfspr r3, SPRN_SVR
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/* shift right by 8 bits and clear E bit of SVR */
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rlwinm r4, r3, 24, ~0x800
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lis r3, SVR_P2040@h
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ori r3, r3, SVR_P2040@l
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cmpw r4, r3
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beq 1f
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li r3, 1
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blr
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1:
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li r3, 0
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blr
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/* flush backside L2 cache */
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flush_backside_L2_cache:
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mflr r10
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bl has_L2_cache
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mtlr r10
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cmpwi r3, 0
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beq 2f
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/* Flush the L2 cache */
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mfspr r3, SPRN_L2CSR0
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ori r3, r3, L2CSR0_L2FL@l
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msync
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isync
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mtspr SPRN_L2CSR0,r3
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isync
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/* check if it is complete */
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1: mfspr r3,SPRN_L2CSR0
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andi. r3, r3, L2CSR0_L2FL@l
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bne 1b
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2:
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blr
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_GLOBAL(cpu_down_flush_e500v2)
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mflr r0
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bl flush_dcache_L1
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mtlr r0
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blr
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_GLOBAL(cpu_down_flush_e500mc)
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_GLOBAL(cpu_down_flush_e5500)
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mflr r0
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bl flush_dcache_L1
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bl flush_backside_L2_cache
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mtlr r0
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blr
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/* L1 Data Cache of e6500 contains no modified data, no flush is required */
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_GLOBAL(cpu_down_flush_e6500)
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blr
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@ -2050,6 +2050,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.cpu_setup = __setup_cpu_e500v2,
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.machine_check = machine_check_e500,
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.platform = "ppc8548",
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.cpu_down_flush = cpu_down_flush_e500v2,
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},
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#else
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{ /* e500mc */
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@ -2069,6 +2070,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.cpu_setup = __setup_cpu_e500mc,
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.machine_check = machine_check_e500mc,
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.platform = "ppce500mc",
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.cpu_down_flush = cpu_down_flush_e500mc,
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},
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#endif /* CONFIG_PPC_E500MC */
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#endif /* CONFIG_PPC32 */
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@ -2093,6 +2095,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
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#endif
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.machine_check = machine_check_e500mc,
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.platform = "ppce5500",
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.cpu_down_flush = cpu_down_flush_e5500,
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},
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{ /* e6500 */
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.pvr_mask = 0xffff0000,
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@ -2115,6 +2118,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
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#endif
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.machine_check = machine_check_e500mc,
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.platform = "ppce6500",
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.cpu_down_flush = cpu_down_flush_e6500,
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},
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#endif /* CONFIG_PPC_E500MC */
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#ifdef CONFIG_PPC32
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@ -1037,80 +1037,6 @@ _GLOBAL(set_context)
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isync /* Force context change */
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blr
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_GLOBAL(flush_dcache_L1)
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mfspr r3,SPRN_L1CFG0
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rlwinm r5,r3,9,3 /* Extract cache block size */
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twlgti r5,1 /* Only 32 and 64 byte cache blocks
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* are currently defined.
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*/
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li r4,32
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subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
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* log2(number of ways)
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*/
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slw r5,r4,r5 /* r5 = cache block size */
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rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
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mulli r7,r7,13 /* An 8-way cache will require 13
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* loads per set.
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*/
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slw r7,r7,r6
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/* save off HID0 and set DCFA */
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mfspr r8,SPRN_HID0
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ori r9,r8,HID0_DCFA@l
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mtspr SPRN_HID0,r9
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isync
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lis r4,KERNELBASE@h
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mtctr r7
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1: lwz r3,0(r4) /* Load... */
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add r4,r4,r5
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bdnz 1b
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msync
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lis r4,KERNELBASE@h
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mtctr r7
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1: dcbf 0,r4 /* ...and flush. */
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add r4,r4,r5
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bdnz 1b
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/* restore HID0 */
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mtspr SPRN_HID0,r8
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isync
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blr
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/* Flush L1 d-cache, invalidate and disable d-cache and i-cache */
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_GLOBAL(__flush_disable_L1)
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mflr r10
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bl flush_dcache_L1 /* Flush L1 d-cache */
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mtlr r10
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mfspr r4, SPRN_L1CSR0 /* Invalidate and disable d-cache */
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li r5, 2
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rlwimi r4, r5, 0, 3
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msync
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isync
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mtspr SPRN_L1CSR0, r4
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isync
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1: mfspr r4, SPRN_L1CSR0 /* Wait for the invalidate to finish */
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andi. r4, r4, 2
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bne 1b
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mfspr r4, SPRN_L1CSR1 /* Invalidate and disable i-cache */
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li r5, 2
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rlwimi r4, r5, 0, 3
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mtspr SPRN_L1CSR1, r4
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isync
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blr
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#ifdef CONFIG_SMP
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/* When we get here, r24 needs to hold the CPU # */
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.globl __secondary_start
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@ -139,7 +139,8 @@ static void smp_85xx_mach_cpu_die(void)
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mtspr(SPRN_TCR, 0);
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__flush_disable_L1();
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cur_cpu_spec->cpu_down_flush();
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tmp = (mfspr(SPRN_HID0) & ~(HID0_DOZE|HID0_SLEEP)) | HID0_NAP;
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mtspr(SPRN_HID0, tmp);
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isync();
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@ -359,7 +360,7 @@ void mpc85xx_smp_kexec_cpu_down(int crash_shutdown, int secondary)
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local_irq_disable();
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if (secondary) {
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__flush_disable_L1();
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cur_cpu_spec->cpu_down_flush();
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atomic_inc(&kexec_down_cpus);
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/* loop forever */
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while (1);
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