x86/speculation: Use synthetic bits for IBRS/IBPB/STIBP
Intel and AMD have different CPUID bits hence for those use synthetic bits
which get set on the respective vendor's in init_speculation_control(). So
that debacles like what the commit message of
c65732e4f7 ("x86/cpu: Restore CPUID_8000_0008_EBX reload")
talks about don't happen anymore.
Signed-off-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Tested-by: Jörg Otte <jrg.otte@gmail.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Link: https://lkml.kernel.org/r/20180504161815.GG9257@pd.tnic
This commit is contained in:
Borislav Petkov
Thomas Gleixner
Родитель
15e6c22fd8
Коммит
e7c587da12
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@ -198,7 +198,6 @@
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#define X86_FEATURE_CAT_L2 ( 7*32+ 5) /* Cache Allocation Technology L2 */
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#define X86_FEATURE_CDP_L3 ( 7*32+ 6) /* Code and Data Prioritization L3 */
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#define X86_FEATURE_INVPCID_SINGLE ( 7*32+ 7) /* Effectively INVPCID && CR4.PCIDE=1 */
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#define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */
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#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
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#define X86_FEATURE_SME ( 7*32+10) /* AMD Secure Memory Encryption */
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@ -216,6 +215,9 @@
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#define X86_FEATURE_USE_IBRS_FW ( 7*32+22) /* "" Use IBRS during runtime firmware calls */
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#define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23) /* "" Disable Speculative Store Bypass. */
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#define X86_FEATURE_AMD_SSBD ( 7*32+24) /* "" AMD SSBD implementation */
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#define X86_FEATURE_IBRS ( 7*32+25) /* Indirect Branch Restricted Speculation */
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#define X86_FEATURE_IBPB ( 7*32+26) /* Indirect Branch Prediction Barrier */
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#define X86_FEATURE_STIBP ( 7*32+27) /* Single Thread Indirect Branch Predictors */
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/* Virtualization flags: Linux defined, word 8 */
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#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
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@ -276,9 +278,9 @@
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#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
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#define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */
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#define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */
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#define X86_FEATURE_IBPB (13*32+12) /* Indirect Branch Prediction Barrier */
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#define X86_FEATURE_IBRS (13*32+14) /* Indirect Branch Restricted Speculation */
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#define X86_FEATURE_STIBP (13*32+15) /* Single Thread Indirect Branch Predictors */
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#define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */
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#define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */
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#define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */
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/* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
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#define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */
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@ -757,17 +757,23 @@ static void init_speculation_control(struct cpuinfo_x86 *c)
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* and they also have a different bit for STIBP support. Also,
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* a hypervisor might have set the individual AMD bits even on
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* Intel CPUs, for finer-grained selection of what's available.
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*
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* We use the AMD bits in 0x8000_0008 EBX as the generic hardware
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* features, which are visible in /proc/cpuinfo and used by the
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* kernel. So set those accordingly from the Intel bits.
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*/
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if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
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set_cpu_cap(c, X86_FEATURE_IBRS);
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set_cpu_cap(c, X86_FEATURE_IBPB);
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}
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if (cpu_has(c, X86_FEATURE_INTEL_STIBP))
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set_cpu_cap(c, X86_FEATURE_STIBP);
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if (cpu_has(c, X86_FEATURE_AMD_IBRS))
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set_cpu_cap(c, X86_FEATURE_IBRS);
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if (cpu_has(c, X86_FEATURE_AMD_IBPB))
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set_cpu_cap(c, X86_FEATURE_IBPB);
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if (cpu_has(c, X86_FEATURE_AMD_STIBP))
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set_cpu_cap(c, X86_FEATURE_STIBP);
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}
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void get_cpu_cap(struct cpuinfo_x86 *c)
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@ -379,7 +379,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
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/* cpuid 0x80000008.ebx */
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const u32 kvm_cpuid_8000_0008_ebx_x86_features =
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F(IBPB) | F(IBRS);
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F(AMD_IBPB) | F(AMD_IBRS);
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/* cpuid 0xC0000001.edx */
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const u32 kvm_cpuid_C000_0001_edx_x86_features =
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@ -648,10 +648,10 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
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entry->eax = g_phys_as | (virt_as << 8);
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entry->edx = 0;
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/* IBRS and IBPB aren't necessarily present in hardware cpuid */
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if (boot_cpu_has(X86_FEATURE_IBPB))
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entry->ebx |= F(IBPB);
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if (boot_cpu_has(X86_FEATURE_IBRS))
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entry->ebx |= F(IBRS);
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if (boot_cpu_has(X86_FEATURE_AMD_IBPB))
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entry->ebx |= F(AMD_IBPB);
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if (boot_cpu_has(X86_FEATURE_AMD_IBRS))
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entry->ebx |= F(AMD_IBRS);
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entry->ebx &= kvm_cpuid_8000_0008_ebx_x86_features;
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cpuid_mask(&entry->ebx, CPUID_8000_0008_EBX);
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break;
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@ -4108,7 +4108,7 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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break;
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case MSR_IA32_SPEC_CTRL:
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if (!msr_info->host_initiated &&
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!guest_cpuid_has(vcpu, X86_FEATURE_IBRS))
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!guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS))
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return 1;
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msr_info->data = svm->spec_ctrl;
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@ -4203,7 +4203,7 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
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break;
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case MSR_IA32_SPEC_CTRL:
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if (!msr->host_initiated &&
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!guest_cpuid_has(vcpu, X86_FEATURE_IBRS))
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!guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS))
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return 1;
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/* The STIBP bit doesn't fault even if it's not advertised */
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@ -4230,7 +4230,7 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
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break;
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case MSR_IA32_PRED_CMD:
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if (!msr->host_initiated &&
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!guest_cpuid_has(vcpu, X86_FEATURE_IBPB))
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!guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
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return 1;
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if (data & ~PRED_CMD_IBPB)
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@ -3523,9 +3523,7 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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return kvm_get_msr_common(vcpu, msr_info);
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case MSR_IA32_SPEC_CTRL:
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if (!msr_info->host_initiated &&
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!guest_cpuid_has(vcpu, X86_FEATURE_IBRS) &&
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!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
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!guest_cpuid_has(vcpu, X86_FEATURE_SSBD))
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!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
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return 1;
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msr_info->data = to_vmx(vcpu)->spec_ctrl;
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@ -3643,9 +3641,7 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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break;
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case MSR_IA32_SPEC_CTRL:
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if (!msr_info->host_initiated &&
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!guest_cpuid_has(vcpu, X86_FEATURE_IBRS) &&
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!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
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!guest_cpuid_has(vcpu, X86_FEATURE_SSBD))
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!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
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return 1;
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/* The STIBP bit doesn't fault even if it's not advertised */
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@ -3675,7 +3671,6 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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break;
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case MSR_IA32_PRED_CMD:
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if (!msr_info->host_initiated &&
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!guest_cpuid_has(vcpu, X86_FEATURE_IBPB) &&
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!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
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return 1;
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