serial: mxs-auart: add the DMA support for mx28
Only we meet the following conditions, we can enable the DMA support for
auart:
(1) We enable the DMA support in the dts file, such as
arch/arm/boot/dts/imx28.dtsi.
(2) We enable the hardware flow control.
(3) We use the mx28, not the mx23. Due to hardware bug(see errata: 2836),
we can not add the DMA support to mx23.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Huang Shijie
Greg Kroah-Hartman
Родитель
f4b1f03b82
Коммит
e800163281
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@ -6,11 +6,19 @@ Required properties:
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- reg : Address and length of the register set for the device
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- interrupts : Should contain the auart interrupt numbers
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Optional properties:
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- fsl,auart-dma-channel : The DMA channels, the first is for RX, the other
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is for TX. If you add this property, it also means that you
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will enable the DMA support for the auart.
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Note: due to the hardware bug in imx23(see errata : 2836),
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only the imx28 can enable the DMA support for the auart.
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Example:
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auart0: serial@8006a000 {
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compatible = "fsl,imx28-auart", "fsl,imx23-auart";
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reg = <0x8006a000 0x2000>;
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interrupts = <112 70 71>;
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fsl,auart-dma-channel = <8 9>;
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};
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Note: Each auart port should have an alias correctly numbered in "aliases"
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@ -34,6 +34,8 @@
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#include <linux/io.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/of_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/fsl/mxs-dma.h>
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#include <asm/cacheflush.h>
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@ -71,6 +73,15 @@
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#define AUART_CTRL0_SFTRST (1 << 31)
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#define AUART_CTRL0_CLKGATE (1 << 30)
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#define AUART_CTRL0_RXTO_ENABLE (1 << 27)
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#define AUART_CTRL0_RXTIMEOUT(v) (((v) & 0x7ff) << 16)
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#define AUART_CTRL0_XFER_COUNT(v) ((v) & 0xffff)
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#define AUART_CTRL1_XFER_COUNT(v) ((v) & 0xffff)
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#define AUART_CTRL2_DMAONERR (1 << 26)
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#define AUART_CTRL2_TXDMAE (1 << 25)
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#define AUART_CTRL2_RXDMAE (1 << 24)
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#define AUART_CTRL2_CTSEN (1 << 15)
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#define AUART_CTRL2_RTSEN (1 << 14)
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@ -111,6 +122,7 @@
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#define AUART_STAT_BERR (1 << 18)
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#define AUART_STAT_PERR (1 << 17)
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#define AUART_STAT_FERR (1 << 16)
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#define AUART_STAT_RXCOUNT_MASK 0xffff
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static struct uart_driver auart_driver;
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@ -122,7 +134,11 @@ enum mxs_auart_type {
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struct mxs_auart_port {
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struct uart_port port;
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unsigned int flags;
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#define MXS_AUART_DMA_CONFIG 0x1
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#define MXS_AUART_DMA_ENABLED 0x2
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#define MXS_AUART_DMA_TX_SYNC 2 /* bit 2 */
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#define MXS_AUART_DMA_RX_READY 3 /* bit 3 */
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unsigned long flags;
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unsigned int ctrl;
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enum mxs_auart_type devtype;
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@ -130,6 +146,20 @@ struct mxs_auart_port {
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struct clk *clk;
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struct device *dev;
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/* for DMA */
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struct mxs_dma_data dma_data;
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int dma_channel_rx, dma_channel_tx;
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int dma_irq_rx, dma_irq_tx;
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int dma_channel;
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struct scatterlist tx_sgl;
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struct dma_chan *tx_dma_chan;
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void *tx_dma_buf;
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struct scatterlist rx_sgl;
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struct dma_chan *rx_dma_chan;
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void *rx_dma_buf;
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};
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static struct platform_device_id mxs_auart_devtype[] = {
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@ -155,14 +185,107 @@ static inline int is_imx28_auart(struct mxs_auart_port *s)
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return s->devtype == IMX28_AUART;
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}
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static inline bool auart_dma_enabled(struct mxs_auart_port *s)
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{
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return s->flags & MXS_AUART_DMA_ENABLED;
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}
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static void mxs_auart_stop_tx(struct uart_port *u);
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#define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
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static inline void mxs_auart_tx_chars(struct mxs_auart_port *s)
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static void mxs_auart_tx_chars(struct mxs_auart_port *s);
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static void dma_tx_callback(void *param)
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{
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struct mxs_auart_port *s = param;
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struct circ_buf *xmit = &s->port.state->xmit;
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dma_unmap_sg(s->dev, &s->tx_sgl, 1, DMA_TO_DEVICE);
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/* clear the bit used to serialize the DMA tx. */
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clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
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smp_mb__after_clear_bit();
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/* wake up the possible processes. */
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(&s->port);
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mxs_auart_tx_chars(s);
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}
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static int mxs_auart_dma_tx(struct mxs_auart_port *s, int size)
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{
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struct dma_async_tx_descriptor *desc;
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struct scatterlist *sgl = &s->tx_sgl;
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struct dma_chan *channel = s->tx_dma_chan;
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u32 pio;
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/* [1] : send PIO. Note, the first pio word is CTRL1. */
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pio = AUART_CTRL1_XFER_COUNT(size);
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desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)&pio,
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1, DMA_TRANS_NONE, 0);
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if (!desc) {
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dev_err(s->dev, "step 1 error\n");
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return -EINVAL;
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}
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/* [2] : set DMA buffer. */
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sg_init_one(sgl, s->tx_dma_buf, size);
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dma_map_sg(s->dev, sgl, 1, DMA_TO_DEVICE);
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desc = dmaengine_prep_slave_sg(channel, sgl,
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1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!desc) {
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dev_err(s->dev, "step 2 error\n");
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return -EINVAL;
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}
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/* [3] : submit the DMA */
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desc->callback = dma_tx_callback;
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desc->callback_param = s;
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dmaengine_submit(desc);
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dma_async_issue_pending(channel);
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return 0;
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}
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static void mxs_auart_tx_chars(struct mxs_auart_port *s)
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{
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struct circ_buf *xmit = &s->port.state->xmit;
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if (auart_dma_enabled(s)) {
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int i = 0;
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int size;
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void *buffer = s->tx_dma_buf;
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if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC, &s->flags))
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return;
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while (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
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size = min_t(u32, UART_XMIT_SIZE - i,
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CIRC_CNT_TO_END(xmit->head,
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xmit->tail,
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UART_XMIT_SIZE));
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memcpy(buffer + i, xmit->buf + xmit->tail, size);
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xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1);
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i += size;
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if (i >= UART_XMIT_SIZE)
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break;
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}
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if (uart_tx_stopped(&s->port))
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mxs_auart_stop_tx(&s->port);
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if (i) {
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mxs_auart_dma_tx(s, i);
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} else {
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clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
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smp_mb__after_clear_bit();
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}
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return;
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}
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while (!(readl(s->port.membase + AUART_STAT) &
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AUART_STAT_TXFF)) {
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if (s->port.x_char) {
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@ -316,10 +439,157 @@ static u32 mxs_auart_get_mctrl(struct uart_port *u)
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return mctrl;
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}
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static bool mxs_auart_dma_filter(struct dma_chan *chan, void *param)
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{
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struct mxs_auart_port *s = param;
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if (!mxs_dma_is_apbx(chan))
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return false;
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if (s->dma_channel == chan->chan_id) {
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chan->private = &s->dma_data;
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return true;
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}
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return false;
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}
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static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s);
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static void dma_rx_callback(void *arg)
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{
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struct mxs_auart_port *s = (struct mxs_auart_port *) arg;
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struct tty_struct *tty = s->port.state->port.tty;
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int count;
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u32 stat;
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stat = readl(s->port.membase + AUART_STAT);
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stat &= ~(AUART_STAT_OERR | AUART_STAT_BERR |
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AUART_STAT_PERR | AUART_STAT_FERR);
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count = stat & AUART_STAT_RXCOUNT_MASK;
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tty_insert_flip_string(tty, s->rx_dma_buf, count);
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writel(stat, s->port.membase + AUART_STAT);
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tty_flip_buffer_push(tty);
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/* start the next DMA for RX. */
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mxs_auart_dma_prep_rx(s);
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}
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static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s)
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{
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struct dma_async_tx_descriptor *desc;
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struct scatterlist *sgl = &s->rx_sgl;
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struct dma_chan *channel = s->rx_dma_chan;
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u32 pio[1];
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/* [1] : send PIO */
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pio[0] = AUART_CTRL0_RXTO_ENABLE
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| AUART_CTRL0_RXTIMEOUT(0x80)
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| AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE);
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desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio,
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1, DMA_TRANS_NONE, 0);
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if (!desc) {
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dev_err(s->dev, "step 1 error\n");
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return -EINVAL;
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}
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/* [2] : send DMA request */
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sg_init_one(sgl, s->rx_dma_buf, UART_XMIT_SIZE);
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dma_map_sg(s->dev, sgl, 1, DMA_FROM_DEVICE);
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desc = dmaengine_prep_slave_sg(channel, sgl, 1, DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!desc) {
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dev_err(s->dev, "step 2 error\n");
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return -1;
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}
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/* [3] : submit the DMA, but do not issue it. */
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desc->callback = dma_rx_callback;
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desc->callback_param = s;
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dmaengine_submit(desc);
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dma_async_issue_pending(channel);
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return 0;
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}
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static void mxs_auart_dma_exit_channel(struct mxs_auart_port *s)
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{
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if (s->tx_dma_chan) {
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dma_release_channel(s->tx_dma_chan);
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s->tx_dma_chan = NULL;
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}
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if (s->rx_dma_chan) {
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dma_release_channel(s->rx_dma_chan);
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s->rx_dma_chan = NULL;
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}
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kfree(s->tx_dma_buf);
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kfree(s->rx_dma_buf);
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s->tx_dma_buf = NULL;
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s->rx_dma_buf = NULL;
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}
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static void mxs_auart_dma_exit(struct mxs_auart_port *s)
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{
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writel(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR,
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s->port.membase + AUART_CTRL2_CLR);
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mxs_auart_dma_exit_channel(s);
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s->flags &= ~MXS_AUART_DMA_ENABLED;
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clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
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clear_bit(MXS_AUART_DMA_RX_READY, &s->flags);
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}
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static int mxs_auart_dma_init(struct mxs_auart_port *s)
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{
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dma_cap_mask_t mask;
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if (auart_dma_enabled(s))
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return 0;
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/* We do not get the right DMA channels. */
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if (s->dma_channel_rx == -1 || s->dma_channel_rx == -1)
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return -EINVAL;
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/* init for RX */
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dma_cap_zero(mask);
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dma_cap_set(DMA_SLAVE, mask);
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s->dma_channel = s->dma_channel_rx;
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s->dma_data.chan_irq = s->dma_irq_rx;
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s->rx_dma_chan = dma_request_channel(mask, mxs_auart_dma_filter, s);
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if (!s->rx_dma_chan)
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goto err_out;
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s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
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if (!s->rx_dma_buf)
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goto err_out;
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/* init for TX */
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s->dma_channel = s->dma_channel_tx;
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s->dma_data.chan_irq = s->dma_irq_tx;
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s->tx_dma_chan = dma_request_channel(mask, mxs_auart_dma_filter, s);
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if (!s->tx_dma_chan)
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goto err_out;
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s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
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if (!s->tx_dma_buf)
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goto err_out;
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/* set the flags */
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s->flags |= MXS_AUART_DMA_ENABLED;
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dev_dbg(s->dev, "enabled the DMA support.");
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return 0;
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err_out:
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mxs_auart_dma_exit_channel(s);
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return -EINVAL;
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}
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static void mxs_auart_settermios(struct uart_port *u,
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struct ktermios *termios,
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struct ktermios *old)
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{
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struct mxs_auart_port *s = to_auart_port(u);
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u32 bm, ctrl, ctrl2, div;
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unsigned int cflag, baud;
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@ -391,10 +661,23 @@ static void mxs_auart_settermios(struct uart_port *u,
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ctrl |= AUART_LINECTRL_STP2;
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/* figure out the hardware flow control settings */
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if (cflag & CRTSCTS)
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if (cflag & CRTSCTS) {
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/*
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* The DMA has a bug(see errata:2836) in mx23.
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* So we can not implement the DMA for auart in mx23,
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* we can only implement the DMA support for auart
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* in mx28.
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*/
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if (is_imx28_auart(s) && (s->flags & MXS_AUART_DMA_CONFIG)) {
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if (!mxs_auart_dma_init(s))
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/* enable DMA tranfer */
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ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE
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| AUART_CTRL2_DMAONERR;
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}
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ctrl2 |= AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN;
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else
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} else {
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ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN);
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}
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/* set baud rate */
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baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk);
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@ -406,6 +689,18 @@ static void mxs_auart_settermios(struct uart_port *u,
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writel(ctrl2, u->membase + AUART_CTRL2);
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uart_update_timeout(u, termios->c_cflag, baud);
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/* prepare for the DMA RX. */
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if (auart_dma_enabled(s) &&
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!test_and_set_bit(MXS_AUART_DMA_RX_READY, &s->flags)) {
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if (!mxs_auart_dma_prep_rx(s)) {
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/* Disable the normal RX interrupt. */
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writel(AUART_INTR_RXIEN, u->membase + AUART_INTR_CLR);
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} else {
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mxs_auart_dma_exit(s);
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dev_err(s->dev, "We can not start up the DMA.\n");
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}
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}
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}
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static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
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|
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@ -484,6 +779,9 @@ static void mxs_auart_shutdown(struct uart_port *u)
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{
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struct mxs_auart_port *s = to_auart_port(u);
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|
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if (auart_dma_enabled(s))
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mxs_auart_dma_exit(s);
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writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR);
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writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
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|
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@ -717,6 +1015,7 @@ static int serial_mxs_probe_dt(struct mxs_auart_port *s,
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struct platform_device *pdev)
|
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{
|
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struct device_node *np = pdev->dev.of_node;
|
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u32 dma_channel[2];
|
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int ret;
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|
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if (!np)
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|
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@ -730,6 +1029,20 @@ static int serial_mxs_probe_dt(struct mxs_auart_port *s,
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}
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s->port.line = ret;
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|
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s->dma_irq_rx = platform_get_irq(pdev, 1);
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s->dma_irq_tx = platform_get_irq(pdev, 2);
|
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|
||||
ret = of_property_read_u32_array(np, "fsl,auart-dma-channel",
|
||||
dma_channel, 2);
|
||||
if (ret == 0) {
|
||||
s->dma_channel_rx = dma_channel[0];
|
||||
s->dma_channel_tx = dma_channel[1];
|
||||
|
||||
s->flags |= MXS_AUART_DMA_CONFIG;
|
||||
} else {
|
||||
s->dma_channel_rx = -1;
|
||||
s->dma_channel_tx = -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -787,7 +1100,6 @@ static int __devinit mxs_auart_probe(struct platform_device *pdev)
|
|||
s->port.type = PORT_IMX;
|
||||
s->port.dev = s->dev = get_device(&pdev->dev);
|
||||
|
||||
s->flags = 0;
|
||||
s->ctrl = 0;
|
||||
|
||||
s->irq = platform_get_irq(pdev, 0);
|
||||
|
|
|
|||
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