Merge branch 'timers/hpet' into timers/core
This commit is contained in:
Ingo Molnar
Коммит
e8684605ad
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@ -492,10 +492,12 @@ and is between 256 and 4096 characters. It is defined in the file
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Default: 64
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hpet= [X86-32,HPET] option to control HPET usage
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Format: { enable (default) | disable | force }
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Format: { enable (default) | disable | force |
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verbose }
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disable: disable HPET and use PIT instead
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force: allow force enabled of undocumented chips (ICH4,
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VIA, nVidia)
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verbose: show contents of HPET registers during setup
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com20020= [HW,NET] ARCnet - COM20020 chipset
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Format:
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@ -80,6 +80,7 @@ static inline void hpet_clear_mapping(void)
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*/
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static int boot_hpet_disable;
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int hpet_force_user;
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static int hpet_verbose;
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static int __init hpet_setup(char *str)
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{
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@ -88,6 +89,8 @@ static int __init hpet_setup(char *str)
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boot_hpet_disable = 1;
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if (!strncmp("force", str, 5))
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hpet_force_user = 1;
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if (!strncmp("verbose", str, 7))
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hpet_verbose = 1;
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}
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return 1;
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}
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@ -119,6 +122,43 @@ int is_hpet_enabled(void)
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}
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EXPORT_SYMBOL_GPL(is_hpet_enabled);
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static void _hpet_print_config(const char *function, int line)
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{
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u32 i, timers, l, h;
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printk(KERN_INFO "hpet: %s(%d):\n", function, line);
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l = hpet_readl(HPET_ID);
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h = hpet_readl(HPET_PERIOD);
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timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
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printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
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l = hpet_readl(HPET_CFG);
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h = hpet_readl(HPET_STATUS);
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printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
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l = hpet_readl(HPET_COUNTER);
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h = hpet_readl(HPET_COUNTER+4);
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printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
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for (i = 0; i < timers; i++) {
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l = hpet_readl(HPET_Tn_CFG(i));
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h = hpet_readl(HPET_Tn_CFG(i)+4);
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printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
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i, l, h);
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l = hpet_readl(HPET_Tn_CMP(i));
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h = hpet_readl(HPET_Tn_CMP(i)+4);
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printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
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i, l, h);
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l = hpet_readl(HPET_Tn_ROUTE(i));
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h = hpet_readl(HPET_Tn_ROUTE(i)+4);
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printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
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i, l, h);
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}
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}
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#define hpet_print_config() \
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do { \
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if (hpet_verbose) \
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_hpet_print_config(__FUNCTION__, __LINE__); \
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} while (0)
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/*
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* When the hpet driver (/dev/hpet) is enabled, we need to reserve
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* timer 0 and timer 1 in case of RTC emulation.
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@ -191,27 +231,37 @@ static struct clock_event_device hpet_clockevent = {
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.rating = 50,
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};
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static void hpet_start_counter(void)
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static void hpet_stop_counter(void)
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{
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unsigned long cfg = hpet_readl(HPET_CFG);
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cfg &= ~HPET_CFG_ENABLE;
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hpet_writel(cfg, HPET_CFG);
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hpet_writel(0, HPET_COUNTER);
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hpet_writel(0, HPET_COUNTER + 4);
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}
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static void hpet_start_counter(void)
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{
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unsigned long cfg = hpet_readl(HPET_CFG);
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cfg |= HPET_CFG_ENABLE;
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hpet_writel(cfg, HPET_CFG);
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}
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static void hpet_restart_counter(void)
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{
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hpet_stop_counter();
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hpet_start_counter();
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}
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static void hpet_resume_device(void)
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{
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force_hpet_resume();
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}
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static void hpet_restart_counter(void)
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static void hpet_resume_counter(void)
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{
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hpet_resume_device();
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hpet_start_counter();
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hpet_restart_counter();
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}
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static void hpet_enable_legacy_int(void)
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@ -259,29 +309,23 @@ static int hpet_setup_msi_irq(unsigned int irq);
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static void hpet_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt, int timer)
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{
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unsigned long cfg, cmp, now;
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unsigned long cfg;
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uint64_t delta;
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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hpet_stop_counter();
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delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
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delta >>= evt->shift;
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now = hpet_readl(HPET_COUNTER);
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cmp = now + (unsigned long) delta;
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cfg = hpet_readl(HPET_Tn_CFG(timer));
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/* Make sure we use edge triggered interrupts */
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cfg &= ~HPET_TN_LEVEL;
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cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
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HPET_TN_SETVAL | HPET_TN_32BIT;
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hpet_writel(cfg, HPET_Tn_CFG(timer));
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/*
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* The first write after writing TN_SETVAL to the
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* config register sets the counter value, the second
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* write sets the period.
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*/
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hpet_writel(cmp, HPET_Tn_CMP(timer));
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udelay(1);
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hpet_writel((unsigned long) delta, HPET_Tn_CMP(timer));
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hpet_start_counter();
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hpet_print_config();
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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@ -308,6 +352,7 @@ static void hpet_set_mode(enum clock_event_mode mode,
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irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
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enable_irq(hdev->irq);
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}
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hpet_print_config();
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break;
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}
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}
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@ -526,6 +571,7 @@ static void hpet_msi_capability_lookup(unsigned int start_timer)
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num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
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num_timers++; /* Value read out starts from 0 */
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hpet_print_config();
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hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
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if (!hpet_devs)
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@ -695,7 +741,7 @@ static struct clocksource clocksource_hpet = {
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.mask = HPET_MASK,
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.shift = HPET_SHIFT,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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.resume = hpet_restart_counter,
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.resume = hpet_resume_counter,
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#ifdef CONFIG_X86_64
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.vread = vread_hpet,
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#endif
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@ -707,7 +753,7 @@ static int hpet_clocksource_register(void)
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cycle_t t1;
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/* Start the counter */
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hpet_start_counter();
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hpet_restart_counter();
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/* Verify whether hpet counter works */
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t1 = read_hpet();
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@ -793,6 +839,7 @@ int __init hpet_enable(void)
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* information and the number of channels
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*/
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id = hpet_readl(HPET_ID);
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hpet_print_config();
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#ifdef CONFIG_HPET_EMULATE_RTC
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/*
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@ -845,6 +892,7 @@ static __init int hpet_late_init(void)
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return -ENODEV;
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hpet_reserve_platform_timers(hpet_readl(HPET_ID));
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hpet_print_config();
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for_each_online_cpu(cpu) {
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hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
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