arm64: dts: ipq8074: qcom: Re-arrange dts nodes based on address
This patch re-arranges ipq8074 device nodes based on node address followed by node names followed by node labels. Suggested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Link: https://lore.kernel.org/r/1586572830-22727-1-git-send-email-sivaprak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Sivaprakash Murugesan
Bjorn Andersson
Родитель
5a307c66a3
Коммит
e8a7fdc505
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@ -24,63 +24,61 @@
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device_type = "memory";
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reg = <0x0 0x40000000 0x0 0x20000000>;
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};
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};
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soc {
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serial@78b3000 {
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status = "ok";
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};
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&blsp1_i2c2 {
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status = "ok";
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};
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spi@78b5000 {
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status = "ok";
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&blsp1_spi1 {
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status = "ok";
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m25p80@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <50000000>;
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};
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};
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serial@78b1000 {
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status = "ok";
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};
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i2c@78b6000 {
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status = "ok";
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};
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dma@7984000 {
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status = "ok";
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};
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nand@79b0000 {
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status = "ok";
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nand@0 {
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reg = <0>;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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nand-bus-width = <8>;
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};
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};
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phy@86000 {
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status = "ok";
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};
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phy@8e000 {
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status = "ok";
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};
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pci@20000000 {
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status = "ok";
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perst-gpio = <&tlmm 58 0x1>;
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};
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pci@10000000 {
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status = "ok";
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perst-gpio = <&tlmm 61 0x1>;
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};
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m25p80@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <50000000>;
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};
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};
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&blsp1_uart3 {
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status = "ok";
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};
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&blsp1_uart5 {
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status = "ok";
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};
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&pcie0 {
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status = "ok";
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perst-gpio = <&tlmm 61 0x1>;
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};
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&pcie1 {
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status = "ok";
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perst-gpio = <&tlmm 58 0x1>;
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};
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&pcie_phy0 {
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status = "ok";
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};
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&pcie_phy1 {
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status = "ok";
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};
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&qpic_bam {
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status = "ok";
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};
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&qpic_nand {
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status = "ok";
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nand@0 {
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reg = <0>;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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nand-bus-width = <8>;
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};
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};
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@ -10,15 +10,111 @@
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model = "Qualcomm Technologies, Inc. IPQ8074";
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compatible = "qcom,ipq8074";
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clocks {
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sleep_clk: sleep_clk {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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#clock-cells = <0>;
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};
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xo: xo {
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compatible = "fixed-clock";
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clock-frequency = <19200000>;
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#clock-cells = <0>;
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};
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};
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cpus {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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next-level-cache = <&L2_0>;
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enable-method = "psci";
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x1>;
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next-level-cache = <&L2_0>;
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};
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CPU2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x2>;
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next-level-cache = <&L2_0>;
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};
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CPU3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x3>;
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next-level-cache = <&L2_0>;
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};
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L2_0: l2-cache {
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compatible = "cache";
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cache-level = <0x2>;
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};
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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soc: soc {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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pcie_phy0: phy@86000 {
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compatible = "qcom,ipq8074-qmp-pcie-phy";
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reg = <0x00086000 0x1000>;
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#phy-cells = <0>;
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clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
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clock-names = "pipe_clk";
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clock-output-names = "pcie20_phy0_pipe_clk";
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resets = <&gcc GCC_PCIE0_PHY_BCR>,
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<&gcc GCC_PCIE0PHY_PHY_BCR>;
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reset-names = "phy",
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"common";
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status = "disabled";
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};
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pcie_phy1: phy@8e000 {
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compatible = "qcom,ipq8074-qmp-pcie-phy";
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reg = <0x0008e000 0x1000>;
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#phy-cells = <0>;
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clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
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clock-names = "pipe_clk";
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clock-output-names = "pcie20_phy1_pipe_clk";
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resets = <&gcc GCC_PCIE1_PHY_BCR>,
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<&gcc GCC_PCIE1PHY_PHY_BCR>;
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reset-names = "phy",
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"common";
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status = "disabled";
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};
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tlmm: pinctrl@1000000 {
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compatible = "qcom,ipq8074-pinctrl";
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reg = <0x1000000 0x300000>;
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reg = <0x01000000 0x300000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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gpio-ranges = <&tlmm 0 0 70>;
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@ -66,102 +162,16 @@
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};
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};
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intc: interrupt-controller@b000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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#interrupt-cells = <0x3>;
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reg = <0xb000000 0x1000>, <0xb002000 0x1000>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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timer@b120000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0xb120000 0x1000>;
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clock-frequency = <19200000>;
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frame@b120000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xb121000 0x1000>,
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<0xb122000 0x1000>;
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};
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frame@b123000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xb123000 0x1000>;
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status = "disabled";
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};
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frame@b124000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xb124000 0x1000>;
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status = "disabled";
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};
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frame@b125000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xb125000 0x1000>;
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status = "disabled";
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};
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frame@b126000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xb126000 0x1000>;
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status = "disabled";
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};
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frame@b127000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xb127000 0x1000>;
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status = "disabled";
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};
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frame@b128000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xb128000 0x1000>;
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status = "disabled";
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};
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};
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gcc: gcc@1800000 {
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compatible = "qcom,gcc-ipq8074";
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reg = <0x1800000 0x80000>;
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reg = <0x01800000 0x80000>;
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#clock-cells = <0x1>;
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#reset-cells = <0x1>;
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};
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blsp1_uart5: serial@78b3000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x78b3000 0x200>;
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interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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pinctrl-0 = <&serial_4_pins>;
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pinctrl-names = "default";
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status = "disabled";
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};
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blsp_dma: dma@7884000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x7884000 0x2b000>;
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reg = <0x07884000 0x2b000>;
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interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "bam_clk";
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@ -171,7 +181,7 @@
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blsp1_uart1: serial@78af000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x78af000 0x200>;
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reg = <0x078af000 0x200>;
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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@ -181,7 +191,7 @@
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blsp1_uart3: serial@78b1000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x78b1000 0x200>;
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reg = <0x078b1000 0x200>;
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interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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@ -194,11 +204,23 @@
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status = "disabled";
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};
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blsp1_uart5: serial@78b3000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x078b3000 0x200>;
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interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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pinctrl-0 = <&serial_4_pins>;
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pinctrl-names = "default";
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status = "disabled";
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};
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blsp1_spi1: spi@78b5000 {
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compatible = "qcom,spi-qup-v2.2.1";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x78b5000 0x600>;
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reg = <0x078b5000 0x600>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
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@ -215,7 +237,7 @@
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compatible = "qcom,i2c-qup-v2.2.1";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x78b6000 0x600>;
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reg = <0x078b6000 0x600>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
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@ -232,7 +254,7 @@
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compatible = "qcom,i2c-qup-v2.2.1";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x78b7000 0x600>;
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reg = <0x078b7000 0x600>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
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@ -245,7 +267,7 @@
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qpic_bam: dma@7984000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x7984000 0x1a000>;
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reg = <0x07984000 0x1a000>;
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interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_QPIC_AHB_CLK>;
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clock-names = "bam_clk";
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@ -256,7 +278,7 @@
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|||
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qpic_nand: nand@79b0000 {
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compatible = "qcom,ipq8074-nand";
|
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reg = <0x79b0000 0x10000>;
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reg = <0x079b0000 0x10000>;
|
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&gcc GCC_QPIC_CLK>,
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@ -272,18 +294,139 @@
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status = "disabled";
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||||
};
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||||
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pcie_phy0: phy@86000 {
|
||||
compatible = "qcom,ipq8074-qmp-pcie-phy";
|
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reg = <0x86000 0x1000>;
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#phy-cells = <0>;
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clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
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clock-names = "pipe_clk";
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clock-output-names = "pcie20_phy0_pipe_clk";
|
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intc: interrupt-controller@b000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
|
||||
#interrupt-cells = <0x3>;
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reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
|
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};
|
||||
|
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resets = <&gcc GCC_PCIE0_PHY_BCR>,
|
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<&gcc GCC_PCIE0PHY_PHY_BCR>;
|
||||
reset-names = "phy",
|
||||
"common";
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
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<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
timer@b120000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
compatible = "arm,armv7-timer-mem";
|
||||
reg = <0x0b120000 0x1000>;
|
||||
clock-frequency = <19200000>;
|
||||
|
||||
frame@b120000 {
|
||||
frame-number = <0>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x0b121000 0x1000>,
|
||||
<0x0b122000 0x1000>;
|
||||
};
|
||||
|
||||
frame@b123000 {
|
||||
frame-number = <1>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x0b123000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@b124000 {
|
||||
frame-number = <2>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x0b124000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@b125000 {
|
||||
frame-number = <3>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x0b125000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@b126000 {
|
||||
frame-number = <4>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x0b126000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@b127000 {
|
||||
frame-number = <5>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x0b127000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@b128000 {
|
||||
frame-number = <6>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x0b128000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
pcie1: pci@10000000 {
|
||||
compatible = "qcom,pcie-ipq8074";
|
||||
reg = <0x10000000 0xf1d
|
||||
0x10000f20 0xa8
|
||||
0x00088000 0x2000
|
||||
0x10100000 0x1000>;
|
||||
reg-names = "dbi", "elbi", "parf", "config";
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <1>;
|
||||
bus-range = <0x00 0xff>;
|
||||
num-lanes = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
phys = <&pcie_phy1>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
ranges = <0x81000000 0 0x10200000 0x10200000
|
||||
0 0x100000 /* downstream I/O */
|
||||
0x82000000 0 0x10300000 0x10300000
|
||||
0 0xd00000>; /* non-prefetchable memory */
|
||||
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 142
|
||||
IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
<0 0 0 2 &intc 0 143
|
||||
IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
<0 0 0 3 &intc 0 144
|
||||
IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
<0 0 0 4 &intc 0 145
|
||||
IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
|
||||
clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
|
||||
<&gcc GCC_PCIE1_AXI_M_CLK>,
|
||||
<&gcc GCC_PCIE1_AXI_S_CLK>,
|
||||
<&gcc GCC_PCIE1_AHB_CLK>,
|
||||
<&gcc GCC_PCIE1_AUX_CLK>;
|
||||
clock-names = "iface",
|
||||
"axi_m",
|
||||
"axi_s",
|
||||
"ahb",
|
||||
"aux";
|
||||
resets = <&gcc GCC_PCIE1_PIPE_ARES>,
|
||||
<&gcc GCC_PCIE1_SLEEP_ARES>,
|
||||
<&gcc GCC_PCIE1_CORE_STICKY_ARES>,
|
||||
<&gcc GCC_PCIE1_AXI_MASTER_ARES>,
|
||||
<&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
|
||||
<&gcc GCC_PCIE1_AHB_ARES>,
|
||||
<&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
|
||||
reset-names = "pipe",
|
||||
"sleep",
|
||||
"sticky",
|
||||
"axi_m",
|
||||
"axi_s",
|
||||
"ahb",
|
||||
"axi_m_sticky";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -291,7 +434,7 @@
|
|||
compatible = "qcom,pcie-ipq8074";
|
||||
reg = <0x20000000 0xf1d
|
||||
0x20000f20 0xa8
|
||||
0x80000 0x2000
|
||||
0x00080000 0x2000
|
||||
0x20100000 0x1000>;
|
||||
reg-names = "dbi", "elbi", "parf", "config";
|
||||
device_type = "pci";
|
||||
|
|
@ -349,148 +492,5 @@
|
|||
"axi_m_sticky";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie_phy1: phy@8e000 {
|
||||
compatible = "qcom,ipq8074-qmp-pcie-phy";
|
||||
reg = <0x8e000 0x1000>;
|
||||
#phy-cells = <0>;
|
||||
clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
|
||||
clock-names = "pipe_clk";
|
||||
clock-output-names = "pcie20_phy1_pipe_clk";
|
||||
|
||||
resets = <&gcc GCC_PCIE1_PHY_BCR>,
|
||||
<&gcc GCC_PCIE1PHY_PHY_BCR>;
|
||||
reset-names = "phy",
|
||||
"common";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie1: pci@10000000 {
|
||||
compatible = "qcom,pcie-ipq8074";
|
||||
reg = <0x10000000 0xf1d
|
||||
0x10000f20 0xa8
|
||||
0x88000 0x2000
|
||||
0x10100000 0x1000>;
|
||||
reg-names = "dbi", "elbi", "parf", "config";
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <1>;
|
||||
bus-range = <0x00 0xff>;
|
||||
num-lanes = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
phys = <&pcie_phy1>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
ranges = <0x81000000 0 0x10200000 0x10200000
|
||||
0 0x100000 /* downstream I/O */
|
||||
0x82000000 0 0x10300000 0x10300000
|
||||
0 0xd00000>; /* non-prefetchable memory */
|
||||
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 142
|
||||
IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
<0 0 0 2 &intc 0 143
|
||||
IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
<0 0 0 3 &intc 0 144
|
||||
IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
<0 0 0 4 &intc 0 145
|
||||
IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
|
||||
clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
|
||||
<&gcc GCC_PCIE1_AXI_M_CLK>,
|
||||
<&gcc GCC_PCIE1_AXI_S_CLK>,
|
||||
<&gcc GCC_PCIE1_AHB_CLK>,
|
||||
<&gcc GCC_PCIE1_AUX_CLK>;
|
||||
clock-names = "iface",
|
||||
"axi_m",
|
||||
"axi_s",
|
||||
"ahb",
|
||||
"aux";
|
||||
resets = <&gcc GCC_PCIE1_PIPE_ARES>,
|
||||
<&gcc GCC_PCIE1_SLEEP_ARES>,
|
||||
<&gcc GCC_PCIE1_CORE_STICKY_ARES>,
|
||||
<&gcc GCC_PCIE1_AXI_MASTER_ARES>,
|
||||
<&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
|
||||
<&gcc GCC_PCIE1_AHB_ARES>,
|
||||
<&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
|
||||
reset-names = "pipe",
|
||||
"sleep",
|
||||
"sticky",
|
||||
"axi_m",
|
||||
"axi_s",
|
||||
"ahb",
|
||||
"axi_m_sticky";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
|
||||
CPU0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
CPU1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
enable-method = "psci";
|
||||
reg = <0x1>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
CPU2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
enable-method = "psci";
|
||||
reg = <0x2>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
CPU3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
enable-method = "psci";
|
||||
reg = <0x3>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
L2_0: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <0x2>;
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
sleep_clk: sleep_clk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
xo: xo {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <19200000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
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